171 lines
4.7 KiB
C++
171 lines
4.7 KiB
C++
/*
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* Interactive disassembler (IDA).
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* Copyright (c) 1990-99 by Ilfak Guilfanov.
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* ALL RIGHTS RESERVED.
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* E-mail: ig@datarescue.com
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*
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* Atmel AVR - 8-bit RISC processor
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*
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*/
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#include "avr.hpp"
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#include "../../ldr/elf/elfr_avr.h"
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//------------------------------------------------------------------------
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static void set_immd_bit(const insn_t &insn, int n)
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{
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set_immd(insn.ea);
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if ( is_defarg(get_flags(insn.ea), n) )
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return;
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switch ( insn.itype )
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{
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case AVR_andi:
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case AVR_ori:
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op_num(insn.ea, n);
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}
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}
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//----------------------------------------------------------------------
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void avr_t::handle_operand(const insn_t &insn, const op_t &x, bool isforced, bool isload)
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{
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switch ( x.type )
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{
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case o_reg:
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case o_phrase:
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break;
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case o_imm:
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if ( !isload )
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goto WRONG_CALL;
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set_immd_bit(insn, x.n);
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if ( op_adds_xrefs(get_flags(insn.ea), x.n) )
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insn.add_off_drefs(x, dr_O, OOF_SIGNED);
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break;
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case o_displ:
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set_immd_bit(insn, x.n);
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if ( !isforced && op_adds_xrefs(get_flags(insn.ea), x.n) )
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{
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int outf = OOF_ADDR|OOFS_NEEDSIGN|OOFW_32;
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ea_t ea = insn.add_off_drefs(x, isload ? dr_R : dr_W, outf);
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if ( ea != BADADDR )
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insn.create_op_data(ea, x);
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}
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break;
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case o_near:
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{
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cref_t ftype = fl_JN;
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ea_t ea = to_ea(insn.cs, x.addr);
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if ( has_insn_feature(insn.itype, CF_CALL) )
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{
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if ( !func_does_return(ea) )
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flow = false;
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ftype = fl_CN;
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}
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insn.add_cref(ea, x.offb, ftype);
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}
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break;
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case o_port:
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if ( ram != BADADDR )
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{
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ea_t ea = ram + x.addr;
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if ( subarch < E_AVR_MACH_TINY )
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ea += 0x20; // skip 32 mapped GPRs for legacy archs
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if ( x.type == o_port )
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{ // verify that the calculated address corresponds to the register name
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const ioport_t *port = find_port(x.addr);
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if ( port == NULL || port->name.empty() )
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break;
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ea_t rev = get_name_ea(BADADDR, port->name.c_str());
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if ( rev != ea )
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break;
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}
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insn.add_dref(ea, x.offb, isload ? dr_R : dr_W);
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}
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break;
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case o_mem:
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{
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ea_t ea = map_data_ea(insn, x);
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insn.add_dref(ea, x.offb, isload ? dr_R : dr_W);
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}
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break;
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default:
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WRONG_CALL:
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if ( insn.itype != AVR_lpm && insn.itype != AVR_elpm )
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warning("%a: %s,%d: bad optype %d", insn.ea, insn.get_canon_mnem(ph), x.n, x.type);
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break;
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}
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}
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//----------------------------------------------------------------------
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static bool may_be_skipped(const insn_t &insn)
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{
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ea_t ea = insn.ea - 1;
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if ( is_code(get_flags(ea)) )
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{
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int code = get_wide_byte(ea);
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switch ( code & 0xFC00 )
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{
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// 0001 00rd dddd rrrr cpse rd, rr 4 Compare, Skip if Equal
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case 0x1000:
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// 1111 110r rrrr xbbb sbrc rr, b Skip if Bit in I/O Register Cleared
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// 1111 111r rrrr xbbb sbrs rr, b Skip if Bit in I/O Register Set
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case 0xFC00:
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return true;
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// 1001 1001 pppp pbbb sbic p, b Skip if Bit in Register Cleared
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// 1001 1011 pppp pbbb sbis p, b Skip if Bit in Register Set
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case 0x9800:
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return (code & 0x0100) != 0;
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}
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}
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return false;
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}
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//----------------------------------------------------------------------
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int avr_t::emu(const insn_t &insn)
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{
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uint32 Feature = insn.get_canon_feature(ph);
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bool flag1 = is_forced_operand(insn.ea, 0);
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bool flag2 = is_forced_operand(insn.ea, 1);
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bool flag3 = is_forced_operand(insn.ea, 2);
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flow = (Feature & CF_STOP) == 0;
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if ( Feature & CF_USE1 ) handle_operand(insn, insn.Op1, flag1, true);
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if ( Feature & CF_USE2 ) handle_operand(insn, insn.Op2, flag2, true);
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if ( Feature & CF_USE3 ) handle_operand(insn, insn.Op3, flag3, true);
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if ( Feature & CF_CHG1 ) handle_operand(insn, insn.Op1, flag1, false);
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if ( Feature & CF_CHG2 ) handle_operand(insn, insn.Op2, flag2, false);
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if ( Feature & CF_CHG3 ) handle_operand(insn, insn.Op3, flag3, false);
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//
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// Determine if the next instruction should be executed
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//
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if ( !flow )
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flow = may_be_skipped(insn);
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if ( segtype(insn.ea) == SEG_XTRN )
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flow = false;
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if ( flow )
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add_cref(insn.ea,insn.ea+insn.size, fl_F);
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return 1;
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}
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//----------------------------------------------------------------------
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int idaapi is_align_insn(ea_t ea)
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{
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insn_t insn;
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decode_insn(&insn, ea);
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switch ( insn.itype )
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{
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case AVR_mov:
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if ( insn.Op1.reg == insn.Op2.reg )
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break;
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default:
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return 0;
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case AVR_nop:
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break;
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}
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return insn.size;
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}
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