olari/sigmaker-ida
1
0
Fork 0
Code Issues Pull Requests Releases Wiki Activity

update

Browse Source
This commit is contained in:
olari
2021-06-05 21:10:25 +03:00
parent 807cffd9de
commit e0e0f2be99
923 changed files with 911857 additions and 15 deletions
Download Patch File Download Diff File Expand all files Collapse all files

1111
idasdk75/module/tlcs900/ana.cpp Normal file
View File

File diff suppressed because it is too large Load Diff

98
idasdk75/module/tlcs900/emu.cpp Normal file
View File

@@ -0,0 +1,98 @@
/*
* TLCS900 processor module for IDA.
* Copyright (c) 1998-2006 Konstantin Norvatoff, <konnor@bk.ru>
* Freeware.
*/
#include "tosh.hpp"
//----------------------------------------------------------------------
void tlcs900_t::handle_operand(const insn_t &insn, const op_t &x, bool is_forced, bool isload)
{
ea_t ea = map_code_ea(insn, x);
flags_t F = get_flags(insn.ea);
switch ( x.type )
{
case o_void:
break;
case o_phrase: // 2 registers or indirect addressing
case o_reg:
break;
case o_displ:
break;
case o_imm:
if ( !isload )
goto badTouch;
set_immd(insn.ea);
if ( !is_forced && is_off(F,x.n) )
insn.add_dref(ea, x.offb, dr_O); // offset!
break;
case o_near:
if ( has_insn_feature(insn.itype,CF_CALL) )
{
insn.add_cref(ea, x.offb, fl_CN);
flow = func_does_return(ea);
}
else
{
insn.add_cref(ea, x.offb, fl_JN);
}
break;
case o_mem:
if ( x.specflag1&URB_LDA )
{
if ( x.specflag1&URB_LDA2 )
{
if ( is_defarg1(F) )
{
set_immd(insn.ea);
if ( !is_forced && is_off(F,x.n) )
insn.add_dref(ea, x.offb, dr_O);
break;
}
}
insn.add_dref(x.addr, x.offb, dr_O);
}
else
{
insn.create_op_data(ea, x);
insn.add_dref(ea, x.offb, isload ? dr_R : dr_W);
}
break;
default:
badTouch:
warning("%a %s,%d: bad optype %d", insn.ea, insn.get_canon_mnem(ph), x.n, x.type);
break;
}
}
//----------------------------------------------------------------------
int tlcs900_t::T900_emu(const insn_t &insn)
{
uint32 Feature = insn.get_canon_feature(ph);
bool flag1 = is_forced_operand(insn.ea, 0);
bool flag2 = is_forced_operand(insn.ea, 1);
flow = ((Feature & CF_STOP) == 0);
if ( Feature & CF_USE1 ) handle_operand(insn, insn.Op1, flag1, true);
if ( Feature & CF_USE2 ) handle_operand(insn, insn.Op2, flag2, true);
if ( Feature & CF_JUMP )
remember_problem(PR_JUMP, insn.ea);
if ( Feature & CF_CHG1 ) handle_operand(insn, insn.Op1, flag1, false);
if ( Feature & CF_CHG2 ) handle_operand(insn, insn.Op2, flag2, false);
if ( flow )
add_cref(insn.ea, insn.ea+insn.size, fl_F);
return 1;
}

145
idasdk75/module/tlcs900/ins.cpp Normal file
View File

@@ -0,0 +1,145 @@
/*
* TLCS900 processor module for IDA.
* Copyright (c) 1998-2006 Konstantin Norvatoff, <konnor@bk.ru>
* Freeware.
*/
#include "tosh.hpp"
// Attention!!! Word instruction must be followed
// byte instruction, used in ana.cpp
const instruc_t Instructions[] =
{
{ "", 0 }, // Unknown Operation
{ "LD", CF_USE1|CF_CHG1|CF_USE2 }, // Load data
{ "LDW", CF_USE1|CF_CHG1|CF_USE2 }, // Load data
{ "PUSH", CF_USE1 }, // Push data
{ "PUSHW", CF_USE1 }, // Push data
{ "POP", CF_USE1|CF_CHG1 }, // pop data
{ "POPW", CF_USE1|CF_CHG1 }, // pop data
{ "LDA", CF_USE1|CF_CHG1|CF_USE2 }, // load data from mem
{ "LDAR", CF_USE1|CF_CHG1|CF_USE2 }, // load data from mem rel.
{ "EX", CF_USE1|CF_CHG1|CF_USE2|CF_CHG2 }, // xchg
{ "MIRR", CF_USE1|CF_CHG1 }, // mirror
{ "LDI", CF_USE1|CF_USE2|CF_CHG1|CF_CHG2 }, // copy
{ "LDIW", CF_USE1|CF_USE2|CF_CHG1|CF_CHG2 }, // copy
{ "LDIR", CF_USE1|CF_USE2|CF_CHG1|CF_CHG2 }, // copy
{ "LDIRW", CF_USE1|CF_USE2|CF_CHG1|CF_CHG2 }, // copy
{ "LDD", CF_USE1|CF_USE2|CF_CHG1|CF_CHG2 }, // copy
{ "LDDW", CF_USE1|CF_USE2|CF_CHG1|CF_CHG2 }, // copy
{ "LDDR", CF_USE1|CF_USE2|CF_CHG1|CF_CHG2 }, // copy
{ "LDDRW", CF_USE1|CF_USE2|CF_CHG1|CF_CHG2 }, // copy
{ "CPI", CF_USE1|CF_USE2|CF_CHG1|CF_CHG2 }, // compare
{ "CPIR", CF_USE1|CF_USE2|CF_CHG1|CF_CHG2 }, // compare
{ "CPD", CF_USE1|CF_USE2|CF_CHG1|CF_CHG2 }, // compare
{ "CPDR", CF_USE1|CF_USE2|CF_CHG1|CF_CHG2 }, // compare
{ "ADD", CF_USE1|CF_CHG1|CF_USE2 },
{ "ADDW", CF_USE1|CF_CHG1|CF_USE2 },
{ "ADC", CF_USE1|CF_CHG1|CF_USE2 },
{ "ADCW", CF_USE1|CF_CHG1|CF_USE2 },
{ "SUB", CF_USE1|CF_CHG1|CF_USE2 },
{ "SUBW", CF_USE1|CF_CHG1|CF_USE2 },
{ "SBC", CF_USE1|CF_CHG1|CF_USE2 },
{ "SBCW", CF_USE1|CF_CHG1|CF_USE2 },
{ "CP", CF_USE1|CF_USE2 }, // cmp
{ "CPW", CF_USE1|CF_USE2 }, // cmp
{ "INC", CF_USE1|CF_USE2|CF_CHG2 },
{ "INCW", CF_USE1|CF_USE2|CF_CHG2 },
{ "DEC", CF_USE1|CF_USE2|CF_CHG2 },
{ "DECW", CF_USE1|CF_USE2|CF_CHG2 },
{ "NEG", CF_USE1|CF_CHG1 },
{ "EXTZ", CF_USE1|CF_CHG1 },
{ "EXTS", CF_USE1|CF_CHG1 },
{ "DAA", CF_USE1|CF_CHG1 },
{ "PAA", CF_USE1|CF_CHG1 },
{ "CPL", CF_USE1|CF_CHG1 },
{ "MUL", CF_USE1|CF_CHG1|CF_USE2 },
{ "MULS", CF_USE1|CF_CHG1|CF_USE2 },
{ "DIV", CF_USE1|CF_CHG1|CF_USE2 },
{ "DIVS", CF_USE1|CF_CHG1|CF_USE2 },
{ "MULA", CF_USE1|CF_CHG1 }, // rr+=(XDE)*(XHL--)
{ "MINC1", CF_USE1|CF_USE2|CF_CHG2 },
{ "MINC2", CF_USE1|CF_USE2|CF_CHG2 },
{ "MINC4", CF_USE1|CF_USE2|CF_CHG2 },
{ "MDEC1", CF_USE1|CF_USE2|CF_CHG2 },
{ "MDEC2", CF_USE1|CF_USE2|CF_CHG2 },
{ "MDEC4", CF_USE1|CF_USE2|CF_CHG2 },
{ "AND", CF_USE1|CF_CHG1|CF_USE2 },
{ "ANDW", CF_USE1|CF_CHG1|CF_USE2 },
{ "OR", CF_USE1|CF_CHG1|CF_USE2 },
{ "ORW", CF_USE1|CF_CHG1|CF_USE2 },
{ "XOR", CF_USE1|CF_CHG1|CF_USE2 },
{ "XORW", CF_USE1|CF_CHG1|CF_USE2 },
{ "LDCF", CF_USE1|CF_USE2 },
{ "STCF", CF_USE1|CF_USE2|CF_CHG2 },
{ "ANDCF", CF_USE1|CF_USE2 },
{ "ORCF", CF_USE1|CF_USE2 },
{ "XORCF", CF_USE1|CF_USE2 },
{ "RCF", 0 },
{ "SCF", 0 },
{ "CCF", 0 },
{ "ZCF", 0 },
{ "BIT", CF_USE1|CF_USE2 },
{ "RES", CF_USE1|CF_USE2|CF_CHG2 },
{ "SET", CF_USE1|CF_USE2|CF_CHG2 },
{ "CHG", CF_USE1|CF_USE2|CF_CHG2 },
{ "TSET", CF_USE1|CF_USE2|CF_CHG2 },
{ "BS1F", CF_USE1|CF_CHG1|CF_USE2 },
{ "BS1B", CF_USE1|CF_CHG1|CF_USE2 },
{ "NOP", 0 },
{ "EI", CF_USE1 },
{ "DI", 0 },
{ "SWI", CF_USE1|CF_CALL }, // interrupt
{ "HALT", CF_STOP },
{ "LDC", CF_USE1|CF_USE2 }, // actually changes
{ "LDX", CF_USE1|CF_CHG1|CF_USE2 },
{ "LINK", CF_USE1|CF_CHG1|CF_USE2|CF_HLL },
{ "UNLK", CF_USE1|CF_CHG1|CF_HLL },
{ "LDF", CF_USE1 }, // set reg bank
{ "INCF", 0 },
{ "DECF", 0 },
{ "SCC", CF_USE1|CF_USE2|CF_CHG2 },
{ "RLC", CF_USE1|CF_USE2|CF_CHG2 },
{ "RLC", CF_USE1|CF_CHG1 },
{ "RLCW", CF_USE1|CF_CHG2 },
{ "RRC", CF_USE1|CF_USE2|CF_CHG2 },
{ "RRC", CF_USE1|CF_CHG1 },
{ "RRCW", CF_USE1|CF_CHG2 },
{ "RL", CF_USE1|CF_USE2|CF_CHG2 },
{ "RL", CF_USE1|CF_CHG1 },
{ "RLW", CF_USE1|CF_CHG2 },
{ "RR", CF_USE1|CF_USE2|CF_CHG2 },
{ "RR", CF_USE1|CF_CHG1 },
{ "RRW", CF_USE1|CF_CHG2 },
{ "SLA", CF_USE1|CF_USE2|CF_CHG2 },
{ "SLA", CF_USE1|CF_CHG1 },
{ "SLAW", CF_USE1|CF_CHG2 },
{ "SRA", CF_USE1|CF_USE2|CF_CHG2 },
{ "SRA", CF_USE1|CF_CHG1 },
{ "SRAW", CF_USE1|CF_CHG2 },
{ "SLL", CF_USE1|CF_USE2|CF_CHG2 },
{ "SLL", CF_USE1|CF_CHG1 },
{ "SLLW", CF_USE1|CF_CHG2 },
{ "SRL", CF_USE1|CF_USE2|CF_CHG2 },
{ "SRL", CF_USE1|CF_CHG1 },
{ "SRLW", CF_USE1|CF_CHG2 },
{ "RLD", CF_USE1|CF_CHG1|CF_USE2|CF_CHG2 },
{ "RRD", CF_USE1|CF_CHG1|CF_USE2|CF_CHG2 },
{ "JP", CF_USE1|CF_JUMP|CF_STOP },
{ "JP", CF_USE1|CF_USE2|CF_JUMP },
{ "JR", CF_USE1|CF_USE2|CF_JUMP|CF_STOP },
{ "JR", CF_USE1|CF_USE2|CF_JUMP },
{ "JRL", CF_USE1|CF_USE2|CF_JUMP|CF_STOP },
{ "JRL", CF_USE1|CF_USE2|CF_JUMP },
{ "CALL", CF_USE1|CF_USE2|CF_CALL },
{ "CALR", CF_USE1|CF_CALL },
{ "DJNZ", CF_USE1|CF_CHG1|CF_USE2|CF_JUMP },
{ "RET", CF_STOP },
{ "RET", CF_USE1 },
{ "RETD", CF_USE1|CF_STOP },
{ "RETI", CF_STOP|CF_USE1 },
{ "MAX", 0 }, // from IAR
{ "NORMAL", 0 } // from IAR
};
CASSERT(qnumber(Instructions) == T900_last);

149
idasdk75/module/tlcs900/ins.hpp Normal file
View File

@@ -0,0 +1,149 @@
/*
* TLCS900 processor module for IDA.
* Copyright (c) 1998-2006 Konstantin Norvatoff, <konnor@bk.ru>
* Freeware.
*/
#ifndef __INSTRS_HPP
#define __INSTRS_HPP
// List of instructions
extern const instruc_t Instructions[];
//
enum nameNum ENUM_SIZE(uint16)
{
T900_null = 0, // Unknown Operation
T900_ld,
T900_ldw,
T900_push,
T900_pushw,
T900_pop,
T900_popw,
T900_lda,
T900_ldar,
T900_ex,
T900_mirr,
T900_ldi,
T900_ldiw,
T900_ldir,
T900_ldirw,
T900_ldd,
T900_lddw,
T900_lddr,
T900_lddrw,
T900_cpi,
T900_cpir,
T900_cpd,
T900_cpdr,
T900_add,
T900_addw,
T900_adc,
T900_adcw,
T900_sub,
T900_subw,
T900_sbc,
T900_sbcw,
T900_cp,
T900_cpw,
T900_inc,
T900_incw,
T900_dec,
T900_decw,
T900_neg,
T900_extz,
T900_exts,
T900_daa,
T900_paa,
T900_cpl,
T900_mul,
T900_muls,
T900_div,
T900_divs,
T900_mula,
T900_minc1,
T900_minc2,
T900_minc4,
T900_mdec1,
T900_mdec2,
T900_mdec4,
T900_and,
T900_andw,
T900_or,
T900_orw,
T900_xor,
T900_xorw,
T900_ldcf,
T900_stcf,
T900_andcf,
T900_orcf,
T900_xorcf,
T900_rcf,
T900_scf,
T900_ccf,
T900_zcf,
T900_bit,
T900_res,
T900_set,
T900_chg,
T900_tset,
T900_bs1f,
T900_bs1b,
T900_nop,
T900_ei,
T900_di,
T900_swi,
T900_halt,
T900_ldc,
T900_ldx,
T900_link,
T900_unlk,
T900_ldf,
T900_incf,
T900_decf,
T900_scc,
T900_rlc,
T900_rlc_mem,
T900_rlcw_mem,
T900_rrc,
T900_rrc_mem,
T900_rrcw_mem,
T900_rl,
T900_rl_mem,
T900_rlw_mem,
T900_rr,
T900_rr_mem,
T900_rrw_mem,
T900_sla,
T900_sla_mem,
T900_slaw_mem,
T900_sra,
T900_sra_mem,
T900_sraw_mem,
T900_sll,
T900_sll_mem,
T900_sllw_mem,
T900_srl,
T900_srl_mem,
T900_srlw_mem,
T900_rld,
T900_rrd,
T900_jp,
T900_jp_cond,
T900_jr,
T900_jr_cond,
T900_jrl,
T900_jrl_cond,
T900_call,
T900_calr,
T900_djnz,
T900_ret,
T900_ret_cond,
T900_retd,
T900_reti,
T900_max,
T900_normal,
T900_last
};
#endif

46
idasdk75/module/tlcs900/makefile Normal file
View File

@@ -0,0 +1,46 @@
PROC=tlcs900
CONFIGS=tlcs900.cfg
include ../module.mak
# MAKEDEP dependency list ------------------
$(F)ana$(O) : $(I)auto.hpp $(I)bitrange.hpp $(I)bytes.hpp \
$(I)config.hpp $(I)diskio.hpp $(I)entry.hpp $(I)fpro.h \
$(I)funcs.hpp $(I)ida.hpp $(I)idp.hpp $(I)kernwin.hpp \
$(I)lines.hpp $(I)llong.hpp $(I)loader.hpp $(I)nalt.hpp \
$(I)name.hpp $(I)netnode.hpp $(I)offset.hpp $(I)pro.h \
$(I)problems.hpp $(I)range.hpp $(I)segment.hpp \
$(I)ua.hpp $(I)xref.hpp ../idaidp.hpp ../iohandler.hpp \
ana.cpp ins.hpp tosh.hpp
$(F)emu$(O) : $(I)auto.hpp $(I)bitrange.hpp $(I)bytes.hpp \
$(I)config.hpp $(I)diskio.hpp $(I)entry.hpp $(I)fpro.h \
$(I)funcs.hpp $(I)ida.hpp $(I)idp.hpp $(I)kernwin.hpp \
$(I)lines.hpp $(I)llong.hpp $(I)loader.hpp $(I)nalt.hpp \
$(I)name.hpp $(I)netnode.hpp $(I)offset.hpp $(I)pro.h \
$(I)problems.hpp $(I)range.hpp $(I)segment.hpp \
$(I)ua.hpp $(I)xref.hpp ../idaidp.hpp ../iohandler.hpp \
emu.cpp ins.hpp tosh.hpp
$(F)ins$(O) : $(I)auto.hpp $(I)bitrange.hpp $(I)bytes.hpp \
$(I)config.hpp $(I)diskio.hpp $(I)entry.hpp $(I)fpro.h \
$(I)funcs.hpp $(I)ida.hpp $(I)idp.hpp $(I)kernwin.hpp \
$(I)lines.hpp $(I)llong.hpp $(I)loader.hpp $(I)nalt.hpp \
$(I)name.hpp $(I)netnode.hpp $(I)offset.hpp $(I)pro.h \
$(I)problems.hpp $(I)range.hpp $(I)segment.hpp \
$(I)ua.hpp $(I)xref.hpp ../idaidp.hpp ../iohandler.hpp \
ins.cpp ins.hpp tosh.hpp
$(F)out$(O) : $(I)auto.hpp $(I)bitrange.hpp $(I)bytes.hpp \
$(I)config.hpp $(I)diskio.hpp $(I)entry.hpp $(I)fpro.h \
$(I)funcs.hpp $(I)ida.hpp $(I)idp.hpp $(I)kernwin.hpp \
$(I)lines.hpp $(I)llong.hpp $(I)loader.hpp $(I)nalt.hpp \
$(I)name.hpp $(I)netnode.hpp $(I)offset.hpp $(I)pro.h \
$(I)problems.hpp $(I)range.hpp $(I)segment.hpp \
$(I)ua.hpp $(I)xref.hpp ../idaidp.hpp ../iohandler.hpp \
ins.hpp out.cpp tosh.hpp
$(F)reg$(O) : $(I)auto.hpp $(I)bitrange.hpp $(I)bytes.hpp \
$(I)config.hpp $(I)diskio.hpp $(I)entry.hpp $(I)fpro.h \
$(I)funcs.hpp $(I)ida.hpp $(I)idp.hpp $(I)kernwin.hpp \
$(I)lines.hpp $(I)llong.hpp $(I)loader.hpp $(I)nalt.hpp \
$(I)name.hpp $(I)netnode.hpp $(I)offset.hpp $(I)pro.h \
$(I)problems.hpp $(I)range.hpp $(I)segment.hpp \
$(I)segregs.hpp $(I)ua.hpp $(I)xref.hpp ../idaidp.hpp \
../iohandler.hpp ins.hpp reg.cpp tosh.hpp

306
idasdk75/module/tlcs900/out.cpp Normal file
View File

@@ -0,0 +1,306 @@
/*
* TLCS900 processor module for IDA.
* Copyright (c) 1998-2006 Konstantin Norvatoff, <konnor@bk.ru>
* Freeware.
*/
#include "tosh.hpp"
// phrase
static const char *const phrases[] =
{
// empty
"",
// conditions
"F", "LT", "LE", "ULE", "PE", "MI", "Z", "C",
"(T)", "GE", "GT", "UGT", "PO", "PL", "NZ", "NC",
// special register
"F", "F'",
// misc
"SR", "PC"
};
// register's name
static const uchar reg_byte[8] =
{
rW, rA, rB, rC, rD, rE, rH, rL
};
static const uchar reg_word[8] =
{
rWA, rBC, rDE, rHL, rIX, rIY, rIZ, rSP
};
static const uchar reg_long[8] =
{
rXWA, rXBC, rXDE, rXHL, rXIX, rXIY, rXIZ, rXSP
};
static const uchar reg_ib[8] =
{
rIXL, rIXH, rIYL, rIYH, rIZL, rIZH, rSPL, rSPH
};
//----------------------------------------------------------------------
class out_T900_t : public outctx_t
{
out_T900_t(void) = delete; // not used
public:
void OutReg(size_t rgnum, uchar size);
void OutVarName(const op_t &x);
bool out_operand(const op_t &x);
void out_insn(void);
};
CASSERT(sizeof(out_T900_t) == sizeof(outctx_t));
DECLARE_OUT_FUNCS_WITHOUT_OUTMNEM(out_T900_t)
//----------------------------------------------------------------------
void out_T900_t::OutReg(size_t rgnum, uchar size)
{
ushort reg_name=0; // main phrase
if ( size != dt_dword )
{
// if 32 - w/o prefixes
if ( rgnum&2 ) // prefix Q
out_symbol('Q');
else if ( rgnum < 0xD0 ) // need R ?
out_symbol('R');
}
// register name
switch ( size )
{
case dt_byte:
if ( (rgnum&0xF0) != 0xF0 )
// general register
reg_name=reg_byte[((1-rgnum)&1)|((rgnum>>1)&6)];
else
// byte I*- regs
reg_name=reg_ib[(rgnum&1)|((rgnum>>1)&6)];
break;
case dt_word:
if ( (rgnum&0xF0) != 0xF0 )
// general word regs
reg_name=reg_word[(rgnum>>2)&3];
else
// high regs
reg_name=reg_word[((rgnum>>2)&3)+4];
break;
case dt_dword:
if ( (rgnum&0xF0) != 0xF0 )
// general double word regs
reg_name=reg_long[(rgnum>>2)&3];
else
// high regs
reg_name=reg_long[((rgnum>>2)&3)+4];
break;
case 255: // special
reg_name=ushort(rgnum);
break;
}
if ( reg_name >= ph.regs_num )
{
out_symbol('?');
msg("Bad Register Ref=%x, size=%x\n", (int)reg_name, (int)size);
}
else
{
out_register(ph.reg_names[reg_name]);
}
// postfix
if ( (rgnum&0xF0) == 0xD0 )
out_symbol('\'');
else if ( rgnum < 0xD0 ) // or banki name
out_symbol('0'+((rgnum>>4)&0xF));
}
//----------------------------------------------------------------------
// label name
void out_T900_t::OutVarName(const op_t &x)
{
ea_t toea = map_code_ea(insn, x);
if ( !out_name_expr(x, toea, x.addr) )
{
out_value(x, OOF_ADDR | OOF_NUMBER | OOFS_NOSIGN | OOFW_32);
remember_problem(PR_NONAME, insn.ea);
}
}
//----------------------------------------------------------------------
bool out_T900_t::out_operand(const op_t &x)
{
switch ( x.type )
{
case o_reg:
OutReg((size_t)x.value, x.dtype);
break;
case o_phrase:
out_line(phrases[x.phrase]);
break;
case o_imm:
ImmOut:
refinfo_t ri;
// micro bug-fix
if ( get_refinfo(&ri, insn.ea, x.n) )
{
if ( ri.flags == REF_OFF16 )
set_refinfo(insn.ea, x.n, REF_OFF32, ri.target, ri.base, ri.tdelta);
// msg("Exec OFF16_Op Fix AT:%a Flags=%x, Target=%a, Base=%a, Delta=%a\n",
// insn.ea, ri.flags, ri.target, ri.base, uval_t(ri.tdelta));
}
out_value(x, OOFS_NOSIGN | OOFW_IMM);
break;
case o_mem:
case o_near:
if ( x.specflag1&URB_LDA2 && is_defarg1(F) )
goto ImmOut;
if ( !(x.specflag1&URB_LDA) )
out_symbol('(');
OutVarName(x);
if ( !(x.specflag1&URB_LDA) )
out_symbol(')');
break;
case o_displ: // open paren
if ( !(x.specflag1&URB_LDA) )
out_symbol('(');
// with reg?
if ( x.reg != rNULLReg )
{
// dec?
if ( x.specflag2 & URB_DECR )
out_symbol('-');
// base eg
OutReg(x.reg, 2); // 32 bit always
// dec
if ( x.specflag2 & URB_DCMASK )
{
if ( (x.specflag2&URB_DECR) == 0 )
out_symbol('+');
out_symbol(':');
out_symbol('0'+(x.specflag2&7));
}
// singleton dec
if ( x.specflag2 & URB_UDEC )
out_symbol('-');
if ( x.specflag2 & URB_UINC )
out_symbol('+');
// offset?
if ( x.offb != 0 )
{
out_symbol('+');
if ( is_off(F, x.n) )
OutVarName(x);
else
out_value(x, OOF_ADDR | OOF_NUMBER | OOFS_NOSIGN | OOFW_32);
}
// additional reg?
if ( x.specval_shorts.low != rNULLReg )
{
out_symbol('+');
OutReg(x.specval_shorts.low, x.specflag1&URB_WORD ? dt_word : dt_byte);
}
}
// closed paren
if ( !(x.specflag1&URB_LDA) )
out_symbol(')');
break;
case o_void:
return 0;
default:
warning("out: %a: bad optype %d", insn.ea, x.type);
break;
}
return 1;
}
//----------------------------------------------------------------------
void out_T900_t::out_insn(void)
{
out_mnemonic();
if ( insn.Op1.type != o_void )
out_one_operand(0);
if ( insn.Op2.type != o_void )
{
out_symbol(',');
out_char(' ');
out_one_operand(1);
}
// imm data if any
out_immchar_cmts();
flush_outbuf();
}
//--------------------------------------------------------------------------
void tlcs900_t::T900_header(outctx_t &ctx)
{
ctx.gen_header(GH_PRINT_ALL_BUT_BYTESEX, ioh.device.c_str(), ioh.deviceparams.c_str());
}
//--------------------------------------------------------------------------
//lint -esym(1764, ctx) could be made const
//lint -esym(818, Sarea) could be made const
void tlcs900_t::T900_segstart(outctx_t &ctx, segment_t *Sarea) const
{
const char *SegType = Sarea->type == SEG_CODE ? "CSEG"
: Sarea->type == SEG_DATA ? "DSEG"
: "RSEG";
// "RSEG <NAME>"
qstring sn;
get_visible_segm_name(&sn, Sarea);
ctx.gen_printf(-1, "%s %s ", SegType, sn.c_str());
// non-zero offset - "ORG XXXX"
if ( (inf_get_outflags() & OFLG_GEN_ORG) != 0 )
{
ea_t org = ctx.insn_ea - get_segm_base(Sarea);
if ( org != 0 )
{
char bufn[MAX_NUMBUF];
btoa(bufn, sizeof(bufn), org);
ctx.gen_printf(-1, "%s %s", ash.origin, bufn);
}
}
}
//--------------------------------------------------------------------------
void tlcs900_t::T900_footer(outctx_t &ctx) const
{
if ( ash.end != NULL )
{
ctx.gen_empty_line();
ctx.out_line(ash.end, COLOR_ASMDIR);
qstring name;
if ( get_colored_name(&name, inf_get_start_ea()) > 0 )
{
size_t i = strlen(ash.end);
do
ctx.out_char(' ');
while ( ++i < 8 );
ctx.out_line(name.begin());
}
ctx.flush_outbuf(DEFAULT_INDENT);
}
else
{
ctx.gen_cmt_line("end of file");
}
}
//--------------------------------------------------------------------------
void idaapi T900_data(outctx_t &ctx, bool analyze_only)
{
ea_t ea = ctx.insn_ea;
// micro bug-fix
refinfo_t ri;
if ( get_refinfo(&ri, ea, 0) && ri.flags == REF_OFF16 )
set_refinfo(ea, 0, REF_OFF32, ri.target, ri.base, ri.tdelta);
ctx.out_data(analyze_only);
}

248
idasdk75/module/tlcs900/reg.cpp Normal file
View File

@@ -0,0 +1,248 @@
/*
* TLCS900 processor module for IDA.
* Copyright (c) 1998-2006 Konstantin Norvatoff, <konnor@bk.ru>
* Freeware.
*/
#include "tosh.hpp"
#include <diskio.hpp>
#include <segregs.hpp>
//--------------------------------------------------------------------------
// registers
static const char *const RegNames[] =
{
// zero reg
"",
// byte regs
"W", "A", "B", "C", "D", "E", "H", "L",
// word regs
"WA", "BC", "DE", "HL", "IX", "IY", "IZ", "SP",
// Double word regs
"XWA", "XBC", "XDE", "XHL", "XIX", "XIY", "XIZ", "XSP",
// strange regs
"IXL", "IXH", "IYL", "IYH", "IZL", "IZH", "SPL", "SPH",
// pesudo-seg regs
"cs", "ds"
};
//----------------------------------------------------------------------
// This old-style callback only returns the processor module object.
static ssize_t idaapi notify(void *, int msgid, va_list)
{
if ( msgid == processor_t::ev_get_procmod )
return size_t(new tlcs900_t);
return 0;
}
//----------------------------------------------------------------------
ssize_t idaapi tlcs900_t::on_event(ssize_t msgid, va_list va)
{
int code = 0;
switch ( msgid )
{
case processor_t::ev_init:
inf_set_be(false);
inf_set_gen_lzero(true);
helper.create("$ TLCS900");
break;
case processor_t::ev_term:
ioh.ports.clear();
break;
case processor_t::ev_newfile:
{
char cfgfile[QMAXFILE];
ioh.get_cfg_filename(cfgfile, sizeof(cfgfile));
iohandler_t::parse_area_line0_t cb(ioh);
if ( choose_ioport_device2(&ioh.device, cfgfile, &cb) )
ioh.set_device_name(ioh.device.c_str(), IORESP_ALL);
}
break;
case processor_t::ev_ending_undo:
case processor_t::ev_oldfile:
ioh.restore_device();
break;
case processor_t::ev_creating_segm:
{
segment_t *s = va_arg(va, segment_t *);
// Set default value of DS register for all segments
set_default_dataseg(s->sel);
}
break;
case processor_t::ev_out_header:
{
outctx_t *ctx = va_arg(va, outctx_t *);
T900_header(*ctx);
return 1;
}
case processor_t::ev_out_footer:
{
outctx_t *ctx = va_arg(va, outctx_t *);
T900_footer(*ctx);
return 1;
}
case processor_t::ev_out_segstart:
{
outctx_t *ctx = va_arg(va, outctx_t *);
segment_t *seg = va_arg(va, segment_t *);
T900_segstart(*ctx, seg);
return 1;
}
case processor_t::ev_ana_insn:
{
insn_t *out = va_arg(va, insn_t *);
return T900_ana(out);
}
case processor_t::ev_emu_insn:
{
const insn_t *insn = va_arg(va, const insn_t *);
return T900_emu(*insn) ? 1 : -1;
}
case processor_t::ev_out_insn:
{
outctx_t *ctx = va_arg(va, outctx_t *);
out_insn(*ctx);
return 1;
}
case processor_t::ev_out_operand:
{
outctx_t *ctx = va_arg(va, outctx_t *);
const op_t *op = va_arg(va, const op_t *);
return out_opnd(*ctx, *op) ? 1 : -1;
}
case processor_t::ev_out_data:
{
outctx_t *ctx = va_arg(va, outctx_t *);
bool analyze_only = va_argi(va, bool);
T900_data(*ctx, analyze_only);
return 1;
}
default:
break;
}
return code;
}
//-----------------------------------------------------------------------
// PseudoSam
//-----------------------------------------------------------------------
static const asm_t pseudosam =
{
AS_COLON | AS_UDATA | ASH_HEXF3,
0,
"Generic IAR-style assembler",
0,
NULL,
"org",
"end",
";",
'"',
'\'',
"\\\"'",
"db", // ascii string directive
"DB", // byte directive
"DW", // word directive
"DL", // dword (4 bytes)
NULL, // qword (8 bytes)
NULL, // oword (16 bytes)
NULL, // float (4 bytes)
NULL, // double (8 bytes)
NULL, // tbyte (10/12 bytes)
NULL, // packed decimal real
"#d dup(#v)", // arrays (#h,#d,#v,#s(...)
"db ?", // uninited arrays
".equ", // equ
NULL, // seg prefix
"$",
NULL,
NULL,
NULL, // public
NULL, // weak
NULL, // extrn
NULL, // comm
NULL,
"align",
'(', // lbrace
')', // rbrace
NULL, // mod
NULL, // and
NULL, // or
NULL, // xor
NULL, // not
NULL, // shl
NULL, // shr
NULL, // sizeof
};
static const asm_t *const asms[] = { &pseudosam, NULL };
//-----------------------------------------------------------------------
#define FAMILY "Toshiba TLCS-900 series:"
static const char *const shnames[] = { "TLCS900", NULL };
static const char *const lnames[] = { FAMILY"Toshiba TLCS900", NULL };
//--------------------------------------------------------------------------
static const uchar retcode_1[] = { 0x0E }; // ret
static const uchar retcode_2[] = { 0x0F }; // ret d
static const uchar retcode_3[] = { 0x07 }; // reti
static const bytes_t retcodes[] =
{
{ sizeof(retcode_1), retcode_1 },
{ sizeof(retcode_2), retcode_2 },
{ sizeof(retcode_3), retcode_3 },
{ 0, NULL }
};
//-----------------------------------------------------------------------
// Processor Definition
//-----------------------------------------------------------------------
processor_t LPH =
{
IDP_INTERFACE_VERSION, // version
PLFM_TLCS900, // id
// flag
PR_USE32
| PR_BINMEM
| PR_SEGTRANS
| PR_DEFSEG32,
// flag2
0,
8, // 8 bits in a byte for code segments
8, // 8 bits in a byte
shnames,
lnames,
asms,
notify,
RegNames, // Regsiter names
qnumber(RegNames), // Number of registers
rVcs, rVds,
2, // size of a segment register
rVcs, rVds,
NULL,
retcodes,
T900_null, T900_last,
Instructions, // instruc
3, // tbyte - 24 bit
{0,0,0,0},
0,
NULL,
};

287
idasdk75/module/tlcs900/tlcs900.cfg Normal file
View File

@@ -0,0 +1,287 @@
; The format of the input file:
; each device definition begins with a line like this:
;
; .devicename
;
; after it go the port definitions in this format:
;
; portname address
;
; the bit definitions (optional) are represented like this:
;
; portname.bitname bitnumber
;
; lines beginning with a space are ignored.
; comment lines should be started with ';' character.
;
; the default device is specified at the start of the file
;
; .default device_name
;
; all lines non conforming to the format are passed to the callback function
;
; Toshiba TLCS900 SPECIFIC LINES
;------------------------
;
; the processor definition may include the memory configuration.
; the line format is:
; area CLASS AREA-NAME START:END
;
; where CLASS is anything, but please use one of CODE, DATA, BSS
; START and END are addresses, the end address is not included
; Interrupt vectors are declared in the following way:
; entry NAME ADDRESS COMMENT
.default TMP93CS42A
.TMP93CS42A
; MEMORY MAP
area DATA FSR 0x0000:0x0080 Special Function Register
area DATA IRAM 0x0080:0x0880 Internal High-Speed RAM
area CODE IROM 0x8000:0x10000 Internal ROM
; Interrupt and reset vector assignments
interrupt RESET_ 0x8000 RESET
interrupt SWI1_ 0x8004 SWI1
interrupt SWI2_ 0x8008 SWI2
interrupt SWI3_ 0x800C SWI3
interrupt SWI4_ 0x8010 SWI4
interrupt SWI5_ 0x8014 SWI5
interrupt SWI6_ 0x8018 SWI6
interrupt SWI7_ 0x801C SWI7
interrupt NMI_ 0x8020 NMI
interrupt INTWD_ 0x8024 INTWD
interrupt INT0_ 0x8028 INT0
interrupt INT4_ 0x802C INT4
interrupt INT5_ 0x8030 INT5
interrupt INT6_ 0x8034 INT6
interrupt INT7_ 0x8038 INT7
interrupt INTT0_ 0x8040 INTT0
interrupt INTT1_ 0x8044 INTT1
interrupt INT8_ 0x8048 INT8
interrupt INT9_ 0x804C INT9
interrupt INTR4_ 0x8050 INTR4
interrupt INTR5_ 0x8054 INTR5
interrupt INTR6_ 0x8058 INTR6
interrupt INTR7_ 0x805C INTR7
interrupt INTRX0_ 0x8060 INTRX0
interrupt INTTX0_ 0x8064 INTTX0
interrupt INTRX1_ 0x8068 INTRX1
interrupt INTTX1_ 0x806C INTTX1
interrupt INTAD_ 0x8070 INTAD
; INPUT/OUTPUT
P0 0x00 Port 0
P1 0x01 Port 1
P0CR 0x02 Port 0 Control
P1CR 0x04 Port 1 Control
P1FC 0x05 Port 1 Function
P2 0x06 Port 2
P3 0x07 Port 3
P2CR 0x08 Port 2 Control
P2FC 0x09 Port 2 Function
P3CR 0x0A Port 3 Control
P3FC 0x0B Port 3 Function
P4 0x0C Port 4
P5 0x0D Port 5
P4CR 0x0E Port 4 Control
P4FC 0x10 Port 4 Function
P6 0x12 Port 6
P7 0x13 Port 7
P6CR 0x14 Port 6 Control
P7CR 0x15 Port 7 Control
P6FC 0x16 Port 6 Function
P7FC 0x17 Port 7 Function
P8 0x18 Port 8
P9 0x19 Port 9
P8CR 0x1A Port 8 Control
P9CR 0x1B Port 9 Control
P8FC 0x1C Port 8 Function
P9FC 0x1D Port 9 Function
PA 0x1E Port A
PACR 0x1F Port A Control
TRUN 0x20 Timer Control
TREG0 0x22 Timer Register 0
TREG1 0x23 Timer Register 1
TMOD 0x24 Timer Source CLK & MODE
TFFCR 0x25 Flip-Flop Control
TREG2 0x26 Timer Register 2
TREG3 0x27 Timer Register 3
P0MOD 0x28 PWM0 Mode
P1MOD 0x29 PWM1 Mode
PFFCR 0x2A PWM Flip-Flop Control
TREG4L 0x30 Timer Register 4 Low
TREG4H 0x31 Timer Register 4 High
TREG5L 0x32 Timer Register 5 Low
TREG5H 0x33 Timer Register 5 High
CAP1L 0x34 Capture Register 1 Low
CAP1H 0x35 Capture Register 1 High
CAP2L 0x36 Capture Register 2 Low
CAP2H 0x37 Capture Register 2 High
T4MOD 0x38 Timer 4 Source CLK & Mode
T4FFCR 0x39 Timer 4 Flip-Flop Control
T45CR 0x3A T4, T5 Control
TREG6L 0x40 Timer Register 6 Low
TREG6H 0x41 Timer Register 6 High
TREG7L 0x42 Timer Register 7 Low
TREG7H 0x43 Timer Register 7 High
CAP3L 0x44 Capture Register 3 Low
CAP3H 0x45 Capture REgister 3 High
CAP4L 0x46 Capture Register 4 Low
CAP4H 0x47 Capture Register 4 High
T5MOD 0x48 Timer 5 Source CLK & Mode
T5FFCR 0x49 Timer 5 Flip-Flip Control
SC0BUF 0x50 Serial Chanel 0 Buffer
SC0CR 0x51 Serial Chanel 0 Control
SC0MOD 0x52 Serial Chanel 0 Mode
BR0CR 0x53 Serial Chanel 0 Baud Rate
SC1BUF 0x54 Serial Chanel 1 Buffer
SC1CR 0x55 Serial Chanel 1 Control
SC1MOD 0x56 Serial Chanel 1 Mode
BR1CR 0x57 Serial Chanel 1 Baud Rate
ODE 0x58 Serial Open Drain Enable
WDMOD 0x5C Watch Dog Timer Mode
WDCR 0x5D Watch Dog Control Register
ADMOD1 0x5E A/D Mode Register 1
ADMOD2 0x5F A/D Mode Register 2
ADREG04L 0x60 A/D Result Register 0/4 Low
ADREG04H 0x61 A/D Result Register 0/4 High
ADREG15L 0x62 A/D Result Register 1 Low
ADREG15H 0x63 A/D Result Register 1 High
ADREG26L 0x64 A/D Result Register 2 Low
ADREG26H 0x65 A/D Result Register 2 High
ADREG37L 0x66 A/D Result Register 3 Low
ADREG37H 0x67 A/D Result Register 3 High
B0CS 0x68 Block 0 CS/WAIT Control Register
B1CS 0x69 Block 1 CS/WAIT Control Register
B2CS 0x6A Block 2 CS/WAIT Control Register
CKOCR 0x6D Clock Output Control Register
SYSCR0 0x6E System Clock Register 0
SYSCR1 0x6F System Clock Contol Register 1
INTE0AD 0x70 Interrupt Enable 0 & A/D
INTE45 0x71 Interrupt Enable 4/5
INTE67 0x72 Interrupt Enable 6/7
INTET10 0x73 Interrupt Enable Timer 1/0
INTE89 0x74 Interrupt Enable 8/9
INTET54 0x75 Interrupt Enable 5/4
INTET76 0x76 Interrupt Enable 7/6
INTES0 0x77 Interrupt Enable Serial 0
INTES1 0x78 Interrupt Enable Serial 1
IIMC 0x7B Interrupt Input Mode Control
DMA0V 0x7C DMA 0 Reauest Vector
DMA1V 0x7D DMA 1 Request Vector
DMA2V 0x7E DMA 2 Request Vector
DMA3V 0x7F DMA 3 Request Vector
.TMP94CS40A
; MEMORY MAP
area DATA FSR 0x000000:0x000170 Special Function Register
area DATA IRAM 0x000400:0x000C00 Internal High-Speed RAM
area CODE IROM 0xFF0000:0x100000 Internal ROM
; Interrupt and reset vector assignments
interrupt RESET_ 0xFFFF00 RESET
interrupt SWI1_ 0xFFFF04 SWI1
interrupt SWI2_ 0xFFFF08 SWI2
interrupt SWI3_ 0xFFFF0C SWI3
interrupt SWI4_ 0xFFFF10 SWI4
interrupt SWI5_ 0xFFFF14 SWI5
interrupt SWI6_ 0xFFFF18 SWI6
interrupt SWI7_ 0xFFFF1C SWI7
interrupt NMI_ 0xFFFF20 NMI
interrupt INTWD_ 0xFFFF24 Watch-dog Timer
interrupt INT0_ 0xFFFF28 INT0
interrupt INT4_ 0xFFFF2C INT4
interrupt INT5_ 0xFFFF30 INT5
interrupt INT6_ 0xFFFF34 INT6
interrupt INT7_ 0xFFFF38 INT7
interrupt INT8_ 0xFFFF40 INT8
interrupt INT9_ 0xFFFF44 INT9
interrupt INTA_ 0xFFFF48 INTA
interrupt INTB_ 0xFFFF4C INTB
interrupt INTT0_ 0xFFFF50 INTT0
interrupt INTT1_ 0xFFFF54 INTT1
interrupt INTT2_ 0xFFFF58 INTT2
interrupt INTT3_ 0xFFFF5C INTT3
interrupt INTTR4_ 0xFFFF60 16-bit timer 4
interrupt INTTR5_ 0xFFFF64 16-bit timer 5
interrupt INTTR6_ 0xFFFF68 16-bit timer 6
interrupt INTTR7_ 0xFFFF6C 16-bit timer 7
interrupt INTTR8_ 0xFFFF70 16-bit timer 8
interrupt INTTR9_ 0xFFFF74 16-bit timer 9
interrupt INTTRA_ 0xFFFF78 16-bit timer A
interrupt INTTRB_ 0xFFFF7C 16-bit timer B
interrupt INTRX0_ 0xFFFF80 Serial RX 0
interrupt INTTX0_ 0xFFFF84 Serial Tx 0
interrupt INTRX1_ 0xFFFF88 Serial RX 1
interrupt INTTX1_ 0xFFFF8C Serial TX 1
interrupt INTAD_ 0xFFFF90 AD conversion complete
interrupt INTTC0_ 0xFFFF94 Micro DMA completion Ch.0
interrupt INTTC1_ 0xFFFF98 Micro DMA completion Ch.1
interrupt INTTC2_ 0xFFFF9C Micro DMA completion Ch.2
interrupt INTTC3_ 0xFFFFA0 Micro DMA completion Ch.3
interrupt INTTC4_ 0xFFFFA4 Micro DMA completion Ch.4
interrupt INTTC5_ 0xFFFFA8 Micro DMA completion Ch.5
interrupt INTTC6_ 0xFFFFAC Micro DMA completion Ch.6
interrupt INTTC7_ 0xFFFFB0 Micro DMA completion Ch.7
; INPUT/OUPUT
; Warning - only i/o port register, not all!!!
P0 0x00 Port 0
P0CR 0x02 Port 0 Control
P0FC 0x03 Port 0 Function
P1 0x04 Port 1
P1CR 0x06 Port 1 Control
P1FC 0x07 Port 1 Function
P2 0x08 Port 2
P2CR 0x0A Port 2 Control
P2FC 0x0B Port 2 Function
P3 0x0C Port 3
P3CR 0x0E Port 3 Control
P3FC 0x0F Port 3 Function
P4 0x10 Port 4
P4CR 0x12 Port 4 Control
P4FC 0x13 Port 4 Function
P5 0x14 Port 5
P5CR 0x16 Port 4 Control
P5FC 0x17 Port 4 Function
P6 0x18 Port 6
P6CR 0x1A Port 6 Control
P6FC 0x1B Port 6 Function
P7 0x1C Port 7
P7CR 0x1E Port 7 Control
P7FC 0x1F Port 7 Function
P8 0x20 Port 8
P8CR 0x22 Port 8 Control
P8FC 0x23 Port 8 Function
PA 0x28 Port A
PAFC 0x2B Port A Function
PB 0x2C Port B
PBFC 0x2F Port B Function
PC 0x30 Port C
PCCR 0x32 Port C Control
PCFC 0x33 Port C Function
PD 0x34 Port D
PDCR 0x36 Port D Control
PDFC 0x37 Port D Function
PE 0x38 Port E
PECR 0x3A Port E Control
PEFC 0x3B Port E Function
PF 0x3C Port F
PFCR 0x3E Port F Control
PFFC 0x3F Port F Function
PG 0x40 Port G
PH 0x44 Port H
PHCR 0x46 Port H Control
PHFC 0x47 Port H Function
PZ 0x68 Port Z
PZCR 0x6A Port Z Control

78
idasdk75/module/tlcs900/tosh.hpp Normal file
View File

@@ -0,0 +1,78 @@
/*
* TLCS900 processor module for IDA.
* Copyright (c) 1998-2006 Konstantin Norvatoff, <konnor@bk.ru>
* Freeware.
*/
#ifndef _TOSH_HPP
#define _TOSH_HPP
#include <ida.hpp>
#include <idp.hpp>
#include "../idaidp.hpp"
#include "ins.hpp"
#include <diskio.hpp>
#include "../iohandler.hpp"
//-----------------------------------------------
// Increment/decrement
#define URB_DECR (0x80) // decrement
#define URB_DCMASK (0x07) // mask or decrement
#define URB_UDEC (0x40) // singleton decrement
#define URB_UINC (0x20) // signleto increment
// specflag1 bits
#define URB_WORD (1) // second index register is word
#define URB_LDA (2) // insn uses address not the content
#define URB_LDA2 (4) // same, but may constant!
//------------------------------------------------------------------------
enum T900_registers
{
rNULLReg,
rW, rA, rB, rC, rD, rE, rH, rL,
rWA, rBC, rDE, rHL, rIX, rIY, rIZ, rSP,
rXWA, rXBC, rXDE, rXHL, rXIX, rXIY, rXIZ, rXSP,
rIXL, rIXH, rIYL, rIYH, rIZL, rIZH, rSPL, rSPH,
rVcs, rVds
};
// phrases
enum T900_phrases
{
rNULLPh,
fCF,fCLT,fCLE,fCULE,fCPE,fCMI,fCZ,fCC,
fCT,fCGE,fCGT,fCUGT,fCPO,fCPL,fCNZ,fCNC,
fSF,fSF1,
fSR, fPC
};
//------------------------------------------------------------------
struct tlcs900_iohandler_t : public iohandler_t
{
tlcs900_iohandler_t(netnode &nn) : iohandler_t(nn) {}
};
struct tlcs900_t : public procmod_t
{
netnode helper;
tlcs900_iohandler_t ioh = tlcs900_iohandler_t(helper);
bool flow = false;
virtual ssize_t idaapi on_event(ssize_t msgid, va_list va) override;
void handle_operand(const insn_t &insn, const op_t &x, bool is_forced, bool isload);
int T900_emu(const insn_t &insn);
void T900_header(outctx_t &ctx);
void T900_segstart(outctx_t &ctx, segment_t *Sarea) const;
void T900_footer(outctx_t &ctx) const;
};
//------------------------------------------------------------------------
int idaapi T900_ana(insn_t *_insn);
void idaapi T900_data(outctx_t &ctx, bool analyze_only);
#endif