288 lines
11 KiB
INI
288 lines
11 KiB
INI
; The format of the input file:
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; each device definition begins with a line like this:
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;
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; .devicename
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;
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; after it go the port definitions in this format:
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;
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; portname address
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;
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; the bit definitions (optional) are represented like this:
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;
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; portname.bitname bitnumber
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;
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; lines beginning with a space are ignored.
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; comment lines should be started with ';' character.
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;
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; the default device is specified at the start of the file
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;
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; .default device_name
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;
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; all lines non conforming to the format are passed to the callback function
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;
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; Toshiba TLCS900 SPECIFIC LINES
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;------------------------
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;
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; the processor definition may include the memory configuration.
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; the line format is:
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; area CLASS AREA-NAME START:END
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;
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; where CLASS is anything, but please use one of CODE, DATA, BSS
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; START and END are addresses, the end address is not included
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; Interrupt vectors are declared in the following way:
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; entry NAME ADDRESS COMMENT
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.default TMP93CS42A
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.TMP93CS42A
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; MEMORY MAP
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area DATA FSR 0x0000:0x0080 Special Function Register
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area DATA IRAM 0x0080:0x0880 Internal High-Speed RAM
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area CODE IROM 0x8000:0x10000 Internal ROM
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; Interrupt and reset vector assignments
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interrupt RESET_ 0x8000 RESET
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interrupt SWI1_ 0x8004 SWI1
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interrupt SWI2_ 0x8008 SWI2
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interrupt SWI3_ 0x800C SWI3
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interrupt SWI4_ 0x8010 SWI4
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interrupt SWI5_ 0x8014 SWI5
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interrupt SWI6_ 0x8018 SWI6
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interrupt SWI7_ 0x801C SWI7
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interrupt NMI_ 0x8020 NMI
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interrupt INTWD_ 0x8024 INTWD
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interrupt INT0_ 0x8028 INT0
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interrupt INT4_ 0x802C INT4
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interrupt INT5_ 0x8030 INT5
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interrupt INT6_ 0x8034 INT6
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interrupt INT7_ 0x8038 INT7
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interrupt INTT0_ 0x8040 INTT0
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interrupt INTT1_ 0x8044 INTT1
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interrupt INT8_ 0x8048 INT8
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interrupt INT9_ 0x804C INT9
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interrupt INTR4_ 0x8050 INTR4
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interrupt INTR5_ 0x8054 INTR5
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interrupt INTR6_ 0x8058 INTR6
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interrupt INTR7_ 0x805C INTR7
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interrupt INTRX0_ 0x8060 INTRX0
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interrupt INTTX0_ 0x8064 INTTX0
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interrupt INTRX1_ 0x8068 INTRX1
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interrupt INTTX1_ 0x806C INTTX1
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interrupt INTAD_ 0x8070 INTAD
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; INPUT/OUTPUT
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P0 0x00 Port 0
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P1 0x01 Port 1
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P0CR 0x02 Port 0 Control
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P1CR 0x04 Port 1 Control
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P1FC 0x05 Port 1 Function
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P2 0x06 Port 2
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P3 0x07 Port 3
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P2CR 0x08 Port 2 Control
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P2FC 0x09 Port 2 Function
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P3CR 0x0A Port 3 Control
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P3FC 0x0B Port 3 Function
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P4 0x0C Port 4
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P5 0x0D Port 5
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P4CR 0x0E Port 4 Control
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P4FC 0x10 Port 4 Function
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P6 0x12 Port 6
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P7 0x13 Port 7
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P6CR 0x14 Port 6 Control
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P7CR 0x15 Port 7 Control
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P6FC 0x16 Port 6 Function
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P7FC 0x17 Port 7 Function
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P8 0x18 Port 8
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P9 0x19 Port 9
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P8CR 0x1A Port 8 Control
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P9CR 0x1B Port 9 Control
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P8FC 0x1C Port 8 Function
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P9FC 0x1D Port 9 Function
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PA 0x1E Port A
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PACR 0x1F Port A Control
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TRUN 0x20 Timer Control
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TREG0 0x22 Timer Register 0
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TREG1 0x23 Timer Register 1
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TMOD 0x24 Timer Source CLK & MODE
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TFFCR 0x25 Flip-Flop Control
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TREG2 0x26 Timer Register 2
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TREG3 0x27 Timer Register 3
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P0MOD 0x28 PWM0 Mode
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P1MOD 0x29 PWM1 Mode
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PFFCR 0x2A PWM Flip-Flop Control
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TREG4L 0x30 Timer Register 4 Low
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TREG4H 0x31 Timer Register 4 High
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TREG5L 0x32 Timer Register 5 Low
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TREG5H 0x33 Timer Register 5 High
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CAP1L 0x34 Capture Register 1 Low
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CAP1H 0x35 Capture Register 1 High
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CAP2L 0x36 Capture Register 2 Low
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CAP2H 0x37 Capture Register 2 High
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T4MOD 0x38 Timer 4 Source CLK & Mode
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T4FFCR 0x39 Timer 4 Flip-Flop Control
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T45CR 0x3A T4, T5 Control
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TREG6L 0x40 Timer Register 6 Low
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TREG6H 0x41 Timer Register 6 High
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TREG7L 0x42 Timer Register 7 Low
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TREG7H 0x43 Timer Register 7 High
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CAP3L 0x44 Capture Register 3 Low
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CAP3H 0x45 Capture REgister 3 High
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CAP4L 0x46 Capture Register 4 Low
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CAP4H 0x47 Capture Register 4 High
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T5MOD 0x48 Timer 5 Source CLK & Mode
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T5FFCR 0x49 Timer 5 Flip-Flip Control
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SC0BUF 0x50 Serial Chanel 0 Buffer
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SC0CR 0x51 Serial Chanel 0 Control
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SC0MOD 0x52 Serial Chanel 0 Mode
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BR0CR 0x53 Serial Chanel 0 Baud Rate
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SC1BUF 0x54 Serial Chanel 1 Buffer
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SC1CR 0x55 Serial Chanel 1 Control
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SC1MOD 0x56 Serial Chanel 1 Mode
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BR1CR 0x57 Serial Chanel 1 Baud Rate
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ODE 0x58 Serial Open Drain Enable
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WDMOD 0x5C Watch Dog Timer Mode
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WDCR 0x5D Watch Dog Control Register
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ADMOD1 0x5E A/D Mode Register 1
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ADMOD2 0x5F A/D Mode Register 2
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ADREG04L 0x60 A/D Result Register 0/4 Low
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ADREG04H 0x61 A/D Result Register 0/4 High
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ADREG15L 0x62 A/D Result Register 1 Low
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ADREG15H 0x63 A/D Result Register 1 High
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ADREG26L 0x64 A/D Result Register 2 Low
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ADREG26H 0x65 A/D Result Register 2 High
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ADREG37L 0x66 A/D Result Register 3 Low
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ADREG37H 0x67 A/D Result Register 3 High
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B0CS 0x68 Block 0 CS/WAIT Control Register
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B1CS 0x69 Block 1 CS/WAIT Control Register
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B2CS 0x6A Block 2 CS/WAIT Control Register
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CKOCR 0x6D Clock Output Control Register
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SYSCR0 0x6E System Clock Register 0
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SYSCR1 0x6F System Clock Contol Register 1
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INTE0AD 0x70 Interrupt Enable 0 & A/D
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INTE45 0x71 Interrupt Enable 4/5
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INTE67 0x72 Interrupt Enable 6/7
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INTET10 0x73 Interrupt Enable Timer 1/0
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INTE89 0x74 Interrupt Enable 8/9
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INTET54 0x75 Interrupt Enable 5/4
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INTET76 0x76 Interrupt Enable 7/6
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INTES0 0x77 Interrupt Enable Serial 0
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INTES1 0x78 Interrupt Enable Serial 1
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IIMC 0x7B Interrupt Input Mode Control
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DMA0V 0x7C DMA 0 Reauest Vector
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DMA1V 0x7D DMA 1 Request Vector
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DMA2V 0x7E DMA 2 Request Vector
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DMA3V 0x7F DMA 3 Request Vector
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.TMP94CS40A
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; MEMORY MAP
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area DATA FSR 0x000000:0x000170 Special Function Register
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area DATA IRAM 0x000400:0x000C00 Internal High-Speed RAM
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area CODE IROM 0xFF0000:0x100000 Internal ROM
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; Interrupt and reset vector assignments
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interrupt RESET_ 0xFFFF00 RESET
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interrupt SWI1_ 0xFFFF04 SWI1
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interrupt SWI2_ 0xFFFF08 SWI2
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interrupt SWI3_ 0xFFFF0C SWI3
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interrupt SWI4_ 0xFFFF10 SWI4
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interrupt SWI5_ 0xFFFF14 SWI5
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interrupt SWI6_ 0xFFFF18 SWI6
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interrupt SWI7_ 0xFFFF1C SWI7
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interrupt NMI_ 0xFFFF20 NMI
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interrupt INTWD_ 0xFFFF24 Watch-dog Timer
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interrupt INT0_ 0xFFFF28 INT0
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interrupt INT4_ 0xFFFF2C INT4
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interrupt INT5_ 0xFFFF30 INT5
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interrupt INT6_ 0xFFFF34 INT6
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interrupt INT7_ 0xFFFF38 INT7
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interrupt INT8_ 0xFFFF40 INT8
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interrupt INT9_ 0xFFFF44 INT9
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interrupt INTA_ 0xFFFF48 INTA
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interrupt INTB_ 0xFFFF4C INTB
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interrupt INTT0_ 0xFFFF50 INTT0
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interrupt INTT1_ 0xFFFF54 INTT1
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interrupt INTT2_ 0xFFFF58 INTT2
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interrupt INTT3_ 0xFFFF5C INTT3
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interrupt INTTR4_ 0xFFFF60 16-bit timer 4
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interrupt INTTR5_ 0xFFFF64 16-bit timer 5
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interrupt INTTR6_ 0xFFFF68 16-bit timer 6
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interrupt INTTR7_ 0xFFFF6C 16-bit timer 7
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interrupt INTTR8_ 0xFFFF70 16-bit timer 8
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interrupt INTTR9_ 0xFFFF74 16-bit timer 9
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interrupt INTTRA_ 0xFFFF78 16-bit timer A
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interrupt INTTRB_ 0xFFFF7C 16-bit timer B
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interrupt INTRX0_ 0xFFFF80 Serial RX 0
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interrupt INTTX0_ 0xFFFF84 Serial Tx 0
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interrupt INTRX1_ 0xFFFF88 Serial RX 1
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interrupt INTTX1_ 0xFFFF8C Serial TX 1
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interrupt INTAD_ 0xFFFF90 AD conversion complete
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interrupt INTTC0_ 0xFFFF94 Micro DMA completion Ch.0
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interrupt INTTC1_ 0xFFFF98 Micro DMA completion Ch.1
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interrupt INTTC2_ 0xFFFF9C Micro DMA completion Ch.2
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interrupt INTTC3_ 0xFFFFA0 Micro DMA completion Ch.3
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interrupt INTTC4_ 0xFFFFA4 Micro DMA completion Ch.4
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interrupt INTTC5_ 0xFFFFA8 Micro DMA completion Ch.5
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interrupt INTTC6_ 0xFFFFAC Micro DMA completion Ch.6
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interrupt INTTC7_ 0xFFFFB0 Micro DMA completion Ch.7
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; INPUT/OUPUT
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; Warning - only i/o port register, not all!!!
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P0 0x00 Port 0
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P0CR 0x02 Port 0 Control
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P0FC 0x03 Port 0 Function
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P1 0x04 Port 1
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P1CR 0x06 Port 1 Control
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P1FC 0x07 Port 1 Function
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P2 0x08 Port 2
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P2CR 0x0A Port 2 Control
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P2FC 0x0B Port 2 Function
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P3 0x0C Port 3
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P3CR 0x0E Port 3 Control
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P3FC 0x0F Port 3 Function
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P4 0x10 Port 4
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P4CR 0x12 Port 4 Control
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P4FC 0x13 Port 4 Function
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P5 0x14 Port 5
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P5CR 0x16 Port 4 Control
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P5FC 0x17 Port 4 Function
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P6 0x18 Port 6
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P6CR 0x1A Port 6 Control
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P6FC 0x1B Port 6 Function
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P7 0x1C Port 7
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P7CR 0x1E Port 7 Control
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P7FC 0x1F Port 7 Function
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P8 0x20 Port 8
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P8CR 0x22 Port 8 Control
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P8FC 0x23 Port 8 Function
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PA 0x28 Port A
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PAFC 0x2B Port A Function
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PB 0x2C Port B
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PBFC 0x2F Port B Function
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PC 0x30 Port C
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PCCR 0x32 Port C Control
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PCFC 0x33 Port C Function
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PD 0x34 Port D
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PDCR 0x36 Port D Control
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PDFC 0x37 Port D Function
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PE 0x38 Port E
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PECR 0x3A Port E Control
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PEFC 0x3B Port E Function
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PF 0x3C Port F
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PFCR 0x3E Port F Control
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PFFC 0x3F Port F Function
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PG 0x40 Port G
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PH 0x44 Port H
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PHCR 0x46 Port H Control
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PHFC 0x47 Port H Function
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PZ 0x68 Port Z
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PZCR 0x6A Port Z Control
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