240 lines
8.9 KiB
INI
240 lines
8.9 KiB
INI
.Z80180
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; Enhanced Z80 Megacell
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; http://www.zilog.com/products/partdetails.asp?id=Z80180
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; INPUT/ OUTPUT PORTS
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CNTLA0 0x0000 ASCI Channel Control Register A 0
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CNTLA0.MPE 7 Multi-Processor Mode Enable
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CNTLA0.RE 6 Receiver Enable
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CNTLA0.TE 5 Transmitter Enable
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CNTLA0._RTS0 4 Request to Send Channel 0
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CNTLA0.MPBR_EFR 3 Multiprocessor Bit Receive/Error Flag Reset
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CNTLA0.MOD2 2 ASCI Data Format Mode 2
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CNTLA0.MOD1 1 ASCI Data Format Mode 1
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CNTLA0.MOD0 0 ASCI Data Format Mode 0
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CNTLA1 0x0001 ASCI Channel Control Register A 0
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CNTLA1.MPE 7 Multi-Processor Mode Enable
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CNTLA1.RE 6 Receiver Enable
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CNTLA1.TE 5 Transmitter Enable
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CNTLA1._RTS0 4 Request to Send Channel 0
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CNTLA1.MPBR_EFR 3 Multiprocessor Bit Receive/Error Flag Reset
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CNTLA1.MOD2 2 ASCI Data Format Mode 2
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CNTLA1.MOD1 1 ASCI Data Format Mode 1
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CNTLA1.MOD0 0 ASCI Data Format Mode 0
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CNTLB0 0x0002 ASCI Channel Control Register B 0
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CNTLB0.MPBT 7 Multiprocessor Bit Transmit
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CNTLB0.MP 6 Multiprocessor Mode
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CNTLB0.__CTS_PS 5 Clear to Send/Prescale
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CNTLB0.PEO 4 Parity Even Odd
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CNTLB0.DR 3 Divide Ratio
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CNTLB0.SS2 2 Source/Speed Select 2
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CNTLB0.SS1 1 Source/Speed Select 1
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CNTLB0.SS0 0 Source/Speed Select 0
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CNTLB1 0x0003 ASCI Channel Control Register B 1
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CNTLB1.MPBT 7 Multiprocessor Bit Transmit
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CNTLB1.MP 6 Multiprocessor Mode
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CNTLB1.__CTS_PS 5 Clear to Send/Prescale
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CNTLB1.PEO 4 Parity Even Odd
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CNTLB1.DR 3 Divide Ratio
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CNTLB1.SS2 2 Source/Speed Select 2
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CNTLB1.SS1 1 Source/Speed Select 1
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CNTLB1.SS0 0 Source/Speed Select 0
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STAT0 0x0004 ASCI Status Register 0
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STAT0.RDRF 7 Receive Data Register Full
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STAT0.OVRN 6 Overrun Error
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STAT0.PE 5 Parity Error
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STAT0.FE 4 Framing Error
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STAT0.REI 3 Receive Interrupt Enable
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STAT0._DCD0 2 Data Carrier Detect
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STAT0.TDRE 1 Transmit Data Register Empty
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STAT0.TIE 0 Transmit Interrupt Enable
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STAT1 0x0005 ASCI Status Register 1
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STAT1.RDRF 7 Receive Data Register Full
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STAT1.OVRN 6 Overrun Error
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STAT1.PE 5 Parity Error
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STAT1.FE 4 Framing Error
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STAT1.REI 3 Receive Interrupt Enable
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STAT1.TDRE 1 Transmit Data Register Empty
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STAT1.TIE 0 Transmit Interrupt Enable
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TDR0 0x0006
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TDR1 0x0007
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RDR0 0x0008
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RDR1 0x0009
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CNTR 0x000A CSIO Control/Status Register
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CNTR.EF 7 End Flag
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CNTR.EIE 6 End Interrupt Enable
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CNTR.RE 5 Receive Enable
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CNTR.TE 4 Transmit Enable
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CNTR.SS2 2 Speed Select 2
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CNTR.SS1 1 Speed Select 1
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CNTR.SS0 0 Speed Select 0
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TRDR 0x000B CSIO Transmit/Receive Data Register
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TMDR0L 0x000C Timer Data Register Channel 0L
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TMDR0H 0x000D Timer Data Register Channel 0H
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RLDR0L 0x000E Timer Reload Register 0L
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RLDR0H 0x000F Timer Reload Register 0H
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TCR 0x0010 Timer Control Register
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TCR.TIF1 7 Timer Interrupt Flag 1
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TCR.TIF0 6 Timer Interrupt Flag 0
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TCR.TIE1 5 Timer Interrupt Enable 1
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TCR.TIE0 4 Timer Interrupt Enable 0
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TCR.TOC1 3 Timer Output Control
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TCR.TOC0 2 Timer Output Control
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TCR.TDE1 1
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TCR.TDE0 0
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TMDR1L 0x0014 Timer Data Register Channel 1L
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TMDR1H 0x0015 Timer Data Register Channel 1H
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RLDR1L 0x0016 Timer Reload Register 1L
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RLDR1H 0x0017 Timer Reload Register 1H
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FRC 0x0018 Free Running Counter
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SAR0L 0x0020 DMA Source Address Register Channel 0L
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SAR0H 0x0021 DMA Source Address Register Channel 0H
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SAR0B 0x0022 DMA Source Address Register Channel 0B
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DAR0L 0x0023 DMA Destination Address Register Channel 0L
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DAR0H 0x0024 DMA Destination Address Register Channel 0H
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DAR0B 0x0025 DMA Destination Address Register Channel 0B
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BCR0L 0x0026 DMA Byte Count Register Channel 0L
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BCR0H 0x0027 DMA Byte Count Register Channel 0H
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MAR1L 0x0028 DMA Memory Address Register, Channel 1L
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MAR1H 0x0029 DMA Memory Address Register, Channel 1H
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MAR1B 0x002A DMA Memory Address Register, Channel 1B
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IAR1L 0x002B DMA I/O Address Register Channel 1L
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IAR1H 0x002C DMA I/O Address Register Channel 1H
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BCR1L 0x002E DMA Byte Count Register Channel 1L
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BCR1H 0x002F DMA Byte Count Register Channel 1H
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DSTAT 0x0030 DMA Status Register
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DSTAT.DE1 7 DE1: DMA Enable Channel 1
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DSTAT.DE0 6 DE0: DMA Enable Channel 0
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DSTAT.DWE1 5 DE1 Bit WRITE Enable
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DSTAT.DWE0 4 DE0 Bit WRITE Enable
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DSTAT.DIE1 3 DMA Interrupt Enable Channel
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DSTAT.DIE0 2 DMA Interrupt Enable Channel
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DSTAT.DME 0 DMA Main Enable
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DMODE 0x0031 DMA Mode Register
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DMODE.DM1 5 Destination Mode Channel 0
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DMODE.DM0 4 Destination Mode Channel 0
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DMODE.SM1 3 Source Mode Channel 0
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DMODE.SM0 2 Source Mode Channel 0
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DMODE.MMOD 1 Memory Mode Channel 0
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DCNTL 0x0032 DMA/WAIT Control Register
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DCNTL.MWI1 7 Memory Wait Insertion
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DCNTL.MWI0 6 Memory Wait Insertion
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DCNTL.IWI1 5 I/O Wait Insertion
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DCNTL.IWI0 4 I/O Wait Insertion
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DCNTL.DMS1 3 DMA Request Sense
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DCNTL.DMS0 2 DMA Request Sense
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DCNTL.DIM1 1 DMA Channel 1 I/O and Memory Mode
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DCNTL.DIM0 0 DMA Channel 1 I/O and Memory Mode
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IL 0x0033 Interrupt Vector Low Register
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IL.IL7 7
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IL.IL6 6
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IL.IL5 5
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ITC 0x0034 Int/TRAP Control Register
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ITC.TRAP 7
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ITC.UFO 6 Undefined Fetch Object
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ITC.ITE2 2 Interrupt Enable 2
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ITC.ITE1 1 Interrupt Enable 1
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ITC.ITE0 0 Interrupt Enable 0
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RCR 0x0036 Refresh Control Register
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RCR.REFE 7 Refresh Enable
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RCR.REFW 6 Refresh Wait
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RCR.CYC1 1 Cycle Interval
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RCR.CYC0 0 Cycle Interval
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CBR 0x0038 MMU Common Base Register (CBR)
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CBR.CB7 7
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CBR.CB6 6
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CBR.CB5 5
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CBR.CB4 4
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CBR.CB3 3
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CBR.CB2 2
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CBR.CB1 1
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CBR.CB0 0
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BBR 0x0039 MMU Bank Base Register (BBR)
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BBR.BB7 7
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BBR.BB6 6
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BBR.BB5 5
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BBR.BB4 4
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BBR.BB3 3
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BBR.BB2 2
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BBR.BB1 1
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BBR.BB0 0
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CBAR 0x003A MMU Common/Bank Area Register (CBAR)
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CBAR.CA3 7
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CBAR.CA2 6
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CBAR.CA1 5
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CBAR.CA0 4
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CBAR.BA3 3
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CBAR.BA2 2
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CBAR.BA1 1
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CBAR.BA0 0
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OMCR 0x003E Operation Mode Control Register
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OMCR.MIE 7
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OMCR._MITE 6
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OMCR._IOC 5
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ICR 0x003F I/O Control Register (ICR)
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ICR.IOA7 7
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ICR.IOA6 6
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ICR.IOSTP 5
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.Z80181
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; Smart Access Controller
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.Z80182
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; ZiLOG Intelligent Peripheral (ZIPT)
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.Z80189
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.Z8S180
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; + Parallel I/O
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.Z80195
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; Smart Peripheral Controller (ROMless)
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.Z80L183
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; Mixed-Signal Z183 Internet Processor
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.Z80S183
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. Mixed-Signal Z183 Internet Processor
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.Z8L180
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; Enhanced Z80 Megacell
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.Z8L180
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; Low-Voltage Version (3.3 V)
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.Z8L182
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; ZiLOG Intelligent Peripheral (ZIPT) - Low Voltage Version
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.Z8S180
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; Enhanced Z80 Megacell
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.Z8L180
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; Low-Voltage Version (3.3 V)
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