325 lines
8.4 KiB
C++
325 lines
8.4 KiB
C++
/*
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* Interactive disassembler (IDA).
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* Copyright (c) 1990-98 by Ilfak Guilfanov.
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* ALL RIGHTS RESERVED.
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* E-mail: ig@estar.msk.su
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* FIDO: 2:5020/209
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*
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*
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* TMS320C6xx - VLIW (very long instruction word) architecture
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*
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*/
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#include "tms6.hpp"
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//--------------------------------------------------------------------------
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// B14 - data page pointer
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// B15 - stack pointer
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static const char *const RegNames[] =
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{
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"A0", "A1", "A2", "A3", "A4", "A5", "A6", "A7",
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"A8", "A9", "A10", "A11", "A12", "A13", "A14", "A15",
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"A16", "A17", "A18", "A19", "A20", "A21", "A22", "A23",
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"A24", "A25", "A26", "A27", "A28", "A29", "A30", "A31",
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"B0", "B1", "B2", "B3", "B4", "B5", "B6", "B7",
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"B8", "B9", "B10", "B11", "B12", "B13", "B14", "B15",
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"B16", "B17", "B18", "B19", "B20", "B21", "B22", "B23",
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"B24", "B25", "B26", "B27", "B28", "B29", "B30", "B31",
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"AMR",
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"CSR",
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"IFR",
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"ISR",
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"ICR",
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"IER",
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"ISTP",
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"IRP",
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"NRP",
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"ACR", // undocumented, info from Jeff Bailey <jeff_bailey@infinitek.com>
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"ADR", // undocumented, info from Jeff Bailey <jeff_bailey@infinitek.com>
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"PCE1",
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"FADCR",
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"FAUCR",
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"FMCR",
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"TSCL",
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"TSCH",
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"ILC",
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"RILC",
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"REP",
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"DNUM",
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"SSR",
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"GPLYA",
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"GPLYB",
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"GFPGFR",
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"TSR",
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"ITSR",
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"NTSR",
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"ECR",
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"EFR",
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"IERR",
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"CS", "DS"
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};
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//--------------------------------------------------------------------------
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ssize_t idaapi idb_listener_t::on_event(ssize_t code, va_list va)
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{
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switch ( code )
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{
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case idb_event::segm_moved: // A segment is moved
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// Fix processor dependent address sensitive information
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{
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ea_t from = va_arg(va, ea_t);
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ea_t to = va_arg(va, ea_t);
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asize_t size = va_arg(va, asize_t);
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bool changed_netmap = va_argi(va, bool);
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if ( !changed_netmap )
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{
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struct aaj_visitor_t : public altadjust_visitor_t
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{
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tms6_t ±
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aaj_visitor_t(tms6_t &_pm): pm(_pm) {}
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virtual bool should_skip(nodeidx_t n) override
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{
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nodeidx_t ndx = pm.tnode.altval(n);
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return ndx == 1 || ndx == 2;
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}
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};
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nodeidx_t ndx1 = ea2node(from);
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nodeidx_t ndx2 = ea2node(to);
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pm.tnode.altshift(ndx1, ndx2, size);
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aaj_visitor_t aaj(pm);
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pm.tnode.altadjust2(ndx1, ndx2, size, aaj);
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}
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}
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break;
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}
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return 0;
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}
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//----------------------------------------------------------------------
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// This old-style callback only returns the processor module object.
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static ssize_t idaapi notify(void *, int msgid, va_list)
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{
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if ( msgid == processor_t::ev_get_procmod )
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return size_t(new tms6_t);
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return 0;
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}
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//--------------------------------------------------------------------------
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ssize_t idaapi tms6_t::on_event(ssize_t msgid, va_list va)
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{
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int code = 0;
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switch ( msgid )
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{
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case processor_t::ev_init:
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hook_event_listener(HT_IDB, &idb_listener, &LPH);
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break;
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case processor_t::ev_term:
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unhook_event_listener(HT_IDB, &idb_listener);
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break;
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case processor_t::ev_ending_undo:
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case processor_t::ev_newfile:
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case processor_t::ev_oldfile:
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tnode.create("$ tms node");
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break;
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case processor_t::ev_out_header:
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{
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outctx_t *ctx = va_arg(va, outctx_t *);
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header(*ctx);
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return 1;
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}
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case processor_t::ev_out_footer:
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{
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outctx_t *ctx = va_arg(va, outctx_t *);
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footer(*ctx);
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return 1;
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}
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case processor_t::ev_out_segstart:
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{
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outctx_t *ctx = va_arg(va, outctx_t *);
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segment_t *seg = va_arg(va, segment_t *);
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segstart(*ctx, seg);
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return 1;
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}
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case processor_t::ev_out_segend:
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{
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outctx_t *ctx = va_arg(va, outctx_t *);
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segment_t *seg = va_arg(va, segment_t *);
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segend(*ctx, seg);
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return 1;
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}
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case processor_t::ev_ana_insn:
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{
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insn_t *out = va_arg(va, insn_t *);
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return ana(out);
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}
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case processor_t::ev_emu_insn:
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{
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const insn_t *insn = va_arg(va, const insn_t *);
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return emu(*insn) ? 1 : -1;
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}
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case processor_t::ev_out_insn:
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{
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outctx_t *ctx = va_arg(va, outctx_t *);
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out_insn(*ctx);
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return 1;
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}
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case processor_t::ev_out_operand:
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{
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outctx_t *ctx = va_arg(va, outctx_t *);
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const op_t *op = va_arg(va, const op_t *);
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return out_opnd(*ctx, *op) ? 1 : -1;
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}
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case processor_t::ev_out_data:
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{
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outctx_t *ctx = va_arg(va, outctx_t *);
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bool analyze_only = va_argi(va, bool);
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data(*ctx, analyze_only);
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return 1;
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}
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case processor_t::ev_out_special_item:
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{
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outctx_t *ctx = va_arg(va, outctx_t *);
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uchar seg_type = va_argi(va, uchar);
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outspec(*ctx, seg_type);
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return 1;
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}
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case processor_t::ev_is_align_insn:
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{
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ea_t ea = va_arg(va, ea_t);
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return is_align_insn(ea);
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}
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default:
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break;
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}
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return code;
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}
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//-----------------------------------------------------------------------
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// TMS320C6x COFF Assembler
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//-----------------------------------------------------------------------
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static const asm_t dspasm =
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{
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AS_COLON | ASH_HEXF0 | ASD_DECF0 | ASB_BINF0 | ASO_OCTF5,
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0,
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"TMS320C6x COFF Assembler",
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0,
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NULL, // header lines
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NULL, // org
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".end",
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";", // comment string
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'"', // string delimiter
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'\'', // char delimiter
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"\\\"'", // special symbols in char and string constants
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".string", // ascii string directive
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".char", // byte directive
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".short", // word directive
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".long", // double words
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NULL, // no qwords
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NULL, // oword (16 bytes)
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NULL, // float (4 bytes)
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NULL, // double (8 bytes)
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NULL, // tbyte (10/12 bytes)
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NULL, // packed decimal real
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NULL, // arrays (#h,#d,#v,#s(...)
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".space %s", // uninited arrays
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".set", // equ
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NULL, // 'seg' prefix (example: push seg seg001)
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"$", // current IP (instruction pointer)
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NULL, // func_header
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NULL, // func_footer
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".def", // "public" name keyword
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NULL, // "weak" name keyword
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".ref", // "extrn" name keyword
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".usect", // "comm" (communal variable)
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NULL, // get_type_name
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".align", // "align" keyword
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'(', ')', // lbrace, rbrace
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NULL, // mod
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"&", // and
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"|", // or
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"^", // xor
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"!", // not
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"<<", // shl
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">>", // shr
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NULL, // sizeof
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};
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static const asm_t *const asms[] = { &dspasm, NULL };
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//-----------------------------------------------------------------------
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#define FAMILY "TMS320C6 series:"
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static const char *const shnames[] = { "TMS320C6", NULL };
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static const char *const lnames[] =
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{
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FAMILY"Texas Instruments TMS320C6xxx",
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NULL
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};
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//--------------------------------------------------------------------------
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static const uchar retcode_1[] = { 0x62, 0x63, 0x0C, 0x00 };
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static const bytes_t retcodes[] =
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{
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{ sizeof(retcode_1), retcode_1 },
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{ 0, NULL }
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};
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//-----------------------------------------------------------------------
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// Processor Definition
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//-----------------------------------------------------------------------
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processor_t LPH =
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{
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IDP_INTERFACE_VERSION, // version
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PLFM_TMSC6, // id
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// flag
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PR_USE32
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| PR_DEFSEG32
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| PR_DELAYED
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| PR_ALIGN_INSN, // allow align instructions
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// flag2
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0,
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8, // 8 bits in a byte for code segments
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8, // 8 bits in a byte for other segments
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shnames,
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lnames,
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asms,
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notify,
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RegNames, // Register names
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qnumber(RegNames), // Number of registers
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rVcs, // first
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rVds, // last
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0, // size of a segment register
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rVcs, rVds,
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NULL, // No known code start sequences
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retcodes,
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TMS6_null,
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TMS6_last,
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Instructions, // instruc
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0, // int tbyte_size;
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{ 2, 4, 8, 12 }, // char real_width[4];
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TMS6_null, // Icode of return instruction. It is ok to give any of possible return instructions
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};
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