358 lines
8.8 KiB
INI
358 lines
8.8 KiB
INI
; The format of the input file:
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; each device definition begins with a line like this:
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;
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; .devicename
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;
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; after it go the port definitions in this format:
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;
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; portname address
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;
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; the bit definitions (optional) are represented like this:
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;
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; portname.bitname bitnumber
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;
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; lines beginning with a space are ignored.
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; comment lines should be started with ';' character.
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;
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; the default device is specified at the start of the file
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;
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; .default device_name
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;
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; all lines non conforming to the format are passed to the callback function
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;
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; NSC CompactRISC CR16 SPECIFIC LINES
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;------------------------
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;
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; the processor definition may include the memory configuration.
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; the line format is:
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; area CLASS AREA-NAME START:END
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;
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; where CLASS is anything, but please use one of CODE, DATA, BSS
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; START and END are addresses, the end address is not included
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; Interrupt vectors are declared in the following way:
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; entry NAME ADDRESS COMMENT
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.default SC14402
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.SC14402
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; MEMORY MAP
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area DATA SRAM 0xEA00:0xEC00 Sequencer RAM
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area DATA IRAM 0xEC00:0xF400 Internal RAM
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area DATA DRAM 0xF400:0xFBFE Data RAM
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area DATA FSR 0xFBFE:0x10000 Special Function Register
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; Interrupt and reset vector assignments
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interrupt RESET_ 0x0000 RESET
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interrupt NMI_ 0x0004 NMI
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interrupt TRAP_SVC_ 0x000A Trap SVC
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interrupt TRAP_DVZ_ 0x000C Trap DVZ
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interrupt TRAP_FLG_ 0x000E Trap FLG
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interrupt TRAP_BPT_ 0x0010 Trap BPT
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interrupt TRAP_TRC_ 0x0012 Trap TRC
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interrupt TRAP_UND_ 0x0014 Trap UND
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interrupt ISE_ 0x001E ISE
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interrupt IRQ0_ 0x0020 SW INT
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interrupt IRQ1_ 0x0022 Keyboard IRQ
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interrupt IRQ2_ 0x0024 UART IRQ
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interrupt IRQ3_ 0x0026 Timer 0 IRQ
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interrupt IRQ4_ 0x0028 Timer 1 IRQ
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interrupt IRQ5_ 0x002A Clk 100 IRQ
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interrupt IRQ6_ 0x002C DIP IRQ
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; INPUT/OUTPUT
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DIPPC 0xFBFE DIP Programm Counter
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DIPCTRL 0xFBFF DIP Controll
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INTRESET 0xFF02 Reset Interrupt
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INTSET 0xFF03 Set Interrupt
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SWINTPRI 0xFF04 SW INT Priority
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KBINTPRI 0xFF05 KB INT Priority
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UARTINTPRI 0xFF06 UART INT Priority
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T0INTPRI 0xFF07 T0 INT Priority
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T1INTPRI 0xFF08 T1 INT Priority
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CLKINTPRI 0xFF09 CLK100 INT Priority
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DIPINTPRI 0xFF0A DIP INT Priority
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P0DATA 0xFF10 Port 0
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P0SET 0xFF11 Port 0 Set Bit
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P0RESET 0xFF12 Port 0 Reset Bit
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P0DIR 0xFF13 Port 0 Direction
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P0UARTCTL 0xFF14 Port 0 UART Controll
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P0UARTDATA 0xFF15 Port 0 UART Data Register
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P0ENV 0xFF16 Port 0 Environ
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P0TEST 0xFF17 Port 0 ADPCM/CODEC Testpoints
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P1DATA 0xFF20 Port 1
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P1SET 0xFF21 Port 1 Set Bit
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P1RESET 0xFF22 Port 1 Reset Bit
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P1DIR 0xFF23 Port 1 Direction
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P1INTENABLE 0xFF24 Port 1 Interrupt Enable
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P1FILTER 0xFF25 Port 1 debounce filter
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P2DATA 0xFF30 Port 2
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P2DIR 0xFF33 Port 2 Direction
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P2MODE 0xFF34 Port 2 Mode
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P2ADCCONTROLL 0xFF35 Port 2 ADC Controll
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P2ADCVALUE 0xFF36 Port 2 ADC Value
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P2DACVALUE 0xFF37 Port 2 DAC Value
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WTDG_RELOAD 0xFF40 Watchdog Reload
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T0RELOADMLO 0xFF42 Timer 0 Reload M Low
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T0RELOADMHI 0xFF43 Timer 0 Reload M Low
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T0RELOADNLO 0xFF44 Timer 0 Reload N Low
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T0RELOADNHI 0xFF45 Timer 0 Reload N Low
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T1RELOADMLO 0xFF46 Timer 1 Reload M Low
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T1RELOADMHI 0xFF47 Timer 1 Reload M Low
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T1RELOADNLO 0xFF48 Timer 1 Reload N Low
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T1RELOADNHI 0xFF49 Timer 1 Reload N Low
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TIMERCONTROLL 0xFF4A Timer Controll
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SBICLK 0xFF50 SBI Clock
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SBIBANK 0xFF51 SBI Bank
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SBIAUXCSLOW 0xFF52 SBI Aux chipselect controll low
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SBIAUXCSHIGH 0xFF53 SBI Aux chipselect controll high
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SBIAUXWAIT 0xFF54 SBI AUX Wait
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SBISETFREEZE 0xFF55 SBI Set Freeze
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SBIRESETFREEZE 0xFF56 SBI Reset Freeze
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DEBUGSFR 0xFF57 DEBUG Register
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.CR16MCS9
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; MEMORY MAP
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area CODE FLASH 0x0000:0xC000 Flash Program Memory
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area DATA SRAM 0xC000:0xCC00 Static RAM
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area DATA ISP 0xE000:0xE600 ISP Memory
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area DATA EEPROM 0xE800:0xF000 EEPROM
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area DATA EEPROM 0xF000:0xF080 EEPROM
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area DATA FSR 0xF400:0x10000 Peripherals
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; Interrupt and reset vector assignments
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interrupt RESET_ 0x0000 RESET
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;interrupt NMI_ 0x0004 NMI
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;interrupt TRAP_SVC_ 0x000A Trap SVC
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;interrupt TRAP_DVZ_ 0x000C Trap DVZ
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;interrupt TRAP_FLG_ 0x000E Trap FLG
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;interrupt TRAP_BPT_ 0x0010 Trap BPT
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;interrupt TRAP_TRC_ 0x0012 Trap TRC
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;interrupt TRAP_UND_ 0x0014 Trap UND
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;interrupt ISE_ 0x001E ISE
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;interrupt IRQ0_ 0x0020 SW INT
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;interrupt IRQ1_ 0x0022 Keyboard IRQ
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;interrupt IRQ2_ 0x0024 UART IRQ
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;interrupt IRQ3_ 0x0026 Timer 0 IRQ
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;interrupt IRQ4_ 0x0028 Timer 1 IRQ
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;interrupt IRQ5_ 0x002A Clk 100 IRQ
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;interrupt IRQ6_ 0x002C DIP IRQ
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; INPUT/OUTPUT
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BCFG 0xf900
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IOCFG 0xf902
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SZCFG0 0xf904
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SZCFG1 0xf906
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SZCFG2 0xf908
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MCFG 0xf910
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DBGCFG 0xf912
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MSTAT 0xf914
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TMODE 0xf920
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FLCTRL1 0xf930
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FLSEC 0xf932
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ISPKEY 0xf934
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FLCTRL2 0xf936
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DMCSR 0xf940
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DMPSLR 0xf942
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DMSTART 0xf944
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DMTRAN 0xf946
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DMPROG 0xf948
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DMERASE 0xf94a
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DMEND 0xf94c
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DMPCNT 0xf94e
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DMCNT 0xf950
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DMISTAT 0xf952
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DMKEY 0xf954
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FLCSR 0xf960
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FLPSLR 0xf962
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FLSTART 0xf964
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FLTRAN 0xf966
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FLPROG 0xf968
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FLERASE 0xf96a
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FLEND 0xf96c
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FLPCNT 0xf96e
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FLCNT1 0xf970
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FLCNT2 0xf972
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PGMKEY 0xf974
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PBDIR 0xfb00
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PBDIN 0xfb02
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PBDOUT 0xfb04
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PBWKPU 0xfb06
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PCDIR 0xfb10
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PCDIN 0xfb12
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PCDOUT 0xfb14
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PCWKPU 0xfb16
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PFALT 0xfd20
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PFDIR 0xfd22
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PFDIN 0xfd24
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PFDOUT 0xfd26
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PFWKPU 0xfd28
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PFSCHEN 0xfd2a
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PGALT 0xfca0
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PGDIR 0xfca2
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PGDIN 0xfca4
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PGDOUT 0xfca6
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PGWKPU 0xfca8
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PGSCHEN 0xfcaa
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PHALT 0xfcc0
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PHDIR 0xfcc2
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PHDIN 0xfcc4
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PHDOUT 0xfcc6
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PHWKPU 0xfcc8
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PIALT 0xfee0
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PIDIR 0xfee2
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PIDIN 0xfee4
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PIDOUT 0xfee6
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PIWKPU 0xfee8
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PISCHEN 0xfeea
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PLALT 0xff00
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PLDIR 0xff02
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PLDIN 0xff04
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PLDOUT 0xff06
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PLWKPU 0xff08
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PLSCHEN 0xff0a
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CRCTRL 0xfc40
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PRSSC 0xfc42
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PRSSC1 0xfc44
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PMCSR 0xfc60
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WKEDG 0xfc80
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WKENA 0xfc82
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WKICTL 0xfc84
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WKICTL2 0xfc86
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WKPND 0xfc88
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WKPCL 0xfc8a
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IVCT 0xfe00
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NMISTAT 0xfe02
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EXNMI 0xfe04
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NMIIMNTR 0xfe06
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ISTAT0 0xfe0a
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ISTAT1 0xfe0c
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IENAM0 0xfe0e
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IENAM1 0xfe10
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IDBG 0xfe1a
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ITEST0 0xfe1c
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ITEST1 0xfe1e
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U1TBUF 0xfe40
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U1RBUF 0xfe42
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U1ICTRL 0xfe44
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U1STAT 0xfe46
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U1FRS 0xfe48
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U1MDSL 0xfe4a
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U1BAUD 0xfe4c
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U1PSR 0xfe4e
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U2TBUF 0xfe80
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U2RBUF 0xfe82
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U2ICTRL 0xfe84
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U2STAT 0xfe86
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U2FRS 0xfe88
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U2MDSL 0xfe8a
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U2BAUD 0xfe8c
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U2PSR 0xfe8e
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ACBSDA 0xfec0
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ACBST 0xfec2
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ACBCST 0xfec4
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ACBCTL1 0xfec6
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ACBADDR 0xfec8
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ACBCTL2 0xfeca
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MWDAT 0xfe60
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MWCTL 0xfe62
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MWSTAT 0xfe64
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MWTEST 0xfe66
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TWCFG 0xff20
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TWCP 0xff22
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TWMT0 0xff24
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T0CSR 0xff26
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WDCNT 0xff28
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WDSDM 0xff2a
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T1CNT1 0xff40
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T1CRA 0xff42
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T1CRB 0xff44
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T1CNT2 0xff46
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T1PRSC 0xff48
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T1CKC 0xff4A
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T1CTRL 0xff4C
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T1ICTL 0xff4E
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T1ICLR 0xff50
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T2CNT1 0xff60
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T2CRA 0xff62
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T2CRB 0xff64
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T2CNT2 0xff66
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T2PRSC 0xff68
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T2CKC 0xff6A
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T2CTRL 0xff6C
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T2ICTL 0xff6E
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T2ICLR 0xff70
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MODE 0xff80
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IO1CTL 0xff82
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IO2CTL 0xff84
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INTCTL 0xff86
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INTPND 0xff88
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CLK1PS 0xff8a
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COUNT1 0xff8c
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PERCAP1 0xff8e
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DTYCAP1 0xff90
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COUNT2 0xff92
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PERCAP2 0xff94
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DTYCAP2 0xff96
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CLK2PS 0xff98
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COUNT3 0xff9a
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PERCAP3 0xff9c
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DTYCAP3 0xff9e
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COUNT4 0xffa0
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PERCAP4 0xffa2
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DTYCAP4 0xffa4
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ADCST 0xffC0
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ADCCNT1 0xffC2
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ADCCNT2 0xffC4
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ADCCNT3 0xffC6
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ADCENG 0xffC8
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ADDATA0 0xffCA
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ADDATA1 0xffCC
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ADDATA2 0xffCE
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ADDATA3 0xffD0
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ACMP 0xffe0
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CMB0_CNTSTAT 0xf400
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CMB0_TSTP 0xf402
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CMB0_DATA3 0xf404
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CMB0_DATA2 0xf406
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CMB0_DATA1 0xf408
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CMB0_DATA0 0xf40a
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CMB0_ID0 0xf40c
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CMB0_ID1 0xf40e
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CMB1 0xf410
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CMB2 0xf420
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CMB3 0xf430
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CMB4 0xf440
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CMB5 0xf450
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CMB6 0xf460
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CMB7 0xf470
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CMB8 0xf480
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CMB9 0xf490
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CMB10 0xf4a0
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CMB11 0xf4b0
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CMB12 0xf4c0
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CMB13 0xf4d0
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CMB14 0xf4e0
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CMB15 0xf4f0
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CGCR 0xf500
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CTIM 0xf502
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GMSKX 0xf504
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GMSKB 0xf506
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BMSKX 0xf508
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BMSKB 0xf50a
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CIEN 0xf50c
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CIPND 0xf50e
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CICLR 0xf510
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CICEN 0xf512
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CSTPND 0xf514
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CANEC 0xf516
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CEDIAG 0xf518
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CTMR 0xf51a
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BSPD 0xf51c
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RTDIAG 0xf51e
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