398 lines
11 KiB
C++
398 lines
11 KiB
C++
/*
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* Interactive disassembler (IDA).
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* Copyright (c) 1990-99 by Ilfak Guilfanov.
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* ALL RIGHTS RESERVED.
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* E-mail: ig@datarescue.com
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*
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*
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*/
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#include "tms320c55.hpp"
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#include <segregs.hpp>
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#include <frame.hpp>
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//------------------------------------------------------------------------
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ea_t calc_data_mem(const insn_t &insn, const op_t &op)
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{
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ea_t addr = op.addr;
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sel_t dph = 0;
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if ( op.tms_regH == DPH )
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{
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dph = get_sreg(to_ea(insn.cs, insn.ip), DPH);
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if ( dph == BADSEL )
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return BADSEL;
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addr &= 0xFFFF;
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}
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sel_t dp = 0;
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if ( op.tms_regP == DP )
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{
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dp = get_sreg(to_ea(insn.cs, insn.ip), DP);
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if ( dp == BADSEL )
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return BADSEL;
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addr &= 0xFFFF;
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}
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return (((dph & 0x7F) << 16) | (dp + addr)) << 1;
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}
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//----------------------------------------------------------------------
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ea_t calc_io_mem(const insn_t &insn, const op_t &op)
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{
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ea_t addr = op.addr;
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sel_t pdp = 0;
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if ( op.tms_regP == PDP )
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{
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pdp = get_sreg(to_ea(insn.cs, insn.ip), PDP);
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if ( pdp == BADSEL )
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return BADSEL;
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addr &= 0x7F;
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}
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ea_t ea = ((pdp & 0x1FF) << 7) | addr;
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return to_ea(insn.cs, ea);
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}
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//----------------------------------------------------------------------
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int tms320c55_t::get_mapped_register(ea_t ea) const
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{
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ea = ea >> 1;
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if ( idpflags & TMS320C55_MMR )
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{
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static const int registers[] =
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{
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IER0, IFR0, ST0_55, ST1_55, ST3_55, -1, ST0, ST1,
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AC0L, AC0H, AC0G, AC1L, AC1H, AC1G, T3, TRN0,
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AR0, AR1, AR2, AR3, AR4, AR5, AR6, AR7,
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SP, BK03, BRC0, RSA0L, REA0L, PMST, XPC, -1,
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T0, T1, T2, T3, AC2L, AC2H, AC2G, CDP,
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AC3L, AC3H, AC3H, DPH, -1, -1, DP, PDP,
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BK47, BKC, BSA01, BSA23, BSA45, BSA67, BSAC, -1,
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TRN1, BRC1, BRS1, CSR, RSA0H, RSA0L, REA0H, REA0L,
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RSA1H, RSA1L, REA1H, REA1L, RPTC, IER1, IFR1, DBIER0,
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DBIER1, IVPD, IVPH, ST2_55, SSP, SP, SPH, CDPH
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};
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if ( ea <= 0x4F )
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return registers[int(ea)];
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}
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return -1;
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}
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//----------------------------------------------------------------------
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static void process_imm(const insn_t &insn, const op_t &x, flags_t F)
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{
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set_immd(insn.ea); // assign contextual menu for conversions
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if ( is_defarg(F, x.n) )
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return; // if already defined by user
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switch ( insn.itype )
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{
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case TMS320C55_rptcc:
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case TMS320C55_rpt:
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case TMS320C55_aadd:
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case TMS320C55_amov:
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case TMS320C55_asub:
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case TMS320C55_mov2:
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case TMS320C55_and3:
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case TMS320C55_or3:
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case TMS320C55_xor2:
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case TMS320C55_xor3:
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case TMS320C55_mpyk2:
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case TMS320C55_mpyk3:
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case TMS320C55_mpykr2:
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case TMS320C55_mpykr3:
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case TMS320C55_mack3:
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case TMS320C55_mack4:
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case TMS320C55_mackr3:
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case TMS320C55_mackr4:
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case TMS320C55_bclr2:
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case TMS320C55_bset2:
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case TMS320C55_rptadd:
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case TMS320C55_rptsub:
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case TMS320C55_add2:
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case TMS320C55_add3:
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case TMS320C55_sub2:
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case TMS320C55_sub3:
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case TMS320C55_and2:
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case TMS320C55_or2:
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case TMS320C55_intr:
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case TMS320C55_trap:
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case TMS320C55_btst:
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op_num(insn.ea, x.n);
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}
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}
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//----------------------------------------------------------------------
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void tms320c55_t::handle_operand(const insn_t &insn, const op_t &op, flags_t F, bool use)
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{
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switch ( op.type )
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{
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case o_cond:
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case o_shift:
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case o_io:
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return;
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case o_reg:
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// analyze immediate values
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if ( op.tms_modifier == TMS_MODIFIER_REG_OFFSET
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|| op.tms_modifier == TMS_MODIFIER_P_REG_OFFSET
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|| op.tms_modifier == TMS_MODIFIER_REG_SHORT_OFFSET )
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{
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set_immd(insn.ea);
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}
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// analyze local vars
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if ( op.reg == SP && op.tms_modifier == TMS_MODIFIER_REG_OFFSET )
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{
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if ( may_create_stkvars()
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&& get_func(insn.ea) != NULL
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&& insn.create_stkvar(op, 2 * op.value, STKVAR_VALID_SIZE) )
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{
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op_stkvar(insn.ea, op.n);
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}
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}
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// DP, DPH and PDP unknown changes
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if ( !use )
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{
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if ( op.reg == DP || op.reg == DPH || op.reg == PDP )
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split_sreg_range(get_item_end(insn.ea), op.reg, BADSEL, SR_auto);
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}
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break;
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case o_relop: // analyze immediate value
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if ( op.tms_relop_type == TMS_RELOP_IMM )
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set_immd(insn.ea);
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break;
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case o_near:
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{
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if ( insn.itype != TMS320C55_rptb && insn.itype != TMS320C55_rptblocal )
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{
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cref_t ftype = fl_JN;
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ea_t ea = calc_code_mem(insn, op.addr);
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if ( has_insn_feature(insn.itype, CF_CALL) )
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{
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if ( !func_does_return(ea) )
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flow = false;
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ftype = fl_CN;
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}
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#ifndef TMS320C55_NO_NAME_NO_REF
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insn.add_cref(ea, op.offb, ftype);
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#endif
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}
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#ifndef TMS320C55_NO_NAME_NO_REF
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else // evaluate RPTB loops as dref
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insn.add_dref(calc_code_mem(insn, op.addr), op.offb, dr_I);
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#endif
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break;
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}
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case o_imm:
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QASSERT(10114, use);
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process_imm(insn, op, F);
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#ifndef TMS320C55_NO_NAME_NO_REF
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if ( op_adds_xrefs(F, op.n) )
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insn.add_off_drefs(op, dr_O, op.tms_signed ? OOF_SIGNED : 0);
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#endif
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break;
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case o_mem:
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{
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ea_t ea = calc_data_mem(insn, op);
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if ( ea != BADADDR )
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{
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#ifndef TMS320C55_NO_NAME_NO_REF
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insn.add_dref(ea, op.offb, use ? dr_R : dr_W);
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#endif
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insn.create_op_data(ea, op);
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if ( !use )
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{
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int reg = get_mapped_register(ea);
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if ( reg == DP || reg == DPH || reg == PDP )
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split_sreg_range(get_item_end(insn.ea), reg, BADSEL, SR_auto);
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}
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}
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}
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break;
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default:
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warning("interr: emu2 address:%a operand:%d type:%d", insn.ea, op.n, op.type);
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}
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}
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//----------------------------------------------------------------------
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static bool add_stkpnt(const insn_t &insn, sval_t delta)
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{
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func_t *pfn = get_func(insn.ea);
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if ( pfn == NULL )
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return false;
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return add_auto_stkpnt(pfn, insn.ea+insn.size, delta);
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}
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//----------------------------------------------------------------------
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static void trace_sp(const insn_t &insn)
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{
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switch ( insn.itype )
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{
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case TMS320C55_pop1: // pop dst; pop dbl(ACx); pop Smem; pop dbl(Lmem)
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add_stkpnt(insn, (insn.Op1.tms_operator1 & TMS_OPERATOR_DBL) ? 4:2);
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break;
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case TMS320C55_pop2: // pop dst1, dst2; pop dst, Smem
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add_stkpnt(insn, 4);
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break;
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case TMS320C55_psh1: // psh dst; psh dbl(ACx); psh Smem; psh dbl(Lmem)
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add_stkpnt(insn, (insn.Op1.tms_operator1 & TMS_OPERATOR_DBL) ? -4:-2);
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break;
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case TMS320C55_psh2: // psh src1, src2; psh src, Smem
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add_stkpnt(insn, -4);
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break;
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case TMS320C55_popboth:
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case TMS320C55_ret:
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add_stkpnt(insn, 2);
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break;
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case TMS320C55_pshboth:
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add_stkpnt(insn, -2);
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break;
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case TMS320C55_reti:
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add_stkpnt(insn, 6);
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break;
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case TMS320C55_aadd:
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if ( insn.Op2.type == o_reg && insn.Op2.reg == SP && insn.Op1.type == o_imm )
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add_stkpnt(insn, 2 * insn.Op1.value);
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break;
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}
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}
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//----------------------------------------------------------------------
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int tms320c55_t::emu(const insn_t &insn)
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{
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uint32 feature = insn.get_canon_feature(ph);
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flow = (feature & CF_STOP) == 0;
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flags_t F = get_flags(insn.ea);
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if ( feature & CF_USE1 ) handle_operand(insn, insn.Op1, F, true);
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if ( feature & CF_USE2 ) handle_operand(insn, insn.Op2, F, true);
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if ( feature & CF_USE3 ) handle_operand(insn, insn.Op3, F, true);
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if ( feature & CF_USE4 ) handle_operand(insn, insn.Op4, F, true);
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if ( feature & CF_USE5 ) handle_operand(insn, insn.Op5, F, true);
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if ( feature & CF_USE6 ) handle_operand(insn, insn.Op6, F, true);
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if ( feature & CF_CHG1 ) handle_operand(insn, insn.Op1, F, false);
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if ( feature & CF_CHG2 ) handle_operand(insn, insn.Op2, F, false);
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if ( feature & CF_CHG3 ) handle_operand(insn, insn.Op3, F, false);
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if ( feature & CF_CHG4 ) handle_operand(insn, insn.Op4, F, false);
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if ( feature & CF_CHG5 ) handle_operand(insn, insn.Op5, F, false);
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if ( feature & CF_CHG6 ) handle_operand(insn, insn.Op6, F, false);
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// CPL and ARMS status flags changes
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if ( (insn.itype == TMS320C55_bclr1 || insn.itype == TMS320C55_bset1)
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&& insn.Op1.type == o_reg
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&& (insn.Op1.reg == CPL || insn.Op1.reg == ARMS) )
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{
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int value = insn.itype == TMS320C55_bclr1 ? 0 : 1;
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split_sreg_range(get_item_end(insn.ea), insn.Op1.reg, value, SR_auto);
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}
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// DP, DPH and PDP changes
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if ( insn.itype == TMS320C55_mov2
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&& insn.Op2.type == o_reg
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&& insn.Op1.type == o_imm )
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{
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ea_t end = insn.ea + insn.size;
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if ( insn.Op2.reg == DP )
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split_sreg_range(end, DP, insn.Op1.value & 0xFFFF, SR_auto);
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else if ( insn.Op2.reg == DPH )
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split_sreg_range(end, DPH, insn.Op1.value & 0x7F, SR_auto);
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else if ( insn.Op2.reg == PDP )
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split_sreg_range(end, PDP, insn.Op1.value & 0x1FF, SR_auto);
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}
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// determine if the next instruction should be executed
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if ( flow && segtype(insn.ea) == SEG_XTRN )
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flow = false;
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if ( flow )
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add_cref(insn.ea, insn.ea+insn.size, fl_F);
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if ( may_trace_sp() )
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{
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if ( !flow )
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recalc_spd(insn.ea); // recalculate SP register for the next insn
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else
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trace_sp(insn);
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}
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return 1;
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}
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//----------------------------------------------------------------------
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bool idaapi create_func_frame(func_t *pfn)
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{
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if ( pfn != NULL )
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{
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if ( pfn->frame == BADNODE )
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{
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insn_t insn;
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ushort regsize = 0;
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ea_t ea = pfn->start_ea;
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while ( ea < pfn->end_ea ) // check for register pushs
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{
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decode_insn(&insn, ea);
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ea += insn.size;
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if ( insn.itype == TMS320C55_psh1 )
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regsize += (insn.Op1.tms_operator1 & TMS_OPERATOR_DBL) ? 4 : 2;
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else if ( insn.itype == TMS320C55_psh2 )
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regsize += 4;
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else if ( insn.itype == TMS320C55_pshboth )
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regsize += 2;
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else
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break;
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}
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int localsize = 0;
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while ( ea < pfn->end_ea ) // check for frame creation
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{
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if ( decode_insn(&insn, ea) < 1 )
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break;
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ea += insn.size;
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if ( insn.itype == TMS320C55_aadd
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&& insn.Op2.type == o_reg
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&& insn.Op2.reg == SP
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&& insn.Op1.type == o_imm )
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{
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localsize = int(2 * insn.Op1.value);
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break;
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}
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}
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add_frame(pfn, localsize, regsize, 0);
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}
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}
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return 0;
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}
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//----------------------------------------------------------------------
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int idaapi is_align_insn(ea_t ea)
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{
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insn_t insn;
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if ( decode_insn(&insn, ea) < 1 )
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return 0;
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switch ( insn.itype )
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{
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case TMS320C55_nop:
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case TMS320C55_nop_16:
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break;
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default:
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return 0;
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}
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return insn.size;
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}
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//----------------------------------------------------------------------
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bool idaapi can_have_type(const op_t &op)
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{
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switch ( op.type )
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{
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case o_io:
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case o_reg:
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case o_relop:
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case o_imm:
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return true;
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}
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return false;
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}
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