419 lines
12 KiB
C++
419 lines
12 KiB
C++
/*
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* Interactive disassembler (IDA).
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* Copyright (c) 1990-99 by Ilfak Guilfanov.
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* ALL RIGHTS RESERVED.
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* E-mail: ig@datarescue.com
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*
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*
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*/
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#include "tms320c3x.hpp"
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#include <frame.hpp>
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#include <segregs.hpp>
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#include <struct.hpp>
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// simple wrapper class for syntactic sugar of member functions
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// this class may have only simple member functions.
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// virtual functions and data fields are forbidden, otherwise the class
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// layout may change
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class out_tms320c3_t : public outctx_t
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{
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out_tms320c3_t(void) = delete; // not used
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public:
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bool out_operand(const op_t &x);
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void out_insn(void);
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void out_proc_mnem(void);
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void out_address(ea_t ea, const op_t &x, bool at);
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};
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CASSERT(sizeof(out_tms320c3_t) == sizeof(outctx_t));
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DECLARE_OUT_FUNCS(out_tms320c3_t)
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//----------------------------------------------------------------------
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#define SYM(x) COLSTR(x, SCOLOR_SYMBOL)
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#define REG(x) COLSTR(x, SCOLOR_REG)
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#define REGP(x) SYM("(") REG(x) SYM(")")
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// o_phrase output format strings, indexed by phtype
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static const char *const formats[0x1a] =
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{
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SYM("*+") REG("%s"), // 0 "*+arn(NN)"
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SYM("*-") REG("%s"), // 1 "*-arn(NN)"
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SYM("*++") REG("%s"), // 2 "*++arn(NN)"
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SYM("*--") REG("%s"), // 3 "*--arn(NN)"
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SYM("*") REG("%s") SYM("++"), // 4 "*arn++(NN)"
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SYM("*") REG("%s") SYM("--"), // 5 "*arn--(NN)"
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SYM("*") REG("%s") SYM("++"), // 6 "*arn++(NN)%"
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SYM("*") REG("%s") SYM("--"), // 7 "*arn--(NN)%"
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SYM("*+") REG("%s") REGP("ir0"), // 8 "*+arn(ir0)"
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SYM("*-") REG("%s") REGP("ir0"), // 9 "*-arn(ir0)"
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SYM("*++") REG("%s") REGP("ir0"), // a "*++arn(ir0)"
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SYM("*--") REG("%s") REGP("ir0"), // b "*--arn(ir0)"
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SYM("*") REG("%s") SYM("++") REGP("ir0"), // c "*arn++(ir0)"
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SYM("*") REG("%s") SYM("--") REGP("ir0"), // d "*arn--(ir0)"
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SYM("*") REG("%s") SYM("++") REGP("ir0") SYM("%%"), // e "*arn++(ir0)%"
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SYM("*") REG("%s") SYM("--") REGP("ir0") SYM("%%"), // f "*arn--(ir0)%"
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SYM("*+") REG("%s") REGP("ir1"), // 10 "*+arn(ir1)"
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SYM("*-") REG("%s") REGP("ir1"), // 11 "*-arn(ir1)"
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SYM("*++") REG("%s") REGP("ir1"), // 12 "*++arn(ir1)"
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SYM("*--") REG("%s") REGP("ir1"), // 13 "*--arn(ir1)"
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SYM("*") REG("%s") SYM("++") REGP("ir1"), // 14 "*arn++(ir1)"
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SYM("*") REG("%s") SYM("--") REGP("ir1"), // 15 "*arn--(ir1)"
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SYM("*") REG("%s") SYM("++") REGP("ir1") SYM("%%"), // 16 "*arn++(ir1)%"
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SYM("*") REG("%s") SYM("--") REGP("ir1") SYM("%%"), // 17 "*arn--(ir1)%"
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SYM("*") REG("%s"), // 18 "*arn"
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SYM("*") REG("%s") SYM("++") REGP("ir0") SYM("B"), // 19 "*arn++(ir0)B"
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};
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//--------------------------------------------------------------------------
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static const char *const cc_text[] =
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{
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// Unconditional compares
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"u", // Unconditional
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// Unsigned compares
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"lo", // Lower than
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"ls", // Lower than or same as
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"hi", // Higher than
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"hs", // Higher than or same as
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"e", // Equal to
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"ne", // Not equal to
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// Signed compares
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"lt", // Less than
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"le", // Less than or equal to
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"gt", // Greater than
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"ge", // Greater than or equal to
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// Unknown
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"?", // Unknown
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// Compare to condition flags
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"nv", // No overflow
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"v", // Overflow
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"nuf", // No underflow
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"uf", // Underflow
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"nlv", // No latched overflow
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"lv", // Latched overflow
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"nluf", // No latched floating-point underflow
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"luf", // Latched floating-point underflow
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"zuf" // Zero or floating-point underflow
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};
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//----------------------------------------------------------------------
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void out_tms320c3_t::out_address(ea_t ea, const op_t &x, bool at)
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{
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qstring qbuf;
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if ( get_name_expr(&qbuf, insn.ea+x.offb, x.n, ea, ea) > 0 )
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{
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if ( at )
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out_symbol('@');
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out_line(qbuf.begin());
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}
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else
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{
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if ( at )
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out_symbol('@');
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out_tagon(COLOR_ERROR);
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out_value(x, OOFW_IMM|OOF_ADDR|OOFW_16);
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out_printf(" (ea = %a)", ea);
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out_tagoff(COLOR_ERROR);
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remember_problem(PR_NONAME, insn.ea);
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}
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}
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//----------------------------------------------------------------------
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bool out_tms320c3_t::out_operand(const op_t &x)
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{
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ea_t ea;
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char buf[MAXSTR];
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switch ( x.type )
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{
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case o_void:
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return 0;
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case o_reg:
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out_register(ph.reg_names[x.reg]);
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break;
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case o_near:
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out_address(calc_code_mem(insn, x), x, false);
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break;
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case o_imm:
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if ( insn.itype != TMS320C3X_TRAPcond )
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out_symbol('#');
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if ( insn.auxpref & ImmFltFlag )
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{
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int16 v = int16(x.value);
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print_fpval(buf, sizeof(buf), &v, 2);
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out_line(buf[0] == ' ' ? &buf[1] : buf, COLOR_NUMBER);
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}
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else
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{
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out_value(x, OOFW_IMM);
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}
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break;
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case o_mem:
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ea = calc_data_mem(insn, x);
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if ( ea != BADADDR )
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{
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out_address(ea, x, true);
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}
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else
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{
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out_tagon(COLOR_ERROR);
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out_value(x, OOFW_IMM|OOF_ADDR|OOFW_16);
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out_tagoff(COLOR_ERROR);
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}
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break;
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case o_phrase: // Indirect addressing mode
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{
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if ( x.phrase < qnumber(formats) )
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{
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op_t y = x;
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bool outdisp = x.phrase < 8;
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bool printmod = x.phrase >= 6;
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if ( x.phrase == 0x18 )
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{
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// this is *arn phrase
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// check if we need to print the displacement
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int n = x.n;
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if ( is_off(F, n) || is_stkvar(F, n) || is_enum(F, n) || is_stroff(F, n) )
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{
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outdisp = true;
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y.addr = 0;
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printmod = false;
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y.phrase = 0; // use '*+arn(NN)' syntax
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}
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}
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// print the base part
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const char *reg = ph.reg_names[uchar(y.phtype)];
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nowarn_qsnprintf(buf, sizeof(buf), formats[uchar(y.phrase)], reg);
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out_colored_register_line(buf);
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// print the displacement
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if ( outdisp )
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{
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out_symbol('(');
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out_value(y, OOFS_IFSIGN|OOF_ADDR|OOFW_32);
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out_symbol(')');
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if ( printmod )
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out_symbol('%'); // %: circular modify
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}
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}
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else
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{
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out_line("<bad indirect>", COLOR_ERROR);
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}
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break;
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}
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default:
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INTERR(10261);
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}
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return 1;
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}
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//----------------------------------------------------------------------
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void out_tms320c3_t::out_proc_mnem(void)
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{
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char postfix[8];
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postfix[0] = '\0';
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switch ( insn.itype )
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{
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case TMS320C3X_LDFcond:
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case TMS320C3X_LDIcond:
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case TMS320C3X_Bcond:
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case TMS320C3X_DBcond:
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case TMS320C3X_CALLcond:
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case TMS320C3X_TRAPcond:
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case TMS320C3X_RETIcond:
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case TMS320C3X_RETScond:
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qstrncpy(postfix, cc_text[insn.auxpref & 0x1f ], sizeof(postfix));
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if ( insn.auxpref & DBrFlag ) // delayed branch?
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qstrncat(postfix, "d", sizeof(postfix));
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break;
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}
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out_mnem(8, postfix);
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}
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//----------------------------------------------------------------------
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void out_tms320c3_t::out_insn(void)
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{
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out_mnemonic();
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// following operand combinations exist:
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// 0, 1, 2, 3 for non-parallel
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// 2+2, 3+2, 3+3 for parallel
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out_one_operand(0); // two operands can be printed always
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if ( insn.Op2.type != o_void )
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{
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out_symbol(',');
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out_one_operand(1);
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}
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if ( insn.itype2 ) // Parallel
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{
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if ( insn.i2op > 2 ) // 3rd operand is for first instruction half
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{
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out_symbol(',');
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out_one_operand(2);
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}
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flush_outbuf();
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char insn2[MAXSTR];
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qsnprintf(insn2, sizeof(insn2), "||%s", ph.instruc[uchar(insn.itype2)].name);
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::add_spaces(insn2, sizeof(insn2), 8);
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out_line(insn2, COLOR_INSN);
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if ( insn.i2op == 2 ) // 3rd operand is for second instruction half
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{
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out_one_operand(2);
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out_symbol(',');
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}
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if ( insn.Op4.type != o_void )
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out_one_operand(3);
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if ( insn.Op5.type != o_void )
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{
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out_symbol(',');
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out_one_operand(4);
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}
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if ( insn.Op6.type != o_void )
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{
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out_symbol(',');
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out_one_operand(5);
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}
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}
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else if ( insn.Op3.type != o_void )
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{
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out_symbol(',');
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out_one_operand(2);
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}
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out_immchar_cmts();
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flush_outbuf();
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}
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//--------------------------------------------------------------------------
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void tms320c3x_t::print_segment_register(outctx_t &ctx, int reg, sel_t value)
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{
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if ( reg == ph.reg_data_sreg )
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return;
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if ( value != BADADDR )
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{
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char buf[MAX_NUMBUF];
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btoa(buf, sizeof(buf), value);
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ctx.gen_cmt_line("assume %s = %s", ph.reg_names[reg], buf);
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}
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else
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{
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ctx.gen_cmt_line("drop %s", ph.reg_names[reg]);
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}
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}
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//--------------------------------------------------------------------------
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// function to produce assume directives
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//lint -e{1764} ctx could be const
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void tms320c3x_t::assumes(outctx_t &ctx)
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{
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ea_t ea = ctx.insn_ea;
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segment_t *seg = getseg(ea);
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if ( (inf_get_outflags() & OFLG_GEN_ASSUME) == 0 || seg == NULL )
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return;
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bool seg_started = (ea == seg->start_ea);
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for ( int i = ph.reg_first_sreg; i <= ph.reg_last_sreg; ++i )
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{
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if ( i == ph.reg_code_sreg )
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continue;
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sreg_range_t sra;
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if ( !get_sreg_range(&sra, ea, i) )
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continue;
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if ( seg_started || sra.start_ea == ea )
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{
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sel_t now = get_sreg(ea, i);
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sreg_range_t prev;
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bool prev_exists = get_sreg_range(&prev, ea-1, i);
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if ( seg_started || (prev_exists && get_sreg(prev.start_ea, i) != now) )
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print_segment_register(ctx, i, now);
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}
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}
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}
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//--------------------------------------------------------------------------
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//lint -e{818} seg could be const
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void tms320c3x_t::segstart(outctx_t &ctx, segment_t *seg) const
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{
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if ( is_spec_segm(seg->type) )
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return;
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qstring sclas;
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get_segm_class(&sclas, seg);
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if ( sclas == "CODE" )
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ctx.gen_printf(DEFAULT_INDENT, COLSTR(".text", SCOLOR_ASMDIR));
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else if ( sclas == "DATA" )
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ctx.gen_printf(DEFAULT_INDENT, COLSTR(".data", SCOLOR_ASMDIR));
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if ( seg->orgbase != 0 )
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{
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char buf[MAX_NUMBUF];
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btoa(buf, sizeof(buf), seg->orgbase);
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ctx.gen_printf(DEFAULT_INDENT, COLSTR("%s %s", SCOLOR_ASMDIR), ash.origin, buf);
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}
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}
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//--------------------------------------------------------------------------
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void idaapi segend(outctx_t &, segment_t *)
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{
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}
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//--------------------------------------------------------------------------
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void tms320c3x_t::header(outctx_t &ctx)
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{
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ctx.gen_header(GH_PRINT_ALL | GH_BYTESEX_HAS_HIGHBYTE, NULL, ioh.device.c_str());
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ctx.gen_empty_line();
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}
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//--------------------------------------------------------------------------
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void tms320c3x_t::footer(outctx_t &ctx) const
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{
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ctx.gen_printf(DEFAULT_INDENT,COLSTR("%s",SCOLOR_ASMDIR),ash.end);
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}
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//--------------------------------------------------------------------------
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void tms320c3x_t::gen_stkvar_def(outctx_t &ctx, const member_t *mptr, sval_t v) const
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{
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char sign = ' ';
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if ( v < 0 )
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{
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sign = '-';
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v = -v;
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}
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qstring name = get_member_name(mptr->id);
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char vstr[MAX_NUMBUF];
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btoa(vstr, sizeof(vstr), v);
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ctx.out_printf(COLSTR("%s",SCOLOR_KEYWORD)
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COLSTR("%c%s",SCOLOR_DNUM)
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COLSTR(",",SCOLOR_SYMBOL) " "
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COLSTR("%s",SCOLOR_LOCNAME),
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ash.a_equ,
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sign,
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vstr,
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name.c_str());
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}
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