266 lines
6.6 KiB
C++
266 lines
6.6 KiB
C++
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#include "sam8.hpp"
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//----------------------------------------------------------------------
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class out_sam8_t : public outctx_t
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{
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out_sam8_t(void) = delete; // not used
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public:
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void OutRegString(bool isWorkingReg, bool isPair, int regNum, int regBit = -1);
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void OutAddr(const op_t &x, ea_t ea, ea_t off, bool isSigned = false);
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bool out_operand(const op_t &x);
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void out_insn(void);
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};
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CASSERT(sizeof(out_sam8_t) == sizeof(outctx_t));
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DECLARE_OUT_FUNCS_WITHOUT_OUTMNEM(out_sam8_t)
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//----------------------------------------------------------------------
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void out_sam8_t::OutRegString(bool isWorkingReg, bool isPair, int regNum, int regBit)
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{
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char buf[256];
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// if it is a working register, output it with an R in front
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if ( isWorkingReg )
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{
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if ( !isPair )
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qsnprintf(buf, sizeof(buf), "R%u", (unsigned int) regNum);
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else
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qsnprintf(buf, sizeof(buf), "RR%u", (unsigned int) regNum);
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}
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else
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{
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// output either working or non-working reg
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if ( !isPair )
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{
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// N.B. working registers start at 0xC0
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if ( regNum >= 0xC0 )
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qsnprintf(buf, sizeof(buf), "R%u", (unsigned int) (regNum - 0xC0));
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else
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qsnprintf(buf, sizeof(buf), "0%XH", regNum);
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}
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else
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{
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// N.B. working registers start at 0xC0
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if ( regNum >= 0xC0 )
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qsnprintf(buf, sizeof(buf), "RR%u", (unsigned int) regNum - 0xC0);
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else
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qsnprintf(buf, sizeof(buf), "0%XH", regNum);
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}
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}
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out_register(buf);
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// output regBit if requested
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if ( regBit != -1 )
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{
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qsnprintf(buf, sizeof(buf), ".%i", regBit);
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out_line(buf, COLOR_DEFAULT);
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}
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}
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//----------------------------------------------------------------------
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void out_sam8_t::OutAddr(const op_t &x, ea_t ea, ea_t off, bool isSigned)
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{
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// try and find the real name expression
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if ( !out_name_expr(x, ea, off) )
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{
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// work out flags correctly
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uint32 flags = OOF_ADDR | OOFW_16;
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if ( isSigned )
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flags |= OOF_SIGNED;
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else
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flags |= OOFS_NOSIGN;
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// if name wasn't found, just output the value & add to noname queue
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out_value(x, flags);
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remember_problem(PR_NONAME, insn.ea);
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}
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}
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//----------------------------------------------------------------------
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// generate the text representation of an operand
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bool out_sam8_t::out_operand(const op_t &x)
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{
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// output operands
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switch ( x.type )
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{
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case o_reg:
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OutRegString(x.fl_workingReg != 0, x.fl_regPair != 0, x.reg);
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break;
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case o_reg_bit:
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OutRegString(x.fl_workingReg != 0, x.fl_regPair != 0, x.reg, (int)x.v_bit);
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break;
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case o_imm:
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out_symbol('#');
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out_value(x, OOFS_IFSIGN | OOFW_IMM);
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break;
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case o_cmem_ind:
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// this needs special treatment... has to have a # in front of it
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out_symbol('#');
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OutAddr(x, x.addr, x.addr);
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break;
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case o_near:
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case o_cmem:
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OutAddr(x, x.addr, x.addr);
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break;
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case o_emem:
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OutAddr(x, SAM8_EDATASEG_START + x.addr, x.addr);
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break;
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case o_phrase:
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switch ( x.phrase )
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{
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case fIndReg:
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out_symbol('@');
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OutRegString(x.fl_workingReg != 0, x.fl_regPair != 0, x.v_phrase_reg);
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break;
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case fIdxReg:
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out_symbol('#');
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OutRegString(false, false, x.v_phrase_reg);
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out_symbol('[');
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OutRegString(true, false, x.v_phrase_idxreg);
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out_symbol(']');
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break;
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}
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break;
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case o_displ:
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switch ( x.phrase )
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{
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case fIdxCAddr:
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out_symbol('#');
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OutAddr(x, x.addr, x.addr, (x.addr > 0xffff));
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out_symbol('[');
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OutRegString(true, true, x.v_phrase_idxreg);
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out_symbol(']');
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break;
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case fIdxEAddr:
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out_symbol('#');
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OutAddr(x, SAM8_EDATASEG_START + x.addr, x.addr, (x.addr > 0xffff));
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out_symbol('[');
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OutRegString(true, true, x.v_phrase_idxreg);
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out_symbol(']');
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break;
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}
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break;
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}
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// OK
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return 1;
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}
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//----------------------------------------------------------------------
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// generate a text representation of an instruction
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void out_sam8_t::out_insn(void)
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{
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// output instruction mnemonics
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out_mnemonic();
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// check for JP/JR instruction with condition code
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// add the condition on as a pseudo operand if present
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if ( insn.itype == SAM8_JR
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|| insn.itype == SAM8_JP && insn.c_condition != ccNone )
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{
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// sanity check
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if ( insn.c_condition >= cc_last )
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{
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warning("%a (%s): Internal error: bad condition code %i",
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insn.ea, insn.get_canon_mnem(ph), insn.c_condition);
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return;
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}
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// output the condition code normally
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out_keyword(ccNames[insn.c_condition]);
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out_symbol(',');
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out_char(' ');
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}
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// output the first operand
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if ( insn.Op1.type != o_void )
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out_one_operand(0);
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// output the second operand
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if ( insn.Op2.type != o_void )
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{
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out_symbol(',');
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out_char(' ');
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out_one_operand(1);
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}
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// output the third operand
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if ( insn.Op3.type != o_void )
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{
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out_symbol(',');
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out_char(' ');
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out_one_operand(2);
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}
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flush_outbuf();
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}
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//--------------------------------------------------------------------------
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// generate start of the disassembly
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void idaapi sam8_header(outctx_t &ctx)
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{
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ctx.gen_header(GH_PRINT_ALL_BUT_BYTESEX);
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}
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// --------------------------------------------------------------------------
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// generate start of segment
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//lint -esym(1764, ctx) could be made const
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//lint -esym(818, Sarea) could be made const
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void sam8_t::sam8_segstart(outctx_t &ctx, segment_t *Sarea) const
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{
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// generate ORG directive if necessary
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if ( (inf_get_outflags() & OFLG_GEN_ORG) != 0 )
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{
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// get segment data
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size_t org = size_t(ctx.insn_ea - get_segm_base(Sarea));
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// generate line
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if ( org != 0 )
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{
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char buf[MAX_NUMBUF];
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btoa(buf, sizeof(buf), org);
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ctx.gen_printf(DEFAULT_INDENT, COLSTR("%s %s", SCOLOR_ASMDIR), ash.origin, buf);
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}
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}
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}
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// --------------------------------------------------------------------------
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// generate end of the disassembly
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void sam8_t::sam8_footer(outctx_t &ctx) const
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{
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// if assembler supplies end statement, output it
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if ( ash.end != NULL )
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{
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ctx.gen_empty_line();
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ctx.out_line(ash.end, COLOR_ASMDIR);
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ctx.flush_outbuf(DEFAULT_INDENT);
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}
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}
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// --------------------------------------------------------------------------
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// customised address output
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void idaapi sam8_out_data(outctx_t &ctx, bool analyze_only)
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{
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ea_t ea = ctx.insn_ea;
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// if addres is valid, use normal output function
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if ( is_loaded(ea) )
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ctx.out_data(analyze_only);
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else
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ctx.flush_buf(COLSTR("; db ?", SCOLOR_SYMBOL));
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}
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