645 lines
15 KiB
INI
645 lines
15 KiB
INI
;
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; This file defines SFR names and bit names for Microchip's PIC 16 bit processors.
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;
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; This file can be configured for different devices.
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; At the beginning of the file there are definitions common for all devices
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; Device-specific definitions are introduced by
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;
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; .devicename
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;
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; line. Also an optional directive
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;
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; .default devicename
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;
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; designates the default device name.
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;
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.default 18F2520
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; common FSR definitions
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TOSU 0xFFF
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TOSH 0xFFE
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TOSL 0xFFD
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STKPTR 0xFFC
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STKPTR.STKFUL 7
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STKPTR.STKUNF 6
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STKPTR.SP4 4
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STKPTR.SP3 3
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STKPTR.SP2 2
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STKPTR.SP1 1
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STKPTR.SP0 0
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PCLATU 0xFFB
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PCLATH 0xFFA
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PCL 0xFF9
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TBLPTRU 0xFF8
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TBLPTRH 0xFF7
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TBLPTRL 0xFF6
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TABLAT 0xFF5
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PRODH 0xFF4
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PRODL 0xFF3
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INTCON 0xFF2
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INTCON.GIE_GIEH 7
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INTCON.PEIE_GIEL 6
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INTCON.TMR0IE 5
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INTCON.INT0IE 4
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INTCON.RBIE 3
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INTCON.TMR0IF 2
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INTCON.INT0IF 1
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INTCON.RBIF 0
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INTCON2 0xFF1
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INTCON2.RBPU 7
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INTCON2.INTEDG0 6
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INTCON2.INTEDG1 5
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INTCON2.INTEDG2 4
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INTCON2.TMR0IP 2
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INTCON2.RBIP 0
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INTCON3 0xFF0
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INTCON3.INT2IP 7
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INTCON3.INT1IP 6
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INTCON3.INT2IE 4
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INTCON3.INT1IE 3
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INTCON3.INT2IF 1
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INTCON3.INT1IF 0
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INDF0 0xFEF
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POSTINC0 0xFEE
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POSTDEC0 0xFED
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PREINC0 0xFEC
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PLUSW0 0xFEB
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FSR0H 0xFEA
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FSR0L 0xFE9
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WREG 0xFE8
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INDF1 0xFE7
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POSTINC1 0xFE6
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POSTDEC1 0xFE5
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PREINC1 0xFE4
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PLUSW1 0xFE3
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FSR1H 0xFE2
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FSR1L 0xFE1
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BSR 0xFE0
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INDF2 0xFDF
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POSTINC2 0xFDE
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POSTDEC2 0xFDD
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PREINC2 0xFDC
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PLUSW2 0xFDB
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FSR2H 0xFDA
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FSR2L 0xFD9
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STATUS 0xFD8
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STATUS.N 4
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STATUS.OV 3
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STATUS.Z 2
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STATUS.DC 1
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STATUS.C 0
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TMR0H 0xFD7
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TMR0L 0xFD6
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T0CON 0xFD5
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T0CON.TMR0ON 7
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T0CON.T08BIT 6
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T0CON.T0CS 5
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T0CON.T0SE 4
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T0CON.PSA 3
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T0CON.T0PS2 2
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T0CON.T0PS1 1
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T0CON.T0PS0 0
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OSCCON 0xFD3
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OSCCON.IDLEN 7
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OSCCON.IRCF2 6
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OSCCON.IRCF1 5
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OSCCON.IRCF0 4
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OSCCON.OSTS 3
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OSCCON.IOFS 2
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OSCCON.SCS1 1
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OSCCON.SCS0 0
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HLVDCON 0xFD2
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HLVDCON.VDIRMAG 7
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HLVDCON.IRVST 5
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HLVDCON.HLVDEN 4
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HLVDCON.HLVDL3 3
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HLVDCON.HLVDL2 2
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HLVDCON.HLVDL1 1
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HLVDCON.HLVDL0 0
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WDTCON 0xFD1
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WDTCON.SWDTEN 0
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RCON 0xFD0
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RCON.IPEN 7
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RCON.SBOREN 6
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RCON.RI 4
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RCON.TO 3
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RCON.PD 2
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RCON.POR 1
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RCON.BOR 0
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TMR1H 0xFCF
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TMR1L 0xFCE
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T1CON 0xFCD
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T1CON.RD16 7
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T1CON.T1RUN 6
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T1CON.T1CKPS1 5
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T1CON.T1CKPS0 4
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T1CON.T1OSCEN 3
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T1CON.T1SYNC 2
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T1CON.TMR1CS 1
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T1CON.TMR1ON 0
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TMR2 0xFCC
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PR2 0xFCB
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T2CON 0xFCA
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T2CON.T2OUTPS3 6
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T2CON.T2OUTPS2 5
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T2CON.T2OUTPS1 4
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T2CON.T2OUTPS0 3
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T2CON.TMR2ON 2
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T2CON.T2CKPS1 1
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T2CON.T2CKPS0 0
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SSPBUF 0xFC9
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SSPADD 0xFC8
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SSPSTAT 0xFC7
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SSPSTAT.SMP 7
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SSPSTAT.CKE 6
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SSPSTAT.D_A 5
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SSPSTAT.P 4
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SSPSTAT.S 3
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SSPSTAT.R_W 2
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SSPSTAT.UA 1
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SSPSTAT.BF 0
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SSPCON1 0xFC6
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SSPCON1.WCOL 7
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SSPCON1.SSPOV 6
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SSPCON1.SSPEN 5
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SSPCON1.CKP 4
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SSPCON1.SSPM3 3
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SSPCON1.SSPM2 2
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SSPCON1.SSPM1 1
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SSPCON1.SSPM0 0
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SSPCON2 0xFC5
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SSPCON2.GCEN 7
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SSPCON2.ACKSTAT 6
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SSPCON2.ACKDT 5
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SSPCON2.ACKEN 4
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SSPCON2.RCEN 3
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SSPCON2.PEN 2
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SSPCON2.RSEN 1
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SSPCON2.SEN 0
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ADRESH 0xFC4
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ADRESL 0xFC3
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ADCON0 0xFC2
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ADCON0.CHS3 5
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ADCON0.CHS2 4
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ADCON0.CHS1 3
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ADCON0.CHS0 2
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ADCON0.GO_DONE 1
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ADCON0.ADON 0
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ADCON1 0xFC1
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ADCON1.VCFG1 5
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ADCON1.VCFG0 4
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ADCON1.PCFG3 3
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ADCON1.PCFG2 2
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ADCON1.PCFG1 1
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ADCON1.PCFG0 0
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ADCON2 0xFC0
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ADCON2.ADFM 7
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ADCON2.ACQT2 5
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ADCON2.ACQT1 4
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ADCON2.ACQT0 3
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ADCON2.ADCS2 2
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ADCON2.ADCS1 1
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ADCON2.ADCS0 0
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CCPR1H 0xFBF
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CCPR1L 0xFBE
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CCP1CON 0xFBD
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CCP1CON.P1M1 7
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CCP1CON.P1M0 6
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CCP1CON.DC1B1 5
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CCP1CON.DC1B0 4
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CCP1CON.CCP1M3 3
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CCP1CON.CCP1M2 2
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CCP1CON.CCP1M1 1
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CCP1CON.CCP1M0 0
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CCPR2H 0xFBC
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CCPR2L 0xFBB
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CCP2CON 0xFBA
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CCP2CON.DC2B1 5
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CCP2CON.DC2B0 4
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CCP2CON.CCP2M3 3
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CCP2CON.CCP2M2 2
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CCP2CON.CCP2M1 1
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CCP2CON.CCP2M0 0
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BAUDCON 0xFB8
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BAUDCON.ABDOVF 7
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BAUDCON.RCIDL 6
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BAUDCON.SCKP 4
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BAUDCON.BRG16 3
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BAUDCON.WUE 1
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BAUDCON.ABDEN 0
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PWM1CON 0xFB7
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PWM1CON.PRSEN 7
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PWM1CON.PDC6 6
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PWM1CON.PDC5 5
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PWM1CON.PDC4 4
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PWM1CON.PDC3 3
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PWM1CON.PDC2 2
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PWM1CON.PDC1 1
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PWM1CON.PDC0 0
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ECCP1AS 0xFB6
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ECCP1AS.ECCPASE 7
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ECCP1AS.ECCPAS2 6
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ECCP1AS.ECCPAS1 5
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ECCP1AS.ECCPAS0 4
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ECCP1AS.PSSAC1 3
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ECCP1AS.PSSAC0 2
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ECCP1AS.PSSBD1 1
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ECCP1AS.PSSBD0 0
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CVRCON 0xFB5
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CVRCON.CVREN 7
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CVRCON.CVROE 6
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CVRCON.CVRR 5
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CVRCON.CVRSS 4
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CVRCON.CVR3 3
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CVRCON.CVR2 2
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CVRCON.CVR1 1
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CVRCON.CVR0 0
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CMCON 0xFB4
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CMCON.C2OUT 7
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CMCON.C1OUT 6
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CMCON.C2INV 5
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CMCON.C1INV 4
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CMCON.CIS 3
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CMCON.CM2 2
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CMCON.CM1 1
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CMCON.CM0 0
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TMR3H 0xFB3
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TMR3L 0xFB2
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T3CON 0xFB1
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T3CON.RD16 7
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T3CON.T3CCP2 6
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T3CON.T3CKPS1 5
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T3CON.T3CKPS0 4
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T3CON.T3CCP1 3
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T3CON.T3SYNC 2
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T3CON.TMR3CS 1
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T3CON.TMR3ON 0
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SPBRGH 0xFB0
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SPBRG 0xFAF
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RCREG 0xFAE
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TXREG 0xFAD
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TXSTA 0xFAC
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TXSTA.CSRC 7
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TXSTA.TX9 6
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TXSTA.TXEN 5
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TXSTA.SYNC 4
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TXSTA.SENDB 3
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TXSTA.BRGH 2
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TXSTA.TRMT 1
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TXSTA.TX9D 0
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RCSTA 0xFAB
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RCSTA.SPEN 7
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RCSTA.RX9 6
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RCSTA.SREN 5
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RCSTA.CREN 4
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RCSTA.ADDEN 3
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RCSTA.FERR 2
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RCSTA.OERR 1
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RCSTA.RX9D 0
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EEADRH 0xFAA
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EEADR 0xFA9
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EEDATA 0xFA8
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EECON2 0xFA7
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EECON1 0xFA6
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EECON1.EEPGD 7
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EECON1.CFGS 6
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EECON1.FREE 4
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EECON1.WRERR 3
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EECON1.WREN 2
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EECON1.WR 1
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EECON1.RD 0
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IPR3 0xFA5
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PIR3 0xFA4
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PIE3 0xFA3
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IPR2 0xFA2
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IPR2.OSCFIP 7
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IPR2.CMIP 6
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IPR2.EEIP 4
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IPR2.BCLIP 3
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IPR2.HLVDIP 2
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IPR2.TMR3IP 1
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IPR2.CCP2IP 0
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PIR2 0xFA1
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PIR2.OSCFIF 7
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PIR2.CMIF 6
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PIR2.EEIF 4
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PIR2.BCLIF 3
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PIR2.HLVDIF 2
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PIR2.TMR3IF 1
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PIR2.CCP2IF 0
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PIE2 0xFA0
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PIE2.OSCFIE 7
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PIE2.CMIE 6
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PIE2.EEIE 4
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PIE2.BCLIE 3
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PIE2.HLVDIE 2
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PIE2.TMR3IE 1
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PIE2.CCP2IE 0
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IPR1 0xF9F
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IPR1.PSPIP 7
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IPR1.ADIP 6
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IPR1.RCIP 5
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IPR1.TXIP 4
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IPR1.SSPIP 3
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IPR1.CCP1IP 2
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IPR1.TMR2IP 1
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IPR1.TMR1IP 0
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PIR1 0xF9E
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PIR1.PSPIF 7
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PIR1.ADIF 6
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PIR1.RCIF 5
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PIR1.TXIF 4
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PIR1.SSPIF 3
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PIR1.CCP1IF 2
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PIR1.TMR2IF 1
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PIR1.TMR1IF 0
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PIE1 0xF9D
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PIE1.PSPIE 7
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PIE1.ADIE 6
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PIE1.RCIE 5
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PIE1.TXIE 4
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PIE1.SSPIE 3
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PIE1.CCP1IE 2
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PIE1.TMR2IE 1
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PIE1.TMR1IE 0
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MEMCON 0xF9C
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OSCTUNE 0xF9B
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OSCTUNE.INTSRC 7
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OSCTUNE.PLLEN 6
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OSCTUNE.TUN4 4
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OSCTUNE.TUN3 3
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OSCTUNE.TUN2 2
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OSCTUNE.TUN1 1
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OSCTUNE.TUN0 0
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TRISJ 0xF9A
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TRISH 0xF99
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TRISG 0xF98
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TRISF 0xF97
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TRISE 0xF96
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TRISE.IBF 7
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TRISE.OBF 6
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TRISE.IBOV 5
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TRISE.PSPMODE 4
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TRISE.TRISE2 2
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TRISE.TRISE1 1
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TRISE.TRISE0 0
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TRISD 0xF95
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TRISC 0xF94
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TRISB 0xF93
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TRISA 0xF92
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LATJ 0xF91
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LATH 0xF90
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LATG 0xF8F
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LATF 0xF8E
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LATE 0xF8D
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LATD 0xF8C
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LATC 0xF8B
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LATB 0xF8A
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LATA 0xF89
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PORTJ 0xF88
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PORTH 0xF87
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PORTG 0xF86
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PORTF 0xF85
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PORTE 0xF84
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PORTE.RE3 3
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PORTE.RE2 2
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PORTE.RE1 1
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PORTE.RE0 0
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PORTD 0xF83
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PORTD.RD7 7
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PORTD.RD6 6
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PORTD.RD5 5
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PORTD.RD4 4
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PORTD.RD3 3
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PORTD.RD2 2
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PORTD.RD1 1
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PORTD.RD0 0
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PORTC 0xF82
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PORTC.RC7 7
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PORTC.RC6 6
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PORTC.RC5 5
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PORTC.RC4 4
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PORTC.RC3 3
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PORTC.RC2 2
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PORTC.RC1 1
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PORTC.RC0 0
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PORTB 0xF81
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PORTB.RB7 7
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PORTB.RB6 6
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PORTB.RB5 5
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PORTB.RB4 4
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PORTB.RB3 3
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PORTB.RB2 2
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PORTB.RB1 1
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PORTB.RB0 0
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PORTA 0xF80
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PORTA.RA7 7
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PORTA.RA6 6
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PORTA.RA5 5
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PORTA.RA4 4
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PORTA.RA3 3
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PORTA.RA2 2
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PORTA.RA1 1
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PORTA.RA0 0
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; Interrupt and reset vector assignments
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entry RESET 0x0000 RESET
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entry HI_ISR 0x0008 High-Priority Interrupt
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entry LO_ISR 0x0018 Low-Priority Interrupt
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; http://ww1.microchip.com/downloads/en/DeviceDoc/39631a.pdf
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; PIC18F2420/2520/4420/4520
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.18F2520
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; MEMORY MAP
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area CODE ROM 0x0000:0x8000 On-chip Program Memory
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area DATA RAM 0x0000:0x0600 SRAM Data Memory
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area DATA FSR_ 0x0F80:0x1000 Function Special Registers
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; http://ww1.microchip.com/downloads/en/DeviceDoc/39626e.pdf
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; PIC18F2525/2620/4525/4620
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.18F2525
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; MEMORY MAP
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area CODE ROM 0x0000:0x6000 On-chip Program Memory
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area DATA RAM 0x0000:0x0F80 SRAM Data Memory
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area DATA FSR_ 0x0F80:0x1000 Function Special Registers
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.18F4525
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; MEMORY MAP
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area CODE ROM 0x0000:0x6000 On-chip Program Memory
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area DATA RAM 0x0000:0x0F80 SRAM Data Memory
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area DATA FSR_ 0x0F80:0x1000 Function Special Registers
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.18F2620
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; MEMORY MAP
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area CODE ROM 0x0000:0x8000 On-chip Program Memory
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area DATA RAM 0x0000:0x0F80 SRAM Data Memory
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area DATA FSR_ 0x0F80:0x1000 Function Special Registers
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.18F4620
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; MEMORY MAP
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area CODE ROM 0x0000:0x8000 On-chip Program Memory
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area DATA RAM 0x0000:0x0F80 SRAM Data Memory
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area DATA FSR_ 0x0F80:0x1000 Function Special Registers
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.18F2455
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; MEMORY MAP
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area CODE ROM 0x0000:0x6000 On-chip Program Memory
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area DATA RAM 0x0000:0x0800 SRAM Data Memory
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area DATA FSR_ 0x0F80:0x1000 Function Special Registers
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.18F2550
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; MEMORY MAP
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area CODE ROM 0x0000:0x8000 On-chip Program Memory
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area DATA RAM 0x0000:0x0800 SRAM Data Memory
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area DATA FSR_ 0x0F80:0x1000 Function Special Registers
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.18F4455
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; MEMORY MAP
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area CODE ROM 0x0000:0x6000 On-chip Program Memory
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area DATA RAM 0x0000:0x0800 SRAM Data Memory
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area DATA FSR_ 0x0F80:0x1000 Function Special Registers
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.18F4550
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; MEMORY MAP
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area CODE ROM 0x0000:0x8000 On-chip Program Memory
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area DATA RAM 0x0000:0x0800 SRAM Data Memory
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area DATA FSR_ 0x0F80:0x1000 Function Special Registers
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; http://ww1.microchip.com/downloads/en/DeviceDoc/39761c.pdf
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; PIC18F2682/2685/4682/4685
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.18F2682
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; MEMORY MAP
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area CODE ROM 0x0000:0x14000 On-chip Program Memory
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area DATA RAM 0x0000:0x0D00 SRAM Data Memory
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area DATA FSR_ 0x0D00:0x1000 Function Special Registers
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.18F2685
|
|
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; MEMORY MAP
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area CODE ROM 0x0000:0x18000 On-chip Program Memory
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area DATA RAM 0x0000:0x0D00 SRAM Data Memory
|
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area DATA FSR_ 0x0D00:0x1000 Function Special Registers
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.18F4682
|
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|
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; MEMORY MAP
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area CODE ROM 0x0000:0x14000 On-chip Program Memory
|
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area DATA RAM 0x0000:0x0D00 SRAM Data Memory
|
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area DATA FSR_ 0x0D00:0x1000 Function Special Registers
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|
|
.18F4685
|
|
|
|
; MEMORY MAP
|
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area CODE ROM 0x0000:0x18000 On-chip Program Memory
|
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area DATA RAM 0x0000:0x0D00 SRAM Data Memory
|
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area DATA FSR_ 0x0D00:0x1000 Function Special Registers
|
|
|
|
; http://ww1.microchip.com/downloads/en/DeviceDoc/39646c.pdf
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; PIC18F6527/18F6622/18F6627/18F6722/18F8527/18F8622/18F8627/18F8722
|
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|
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.18F6722
|
|
|
|
; MEMORY MAP
|
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area CODE ROM 0x0000:0x200000 On-chip Program Memory
|
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area DATA RAM 0x0000:0x0F60 SRAM Data Memory
|
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area DATA FSR_ 0x0F60:0x1000 Function Special Registers
|
|
|
|
.18F8722
|
|
|
|
; MEMORY MAP
|
|
area CODE ROM 0x0000:0x200000 On-chip Program Memory
|
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area DATA RAM 0x0000:0x0F60 SRAM Data Memory
|
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area DATA FSR_ 0x0F60:0x1000 Function Special Registers
|
|
|
|
.18F6627
|
|
|
|
; MEMORY MAP
|
|
area CODE ROM 0x0000:0x180000 On-chip Program Memory
|
|
area DATA RAM 0x0000:0x0F60 SRAM Data Memory
|
|
area DATA FSR_ 0x0F60:0x1000 Function Special Registers
|
|
|
|
.18F8627
|
|
|
|
; MEMORY MAP
|
|
area CODE ROM 0x0000:0x180000 On-chip Program Memory
|
|
area DATA RAM 0x0000:0x0F60 SRAM Data Memory
|
|
area DATA FSR_ 0x0F60:0x1000 Function Special Registers
|
|
|
|
.18F6622
|
|
|
|
; MEMORY MAP
|
|
area CODE ROM 0x0000:0x10000 On-chip Program Memory
|
|
area DATA RAM 0x0000:0x0F60 SRAM Data Memory
|
|
area DATA FSR_ 0x0F60:0x1000 Function Special Registers
|
|
|
|
.18F8622
|
|
|
|
; MEMORY MAP
|
|
area CODE ROM 0x0000:0x10000 On-chip Program Memory
|
|
area DATA RAM 0x0000:0x0F60 SRAM Data Memory
|
|
area DATA FSR_ 0x0F60:0x1000 Function Special Registers
|
|
|
|
.18F6527
|
|
|
|
; MEMORY MAP
|
|
area CODE ROM 0x0000:0xC000 On-chip Program Memory
|
|
area DATA RAM 0x0000:0x0F60 SRAM Data Memory
|
|
area DATA FSR_ 0x0F60:0x1000 Function Special Registers
|
|
|
|
.18F8527
|
|
|
|
; MEMORY MAP
|
|
area CODE ROM 0x0000:0xC000 On-chip Program Memory
|
|
area DATA RAM 0x0000:0x0F60 SRAM Data Memory
|
|
area DATA FSR_ 0x0F60:0x1000 Function Special Registers
|
|
|
|
; http://ww1.microchip.com/downloads/en/DeviceDoc/30491c.pdf
|
|
; PIC18F6585/8585/6680/8680
|
|
|
|
.18F6585
|
|
|
|
; MEMORY MAP
|
|
area CODE ROM 0x0000:0xC000 On-chip Program Memory
|
|
area DATA RAM 0x0000:0x0D00 SRAM Data Memory
|
|
area DATA CANFSR 0x0D00:0x0F60 Function Special Registers
|
|
area DATA FSR_ 0x0F60:0x1000 Function Special Registers
|
|
|
|
.18F8585
|
|
|
|
; MEMORY MAP
|
|
area CODE ROM 0x0000:0xC000 On-chip Program Memory
|
|
area DATA RAM 0x0000:0x0D00 SRAM Data Memory
|
|
area DATA CANFSR 0x0D00:0x0F60 Function Special Registers
|
|
area DATA FSR_ 0x0F60:0x1000 Function Special Registers
|
|
|
|
.18F6680
|
|
|
|
; MEMORY MAP
|
|
area CODE ROM 0x0000:0x10000 On-chip Program Memory
|
|
area DATA RAM 0x0000:0x0D00 SRAM Data Memory
|
|
area DATA CANFSR 0x0D00:0x0F60 Function Special Registers
|
|
area DATA FSR_ 0x0F60:0x1000 Function Special Registers
|
|
|
|
.18F8680
|
|
|
|
; MEMORY MAP
|
|
area CODE ROM 0x0000:0x10000 On-chip Program Memory
|
|
area DATA RAM 0x0000:0x0D00 SRAM Data Memory
|
|
area DATA CANFSR 0x0D00:0x0F60 Function Special Registers
|
|
area DATA FSR_ 0x0F60:0x1000 Function Special Registers
|