17814 lines
768 KiB
INI
17814 lines
768 KiB
INI
;
|
||
; New directives:
|
||
;
|
||
; RAM=xxxx ;Maximum # bytes of RAM for this part
|
||
; ROM=xxxx ;# 8-bit bytes of ROM for this part
|
||
; EEPROM=xxxx ;# 8-bit bytes of EEPROM for this part
|
||
;
|
||
; Please note that the ROM size must be declared as the double of the addressable
|
||
; size because it is in bytes
|
||
;
|
||
; Information in this file came from the August, 1999 Atmel AVR databook
|
||
; Information was updated based on GCC/binutils information in Jan 2021
|
||
;
|
||
|
||
;
|
||
; this file defines the i/o port definitions for amtel's avr processors.
|
||
; the i/o port definitions are provided for each avr device
|
||
; each device definition begins with a line like this:
|
||
;
|
||
; .devicename
|
||
;
|
||
; after it go the port definitions in this format:
|
||
;
|
||
; portname address
|
||
;
|
||
; lines beginning with a space are ignored.
|
||
; comment lines should be started with ';' character.
|
||
;
|
||
; the default device is specified at the start of the file
|
||
;
|
||
; SUBARCH corresponds to the __AVR_ARCH__ value used in GCC toolchain
|
||
;
|
||
; Last update 2021-01-27:
|
||
; gcc - https://gcc.gnu.org/git/?p=gcc.git;a=blob;f=gcc/config/avr/avr-devices.c;hb=HEAD
|
||
; gcc-doc - https://gcc.gnu.org/onlinedocs/gcc/AVR-Options.html
|
||
; binutils - https://sourceware.org/git/?p=binutils-gdb.git;a=blob;f=gas/config/tc-avr.c;hb=HEAD)
|
||
;
|
||
; The following values are defined (Check latest GCC/binutils if your chip is missing):
|
||
;
|
||
; 1: avr1 - classic AVR core without data RAM
|
||
; MCU types: attiny11, attiny12, attiny15, attiny28, at90s1200
|
||
;
|
||
; 2: avr2 - classic AVR core with up to 8K program memory
|
||
; MCU types: attiny22, attiny26, at90s2313, at90s2323, at90s2333, at90s2343,
|
||
; at90s4414, at90s4433, at90s4434, at90c8534, at90s8515, at90s8535
|
||
;
|
||
; 25: avr25 - classic AVR core with up to 8K program memory plus the MOVW instruction
|
||
; MCU types: attiny13, attiny13a, attiny24, attiny24a, attiny25, attiny261, attiny261a,
|
||
; attiny2313, attiny2313a, attiny43u, attiny44, attiny44a, attiny45, attiny48,
|
||
; attiny441, attiny461, attiny461a, attiny4313, attiny84, attiny84a, attiny85,
|
||
; attiny87, attiny88, attiny828, attiny841, attiny861, attiny861a, ata5272,
|
||
; ata6616c, at86rf401
|
||
;
|
||
; 3: avr3 - classic AVR core with up to 64K program memory
|
||
; MCU types: at76c711, at43usb355
|
||
;
|
||
; 31: avr31 - classic AVR core with up to 128K program memory
|
||
; MCU types: atmega103, at43usb320
|
||
;
|
||
; 35: avr35 - classic AVR core with up to 64K program memory plus MOVW, CALL, and JMP instructions
|
||
; MCU types: attiny167, attiny1634, atmega8u2, atmega16u2, atmega32u2, ata5505, ata6617c,
|
||
; ata664251, at90usb82, at90usb162
|
||
;
|
||
; 4: avr4 - enhanced AVR core with up to 8K program memory
|
||
; MCU types: atmega48, atmega48a, atmega48p, atmega48pa, atmega48pb, atmega8, atmega8a,
|
||
; atmega8hva, atmega88, atmega88a, atmega88p, atmega88pa, atmega88pb, atmega8515,
|
||
; atmega8535, ata6285, ata6286, ata6289, ata6612c, at90pwm1, at90pwm2, at90pwm2b,
|
||
; at90pwm3, at90pwm3b, at90pwm81
|
||
;
|
||
; 5: avr5 - enhanced AVR core with up to 64K program memory
|
||
; MCU types: atmega16, atmega16a, atmega16hva, atmega16hva2, atmega16hvb, atmega16hvbrevb,
|
||
; atmega16m1, atmega16u4, atmega161, atmega162, atmega163, atmega164a, atmega164p,
|
||
; atmega164pa, atmega165, atmega165a, atmega165p, atmega165pa, atmega168, atmega168a,
|
||
; atmega168p, atmega168pa, atmega168pb, atmega169, atmega169a, atmega169p, atmega169pa,
|
||
; atmega32, atmega32a, atmega32c1, atmega32hvb, atmega32hvbrevb, atmega32m1, atmega32u4,
|
||
; atmega32u6, atmega323, atmega324a, atmega324p, atmega324pa, atmega325, atmega325a,
|
||
; atmega325p, atmega325pa, atmega328, atmega328p, atmega328pb, atmega329, atmega329a,
|
||
; atmega329p, atmega329pa, atmega3250, atmega3250a, atmega3250p, atmega3250pa, atmega3290,
|
||
; atmega3290a, atmega3290p, atmega3290pa, atmega406, atmega64, atmega64a, atmega64c1,
|
||
; atmega64hve, atmega64hve2, atmega64m1, atmega64rfr2, atmega640, atmega644, atmega644a,
|
||
; atmega644p, atmega644pa, atmega644rfr2, atmega645, atmega645a, atmega645p, atmega649,
|
||
; atmega649a, atmega649p, atmega6450, atmega6450a, atmega6450p, atmega6490, atmega6490a,
|
||
; atmega6490p, ata5795, ata5790, ata5790n, ata5791, ata6613c, ata6614q, ata5782, ata5831,
|
||
; ata8210, ata8510, ata5702m322, at90pwm161, at90pwm216, at90pwm316, at90can32, at90can64,
|
||
; at90scr100, at90usb646, at90usb647, at94k, m3000
|
||
;
|
||
; 51: avr51 - enhanced AVR core with up to 128K program memory
|
||
; MCU types: atmega128, atmega128a, atmega128rfa1, atmega128rfr2, atmega1280, atmega1281,
|
||
; atmega1284, atmega1284p, atmega1284rfr2, at90can128, at90usb1286, at90usb1287
|
||
;
|
||
; 6: avr6 - enhanced AVR core with up to 256K program memory and a 3-byte PC
|
||
; MCU types: atmega256rfr2, atmega2560, atmega2561, atmega2564rfr2
|
||
;
|
||
; 100: avrtiny - Tiny core with 512B up to 4K of program memory and 16 gp registers
|
||
; MCU types: attiny4, attiny5, attiny9, attiny10, attiny20, attiny40
|
||
; 101: avrxmega1 - XMega core with up to 8K program memory
|
||
; MCU types: currently none(?)
|
||
; 102: avrxmega2 - XMega core with 8K to 64K program memory and less than 64K RAM
|
||
; MCU types: atxmega8e5, atxmega16a4, atxmega16a4u, atxmega16c4, atxmega16d4, atxmega16e5,
|
||
; atxmega32a4, atxmega32a4u, atxmega32c3, atxmega32c4, atxmega32d3, atxmega32d4,
|
||
; atxmega32e5
|
||
;
|
||
; 103: avrxmega3 - XMega core with 8K to 64K program memory and more than 64K RAM
|
||
; MCU types: attiny202, attiny204, attiny212, attiny214, attiny402, attiny404, attiny406,
|
||
; attiny412, attiny414, attiny416, attiny417, attiny804, attiny806, attiny807,
|
||
; attiny814, attiny816, attiny817, attiny1604, attiny1606, attiny1607, attiny1614,
|
||
; attiny1616, attiny1617, attiny3214, attiny3216, attiny3217, atmega808, atmega809,
|
||
; atmega1608, atmega1609, atmega3208, atmega3209, atmega4808, atmega4809
|
||
;
|
||
; 104: avrxmega4 - XMega core with 64K to 128K program memory and less than 64K RAM
|
||
; MCU types: atxmega64a3, atxmega64a3u, atxmega64a4u, atxmega64b1, atxmega64b3, atxmega64c3,
|
||
; atxmega64d3, atxmega64d4
|
||
;
|
||
; 105: avrxmega5 - XMega core with 64K to 128K program memory and more than 64K RAM
|
||
; MCU types: atxmega64a1, atxmega64a1u
|
||
;
|
||
; 106: avrxmega6 - XMega core with 128K to 256K program memory and less than 64K RAM
|
||
; MCU types: atxmega128a3, atxmega128a3u, atxmega128b1, atxmega128b3, atxmega128c3, atxmega128d3,
|
||
; atxmega128d4, atxmega192a3, atxmega192a3u, atxmega192c3, atxmega192d3, atxmega256a3,
|
||
; atxmega256a3b, atxmega256a3bu, atxmega256a3u, atxmega256c3, atxmega256d3, atxmega384c3,
|
||
; atxmega384d3
|
||
;
|
||
; 107: avrxmega7 - XMega core with 128K to 256K program memory and more than 64K RAM
|
||
; MCU types: atxmega128a1, atxmega128a1u, atxmega128a4u
|
||
|
||
.default AT90S8515
|
||
|
||
.AT90C8534
|
||
SUBARCH=2
|
||
; doc1229.pdf
|
||
;
|
||
|
||
RAM=256
|
||
ROM=8192
|
||
EEPROM=512
|
||
|
||
|
||
; MEMORY MAP
|
||
area DATA GPWR_ 0x0000:0x0020 General Purpose Working Registers
|
||
area DATA FSR_ 0x0020:0x0060 I/O registers
|
||
area DATA I_SRAM 0x0060:0x0160 Internal SRAM
|
||
|
||
|
||
; Interrupt and reset vector assignments
|
||
entry __RESET 0x0000 Hardware Pin
|
||
entry INT0_ 0x0001 External Interrupt Request 0
|
||
entry INT1_ 0x0002 External Interrupt Request 1
|
||
entry TIMER1_OVF 0x0003 Timer/Counter1 Overflow
|
||
entry TIMER0_OVF 0x0004 Timer/Counter0 Overflow
|
||
entry ADC_ 0x0005 ADC Conversion Complete
|
||
entry EE_RDY 0x0006 EEPROM Ready
|
||
|
||
|
||
; INPUT/OUTPUT PORTS
|
||
RESERVED0000 0x0000 RESERVED
|
||
RESERVED0001 0x0001 RESERVED
|
||
RESERVED0002 0x0002 RESERVED
|
||
RESERVED0003 0x0003 RESERVED
|
||
ADCL 0x0004 ADC Data Register Low
|
||
ADCH 0x0005 ADC Data Register High
|
||
ADCSR 0x0006 ADC Control and Status Register
|
||
ADCSR.ADEN 7 ADC Enable
|
||
ADCSR.ADSC 6 ADC Start Conversion
|
||
ADCSR.ADFR 5 ADC Free Run Select
|
||
ADCSR.ADIF 4 ADC Interrupt Flag
|
||
ADCSR.ADIE 3 ADC Interrupt Enable
|
||
ADCSR.ADPS2 2 ADC Prescaler Select Bit 2
|
||
ADCSR.ADPS1 1 ADC Prescaler Select Bit 1
|
||
ADCSR.ADPS0 0 ADC Prescaler Select Bit 0
|
||
ADMUX 0x0007 ADC Multiplexer Select Register
|
||
ADMUX.MUX2 2 Analog Channel Select Bit 2
|
||
ADMUX.MUX1 1 Analog Channel Select Bit 1
|
||
ADMUX.MUX0 0 Analog Channel Select Bit 0
|
||
RESERVED0008 0x0008 RESERVED
|
||
RESERVED0009 0x0009 RESERVED
|
||
RESERVED000A 0x000A RESERVED
|
||
RESERVED000B 0x000B RESERVED
|
||
RESERVED000C 0x000C RESERVED
|
||
RESERVED000D 0x000D RESERVED
|
||
RESERVED000E 0x000E RESERVED
|
||
RESERVED000F 0x000F RESERVED
|
||
GIPR 0x0010 General Interrupt Pin Register
|
||
GIPR.IPIN1 3 External Interrupt Pin 1
|
||
GIPR.IPIN0 2 External Interrupt Pin 0
|
||
RESERVED0011 0x0011 RESERVED
|
||
RESERVED0012 0x0012 RESERVED
|
||
RESERVED0013 0x0013 RESERVED
|
||
RESERVED0014 0x0014 RESERVED
|
||
RESERVED0015 0x0015 RESERVED
|
||
RESERVED0016 0x0016 RESERVED
|
||
RESERVED0017 0x0017 RESERVED
|
||
RESERVED0018 0x0018 RESERVED
|
||
RESERVED0019 0x0019 RESERVED
|
||
DDRA 0x001A Port A Data Direction Register
|
||
DDRA.DDA6 6 Port A Data Direction Register bit 6
|
||
DDRA.DDA5 5 Port A Data Direction Register bit 5
|
||
DDRA.DDA4 4 Port A Data Direction Register bit 4
|
||
DDRA.DDA3 3 Port A Data Direction Register bit 3
|
||
DDRA.DDA2 2 Port A Data Direction Register bit 2
|
||
DDRA.DDA1 1 Port A Data Direction Register bit 1
|
||
DDRA.DDA0 0 Port A Data Direction Register bit 0
|
||
PORTA 0x001B Port A Data Register
|
||
PORTA.PORTA6 6 Port A Data Register bit 6
|
||
PORTA.PORTA5 5 Port A Data Register bit 5
|
||
PORTA.PORTA4 4 Port A Data Register bit 4
|
||
PORTA.PORTA3 3 Port A Data Register bit 3
|
||
PORTA.PORTA2 2 Port A Data Register bit 2
|
||
PORTA.PORTA1 1 Port A Data Register bit 1
|
||
PORTA.PORTA0 0 Port A Data Register bit 0
|
||
EECR 0x001C EEPROM Control Register
|
||
EECR.EERIE 3 EEPROM Ready Interrupt Enable
|
||
EECR.EEMWE 2 EEPROM Master Write Enable
|
||
EECR.EEWE 1 EEPROM Write Enable
|
||
EECR.EERE 0 EEPROM Read Enable
|
||
EEDR 0x001D EEPROM Data Register
|
||
EEARL 0x001E EEPROM Address Register Low
|
||
EEARL.EEAR7 7
|
||
EEARL.EEAR6 6
|
||
EEARL.EEAR5 5
|
||
EEARL.EEAR4 4
|
||
EEARL.EEAR3 3
|
||
EEARL.EEAR2 2
|
||
EEARL.EEAR1 1
|
||
EEARL.EEAR0 0
|
||
EEARH 0x001F EEPROM Address Register High
|
||
RESERVED0020 0x0020 RESERVED
|
||
RESERVED0021 0x0021 RESERVED
|
||
RESERVED0022 0x0022 RESERVED
|
||
RESERVED0023 0x0023 RESERVED
|
||
RESERVED0024 0x0024 RESERVED
|
||
RESERVED0025 0x0025 RESERVED
|
||
RESERVED0026 0x0026 RESERVED
|
||
RESERVED0027 0x0027 RESERVED
|
||
RESERVED0028 0x0028 RESERVED
|
||
RESERVED0029 0x0029 RESERVED
|
||
RESERVED002A 0x002A RESERVED
|
||
RESERVED002B 0x002B RESERVED
|
||
TCNT1L 0x002C Timer/Counter1 Low
|
||
TCNT1H 0x002D Timer/Counter1 High
|
||
TCCR1 0x002E Timer/Counter1 Control Register
|
||
TCCR1.CS12 2 Clock Select1, Bit 2
|
||
TCCR1.CS11 1 Clock Select1, Bit 1
|
||
TCCR1.CS10 0 Clock Select1, Bit 0
|
||
RESERVED002F 0x002F RESERVED
|
||
RESERVED0030 0x0030 RESERVED
|
||
RESERVED0031 0x0031 RESERVED
|
||
TCNT0 0x0032 Timer Counter0
|
||
TCCR0 0x0033 Timer/Counter0 Control Register
|
||
TCCR0.CS02 2 Clock Select0, Bit 2
|
||
TCCR0.CS01 1 Clock Select0, Bit 1
|
||
TCCR0.CS00 0 Clock Select0, Bit 0
|
||
RESERVED0034 0x0034 RESERVED
|
||
MCUCR 0x0035 MCU Control Register
|
||
MCUCR.SE 6 Sleep Enable
|
||
MCUCR.SM 5 Sleep Mode
|
||
MCUCR.ISC1 2 Interrupt Sense Control 1
|
||
MCUCR.ISC0 0 Interrupt Sense Control 0
|
||
RESERVED0036 0x0036 RESERVED
|
||
RESERVED0037 0x0037 RESERVED
|
||
TIFR 0x0038 Timer/Counter Interrupt Flag Register
|
||
TIFR.TOV1 2 Timer/Counter1 Overflow Flag
|
||
TIFR.TOV0 0 Timer/Counter0 Overflow Flag
|
||
TIMSK 0x0039 Timer/Counter Interrupt Mask Register
|
||
TIMSK.TOIE1 2 Timer/Counter1 Overflow Interrupt Enable
|
||
TIMSK.TOIE0 0 Timer/Counter0 Overflow Interrupt Enable
|
||
GIFR 0x003A General Interrupt Flag Register
|
||
GIFR.INTF1 7 External Interrupt Flag 1
|
||
GIFR.INTF0 6 External Interrupt Flag 0
|
||
GIMSK 0x003B General Interrupt Mask Register
|
||
GIMSK.INT1 7 External Interrupt Request 1 Enable
|
||
GIMSK.INT0 6 External Interrupt Request 0 Enable
|
||
RESERVED003C 0x003C RESERVED
|
||
SPL 0x003D Stack Pointer Low
|
||
SPL.SP7 7
|
||
SPL.SP6 6
|
||
SPL.SP5 5
|
||
SPL.SP4 4
|
||
SPL.SP3 3
|
||
SPL.SP2 2
|
||
SPL.SP1 1
|
||
SPL.SP0 0
|
||
SPH 0x003E Stack Pointer Low
|
||
SPH.SP8 8
|
||
SREG 0x003F Status Register
|
||
SREG.I 7 Global Interrupt Enable
|
||
SREG.T 6 Bit Copy Storage
|
||
SREG.H 5 Half-carry Flag
|
||
SREG.S 4 Sign Bit
|
||
SREG.V 3 Two's Complement Overflow Flag
|
||
SREG.N 2 Negative Flag
|
||
SREG.Z 1 Zero Flag
|
||
SREG.C 0 Carry Flag
|
||
|
||
|
||
; RESERVED0020 0x0020 RESERVED
|
||
; RESERVED0021 0x0021 RESERVED
|
||
; RESERVED0022 0x0022 RESERVED
|
||
; RESERVED0023 0x0023 RESERVED
|
||
; ADCL 0x0024 ADC Data Register Low
|
||
; ADCH 0x0025 ADC Data Register High
|
||
; ADCSR 0x0026 ADC Control and Status Register
|
||
; ADCSR.ADEN 7 ADC Enable
|
||
; ADCSR.ADSC 6 ADC Start Conversion
|
||
; ADCSR.ADFR 5 ADC Free Run Select
|
||
; ADCSR.ADIF 4 ADC Interrupt Flag
|
||
; ADCSR.ADIE 3 ADC Interrupt Enable
|
||
; ADCSR.ADPS2 2 ADC Prescaler Select Bit 2
|
||
; ADCSR.ADPS1 1 ADC Prescaler Select Bit 1
|
||
; ADCSR.ADPS0 0 ADC Prescaler Select Bit 0
|
||
; ADMUX 0x0027 ADC Multiplexer Select Register
|
||
; ADMUX.MUX2 2 Analog Channel Select Bit 2
|
||
; ADMUX.MUX1 1 Analog Channel Select Bit 1
|
||
; ADMUX.MUX0 0 Analog Channel Select Bit 0
|
||
; RESERVED0028 0x0028 RESERVED
|
||
; RESERVED0029 0x0029 RESERVED
|
||
; RESERVED002A 0x002A RESERVED
|
||
; RESERVED002B 0x002B RESERVED
|
||
; RESERVED002C 0x002C RESERVED
|
||
; RESERVED002D 0x002D RESERVED
|
||
; RESERVED002E 0x002E RESERVED
|
||
; RESERVED002F 0x002F RESERVED
|
||
; GIPR 0x0030 General Interrupt Pin Register
|
||
; GIPR.IPIN1 3 External Interrupt Pin 1
|
||
; GIPR.IPIN0 2 External Interrupt Pin 0
|
||
; RESERVED0031 0x0031 RESERVED
|
||
; RESERVED0032 0x0032 RESERVED
|
||
; RESERVED0033 0x0033 RESERVED
|
||
; RESERVED0034 0x0034 RESERVED
|
||
; RESERVED0035 0x0035 RESERVED
|
||
; RESERVED0036 0x0036 RESERVED
|
||
; RESERVED0037 0x0037 RESERVED
|
||
; RESERVED0038 0x0038 RESERVED
|
||
; RESERVED0039 0x0039 RESERVED
|
||
; DDRA 0x003A Port A Data Direction Register
|
||
; DDRA.DDA6 6 Port A Data Direction Register bit 6
|
||
; DDRA.DDA5 5 Port A Data Direction Register bit 5
|
||
; DDRA.DDA4 4 Port A Data Direction Register bit 4
|
||
; DDRA.DDA3 3 Port A Data Direction Register bit 3
|
||
; DDRA.DDA2 2 Port A Data Direction Register bit 2
|
||
; DDRA.DDA1 1 Port A Data Direction Register bit 1
|
||
; DDRA.DDA0 0 Port A Data Direction Register bit 0
|
||
; PORTA 0x003B Port A Data Register
|
||
; PORTA.PORTA6 6 Port A Data Register bit 6
|
||
; PORTA.PORTA5 5 Port A Data Register bit 5
|
||
; PORTA.PORTA4 4 Port A Data Register bit 4
|
||
; PORTA.PORTA3 3 Port A Data Register bit 3
|
||
; PORTA.PORTA2 2 Port A Data Register bit 2
|
||
; PORTA.PORTA1 1 Port A Data Register bit 1
|
||
; PORTA.PORTA0 0 Port A Data Register bit 0
|
||
; EECR 0x003C EEPROM Control Register
|
||
; EECR.EERIE 3 EEPROM Ready Interrupt Enable
|
||
; EECR.EEMWE 2 EEPROM Master Write Enable
|
||
; EECR.EEWE 1 EEPROM Write Enable
|
||
; EECR.EERE 0 EEPROM Read Enable
|
||
; EEDR 0x003D EEPROM Data Register
|
||
; EEARL 0x003E EEPROM Address Register Low
|
||
; EEARL.EEAR7 7
|
||
; EEARL.EEAR6 6
|
||
; EEARL.EEAR5 5
|
||
; EEARL.EEAR4 4
|
||
; EEARL.EEAR3 3
|
||
; EEARL.EEAR2 2
|
||
; EEARL.EEAR1 1
|
||
; EEARL.EEAR0 0
|
||
; EEARH 0x003F EEPROM Address Register High
|
||
; RESERVED0040 0x0040 RESERVED
|
||
; RESERVED0041 0x0041 RESERVED
|
||
; RESERVED0042 0x0042 RESERVED
|
||
; RESERVED0043 0x0043 RESERVED
|
||
; RESERVED0044 0x0044 RESERVED
|
||
; RESERVED0045 0x0045 RESERVED
|
||
; RESERVED0046 0x0046 RESERVED
|
||
; RESERVED0047 0x0047 RESERVED
|
||
; RESERVED0048 0x0048 RESERVED
|
||
; RESERVED0049 0x0049 RESERVED
|
||
; RESERVED004A 0x004A RESERVED
|
||
; RESERVED004B 0x004B RESERVED
|
||
; TCNT1L 0x004C Timer/Counter1 Low
|
||
; TCNT1H 0x004D Timer/Counter1 High
|
||
; TCCR1 0x004E Timer/Counter1 Control Register
|
||
; TCCR1.CS12 2 Clock Select1, Bit 2
|
||
; TCCR1.CS11 1 Clock Select1, Bit 1
|
||
; TCCR1.CS10 0 Clock Select1, Bit 0
|
||
; RESERVED004F 0x004F RESERVED
|
||
; RESERVED0050 0x0050 RESERVED
|
||
; RESERVED0051 0x0051 RESERVED
|
||
; TCNT0 0x0052 Timer Counter0
|
||
; TCCR0 0x0053 Timer/Counter0 Control Register
|
||
; TCCR0.CS02 2 Clock Select0, Bit 2
|
||
; TCCR0.CS01 1 Clock Select0, Bit 1
|
||
; TCCR0.CS00 0 Clock Select0, Bit 0
|
||
; RESERVED0054 0x0054 RESERVED
|
||
; MCUCR 0x0055 MCU Control Register
|
||
; MCUCR.SE 6 Sleep Enable
|
||
; MCUCR.SM 5 Sleep Mode
|
||
; MCUCR.ISC1 2 Interrupt Sense Control 1
|
||
; MCUCR.ISC0 0 Interrupt Sense Control 0
|
||
; RESERVED0056 0x0056 RESERVED
|
||
; RESERVED0057 0x0057 RESERVED
|
||
; TIFR 0x0058 Timer/Counter Interrupt Flag Register
|
||
; TIFR.TOV1 2 Timer/Counter1 Overflow Flag
|
||
; TIFR.TOV0 0 Timer/Counter0 Overflow Flag
|
||
; TIMSK 0x0059 Timer/Counter Interrupt Mask Register
|
||
; TIMSK.TOIE1 2 Timer/Counter1 Overflow Interrupt Enable
|
||
; TIMSK.TOIE0 0 Timer/Counter0 Overflow Interrupt Enable
|
||
; GIFR 0x005A General Interrupt Flag Register
|
||
; GIFR.INTF1 7 External Interrupt Flag 1
|
||
; GIFR.INTF0 6 External Interrupt Flag 0
|
||
; GIMSK 0x005B General Interrupt Mask Register
|
||
; GIMSK.INT1 7 External Interrupt Request 1 Enable
|
||
; GIMSK.INT0 6 External Interrupt Request 0 Enable
|
||
; RESERVED005C 0x005C RESERVED
|
||
; SPL 0x005D Stack Pointer Low
|
||
; SPL.SP7 7
|
||
; SPL.SP6 6
|
||
; SPL.SP5 5
|
||
; SPL.SP4 4
|
||
; SPL.SP3 3
|
||
; SPL.SP2 2
|
||
; SPL.SP1 1
|
||
; SPL.SP0 0
|
||
; SPH 0x005E Stack Pointer Low
|
||
; SPH.SP8 8
|
||
; SREG 0x005F Status Register
|
||
; SREG.I 7 Global Interrupt Enable
|
||
; SREG.T 6 Bit Copy Storage
|
||
; SREG.H 5 Half-carry Flag
|
||
; SREG.S 4 Sign Bit
|
||
; SREG.V 3 Two's Complement Overflow Flag
|
||
; SREG.N 2 Negative Flag
|
||
; SREG.Z 1 Zero Flag
|
||
; SREG.C 0 Carry Flag
|
||
|
||
|
||
.AT90S1200
|
||
SUBARCH=1
|
||
; doc0838.pdf
|
||
;
|
||
|
||
RAM=0
|
||
ROM=1024
|
||
EEPROM=64
|
||
|
||
|
||
; MEMORY MAP
|
||
|
||
|
||
; Interrupt and reset vector assignments
|
||
|
||
|
||
; INPUT/OUTPUT PORTS
|
||
RESERVED0000 0x0000 RESERVED
|
||
RESERVED0001 0x0001 RESERVED
|
||
RESERVED0002 0x0002 RESERVED
|
||
RESERVED0003 0x0003 RESERVED
|
||
RESERVED0004 0x0004 RESERVED
|
||
RESERVED0005 0x0005 RESERVED
|
||
RESERVED0006 0x0006 RESERVED
|
||
RESERVED0007 0x0007 RESERVED
|
||
ACSR 0x0008 Analog Comparator Control and Status Register
|
||
ACSR.ACD 7 Analog Comparator Disable
|
||
ACSR.ACO 5 Analog Comparator Output
|
||
ACSR.ACI 4 Analog Comparator Interrupt Flag
|
||
ACSR.ACIE 3 Analog Comparator Interrupt Enable
|
||
ACSR.ACIS1 1 Analog Comparator Interrupt Mode Select 1
|
||
ACSR.ACIS0 0 Analog Comparator Interrupt Mode Select 0
|
||
RESERVED000A 0x000A RESERVED
|
||
RESERVED000B 0x000B RESERVED
|
||
RESERVED000C 0x000C RESERVED
|
||
RESERVED000D 0x000D RESERVED
|
||
RESERVED000E 0x000E RESERVED
|
||
RESERVED000F 0x000F RESERVED
|
||
PIND 0x0010 Port D Input Pins Address
|
||
PIND.PIND6 6
|
||
PIND.PIND5 5
|
||
PIND.PIND4 4
|
||
PIND.PIND3 3
|
||
PIND.PIND2 2
|
||
PIND.PIND1 1
|
||
PIND.PIND0 0
|
||
DDRD 0x0011 Port D Data Direction Register
|
||
DDRD.DDD6 6 Port D Data Direction Register bit 6
|
||
DDRD.DDD5 5 Port D Data Direction Register bit 5
|
||
DDRD.DDD4 4 Port D Data Direction Register bit 4
|
||
DDRD.DDD3 3 Port D Data Direction Register bit 3
|
||
DDRD.DDD2 2 Port D Data Direction Register bit 2
|
||
DDRD.DDD1 1 Port D Data Direction Register bit 1
|
||
DDRD.DDD0 0 Port D Data Direction Register bit 0
|
||
PORTD 0x0012 Port D Data Register
|
||
PORTD.PORTD6 6 Port D Data Register bit 6
|
||
PORTD.PORTD5 5 Port D Data Register bit 5
|
||
PORTD.PORTD4 4 Port D Data Register bit 4
|
||
PORTD.PORTD3 3 Port D Data Register bit 3
|
||
PORTD.PORTD2 2 Port D Data Register bit 2
|
||
PORTD.PORTD1 1 Port D Data Register bit 1
|
||
PORTD.PORTD0 0 Port D Data Register bit 0
|
||
RESERVED0013 0x0013 RESERVED
|
||
RESERVED0014 0x0014 RESERVED
|
||
RESERVED0015 0x0015 RESERVED
|
||
PINB 0x0016 Port B Input Pin Address
|
||
PINB.PINB7 7
|
||
PINB.PINB6 6
|
||
PINB.PINB5 5
|
||
PINB.PINB4 4
|
||
PINB.PINB3 3
|
||
PINB.PINB2 2
|
||
PINB.PINB1 1
|
||
PINB.PINB0 0
|
||
DDRB 0x0017 Port B Data Direction Register
|
||
DDRB.DDB7 7 Port B Data Direction Register bit 7
|
||
DDRB.DDB6 6 Port B Data Direction Register bit 6
|
||
DDRB.DDB5 5 Port B Data Direction Register bit 5
|
||
DDRB.DDB4 4 Port B Data Direction Register bit 4
|
||
DDRB.DDB3 3 Port B Data Direction Register bit 3
|
||
DDRB.DDB2 2 Port B Data Direction Register bit 2
|
||
DDRB.DDB1 1 Port B Data Direction Register bit 1
|
||
DDRB.DDB0 0 Port B Data Direction Register bit 0
|
||
PORTB 0x0018 Port B Data Register
|
||
PORTB.PORTB7 7 Port B Data Register bit 7
|
||
PORTB.PORTB6 6 Port B Data Register bit 6
|
||
PORTB.PORTB5 5 Port B Data Register bit 5
|
||
PORTB.PORTB4 4 Port B Data Register bit 4
|
||
PORTB.PORTB3 3 Port B Data Register bit 3
|
||
PORTB.PORTB2 2 Port B Data Register bit 2
|
||
PORTB.PORTB1 1 Port B Data Register bit 1
|
||
PORTB.PORTB0 0 Port B Data Register bit 0
|
||
RESERVED0019 0x0019 RESERVED
|
||
RESERVED001A 0x001A RESERVED
|
||
RESERVED001B 0x001B RESERVED
|
||
EECR 0x001C EEPROM Control Register
|
||
EECR.EEWE 1 EEPROM Write Enable
|
||
EECR.EERE 0 EEPROM Read Enable
|
||
EEDR 0x001D EEPROM Data Register
|
||
EEDR.MSB 7
|
||
EEDR.LSB 0
|
||
EEAR 0x001E EEPROM Address Register
|
||
EEAR.EEAR5 5 EEPROM Address 5
|
||
EEAR.EEAR4 4 EEPROM Address 4
|
||
EEAR.EEAR3 3 EEPROM Address 3
|
||
EEAR.EEAR2 2 EEPROM Address 2
|
||
EEAR.EEAR1 1 EEPROM Address 1
|
||
EEAR.EEAR0 0 EEPROM Address 0
|
||
RESERVED001F 0x001F RESERVED
|
||
RESERVED0020 0x0020 RESERVED
|
||
WDTCR 0x0021 Watchdog Timer Control Register
|
||
WDTCR.WDE 3 Watchdog Enable
|
||
WDTCR.WDP2 2 Watchdog Timer Prescaler 2
|
||
WDTCR.WDP1 1 Watchdog Timer Prescaler 1
|
||
WDTCR.WDP0 0 Watchdog Timer Prescaler 0
|
||
RESERVED0022 0x0022 RESERVED
|
||
RESERVED0023 0x0023 RESERVED
|
||
RESERVED0024 0x0024 RESERVED
|
||
RESERVED0025 0x0025 RESERVED
|
||
RESERVED0026 0x0026 RESERVED
|
||
RESERVED0027 0x0027 RESERVED
|
||
RESERVED0028 0x0028 RESERVED
|
||
RESERVED0029 0x0029 RESERVED
|
||
RESERVED002A 0x002A RESERVED
|
||
RESERVED002B 0x002B RESERVED
|
||
RESERVED002C 0x002C RESERVED
|
||
RESERVED002D 0x002D RESERVED
|
||
RESERVED002E 0x002E RESERVED
|
||
RESERVED002F 0x002F RESERVED
|
||
RESERVED0030 0x0030 RESERVED
|
||
RESERVED0031 0x0031 RESERVED
|
||
TCNT0 0x0032 Timer/Counter0
|
||
TCNT0.MSB 7
|
||
TCNT0.LSB 0
|
||
TCCR0 0x0033 Timer/Counter0 Control Register
|
||
TCCR0.CS02 2 Clock Select0, Bit 2
|
||
TCCR0.CS01 1 Clock Select0, Bit 1
|
||
TCCR0.CS00 0 Clock Select0, Bit 0
|
||
RESERVED0034 0x0034 RESERVED
|
||
MCUCR 0x0035 MCU Control Register
|
||
MCUCR.SE 5 Sleep Enable
|
||
MCUCR.SM 4 Sleep Mode
|
||
MCUCR.ISC01 1 Interrupt Sense Control Bit 1
|
||
MCUCR.ISC00 0 Interrupt Sense Control Bit 0
|
||
RESERVED0036 0x0036 RESERVED
|
||
RESERVED0037 0x0037 RESERVED
|
||
TIFR 0x0038 Timer/Counter Interrupt FLAG Register
|
||
TIFR.TOV0 1 Timer/Counter0 Overflow Flag
|
||
TIMSK 0x0039 Timer/Counter Interrupt Mask Register
|
||
TIMSK.TOIE0 1 Timer/Counter0 Overflow Interrupt Enable
|
||
RESERVED003A 0x003A RESERVED
|
||
GIMSK 0x003B General Interrupt Mask Register
|
||
GIMSK.INT0 6 External Interrupt Request 0 Enable
|
||
RESERVED003C 0x003C RESERVED
|
||
RESERVED003D 0x003D RESERVED
|
||
RESERVED003E 0x003E RESERVED
|
||
SREG 0x003F Status Register
|
||
SREG.I 7 Global Interrupt Enable
|
||
SREG.T 6 Bit Copy Storage
|
||
SREG.H 5 Half-carry Flag
|
||
SREG.S 4 Sign Bit
|
||
SREG.V 3 Two's Complement Overflow Flag
|
||
SREG.N 2 Negative Flag
|
||
SREG.Z 1 Zero Flag
|
||
SREG.C 0 Carry Flag
|
||
|
||
|
||
.AT90S2313
|
||
SUBARCH=2
|
||
; doc0839.pdf
|
||
;
|
||
|
||
RAM=128
|
||
ROM=2048
|
||
EEPROM=128
|
||
|
||
|
||
; MEMORY MAP
|
||
area DATA GPWR_ 0x0000:0x0020 General Purpose Working Registers
|
||
area DATA FSR_ 0x0020:0x0080 I/O registers
|
||
area DATA SRAM_ 0x0080:0x00E0 SRAM
|
||
|
||
|
||
; Interrupt and reset vector assignments
|
||
entry __RESET 0x0000 Processor reset
|
||
entry INT0_ 0x0001 External Interrupt Request 0
|
||
entry INT1_ 0x0002 External Interrupt Request 1
|
||
entry TIMER1_CAPT1 0x0003 Timer/Counter1 Capture Event
|
||
entry TIMER1_COMP1 0x0004 Timer/Counter1 Compare Match
|
||
entry TIMER1_OVF1 0x0005 Timer/Counter1 Overflow
|
||
entry TIMER0_OVF0 0x0006 Timer/Counter0 Overflow
|
||
entry UART_RX 0x0007 UART, RX Complete
|
||
entry UART_UDRE 0x0008 UART Data Register Empty
|
||
entry UART_TX 0x0009 UART, TX Complete
|
||
entry ANA_COMP 0x000A Analog Comparator
|
||
|
||
|
||
; INPUT/OUTPUT PORTS
|
||
RESERVED0000 0x0000 RESERVED
|
||
RESERVED0001 0x0001 RESERVED
|
||
RESERVED0002 0x0002 RESERVED
|
||
RESERVED0003 0x0003 RESERVED
|
||
RESERVED0004 0x0004 RESERVED
|
||
RESERVED0005 0x0005 RESERVED
|
||
RESERVED0006 0x0006 RESERVED
|
||
RESERVED0007 0x0007 RESERVED
|
||
ACSR 0x0008 Analog Comparator Control and Status Register
|
||
ACSR.ACD 7 Analog Comparator Disable
|
||
ACSR.ACO 5 Analog Comparator Output
|
||
ACSR.ACI 4 Analog Comparator Interrupt Flag
|
||
ACSR.ACIE 3 Analog Comparator Interrupt Enable
|
||
ACSR.ACIC 2 Analog Comparator Input Capture Enable
|
||
ACSR.ACIS1 1 Analog Comparator Interrupt Mode Select 1
|
||
ACSR.ACIS0 0 Analog Comparator Interrupt Mode Select 0
|
||
UBRR 0x0009 UART Baud Rate Register
|
||
UCR 0x000A UART Control Register
|
||
UCR.RXCIE 7 RX Complete Interrupt Enable
|
||
UCR.TXCIE 6 TX Complete Interrupt Enable
|
||
UCR.UDRIE 5 UART Data Register Empty Interrupt Enable
|
||
UCR.RXEN 4 Receiver Enable
|
||
UCR.TXEN 3 Transmitter Enable
|
||
UCR.CHR9 2 9 Bit Characters
|
||
UCR.RXB8 1 Receive Data Bit 8
|
||
UCR.TXB8 0 Transmit Data Bit 8
|
||
USR 0x000B UART Status Register
|
||
USR.RXC 7 UART Receive Complete
|
||
USR.TXC 6 UART Transmit Complete
|
||
USR.UDRE 5 UART Data Register Empty
|
||
USR.FE 4 Framing Error
|
||
USR.OR 3 OverRun
|
||
UDR 0x000C The UART I/O Data Register
|
||
RESERVED000D 0x000D RESERVED
|
||
RESERVED000E 0x000E RESERVED
|
||
RESERVED000F 0x000F RESERVED
|
||
PIND 0x0010 Port D Input Pins Address
|
||
PIND.PIND6 6
|
||
PIND.PIND5 5
|
||
PIND.PIND4 4
|
||
PIND.PIND3 3
|
||
PIND.PIND2 2
|
||
PIND.PIND1 1
|
||
PIND.PIND0 0
|
||
DDRD 0x0011 Port D Data Direction Register
|
||
DDRD.DDD6 6 Port D Data Direction Register bit 6
|
||
DDRD.DDD5 5 Port D Data Direction Register bit 5
|
||
DDRD.DDD4 4 Port D Data Direction Register bit 4
|
||
DDRD.DDD3 3 Port D Data Direction Register bit 3
|
||
DDRD.DDD2 2 Port D Data Direction Register bit 2
|
||
DDRD.DDD1 1 Port D Data Direction Register bit 1
|
||
DDRD.DDD0 0 Port D Data Direction Register bit 0
|
||
PORTD 0x0012 Port D Data Register
|
||
PORTD.PORTD6 6 Port D Data Register bit 6
|
||
PORTD.PORTD5 5 Port D Data Register bit 5
|
||
PORTD.PORTD4 4 Port D Data Register bit 4
|
||
PORTD.PORTD3 3 Port D Data Register bit 3
|
||
PORTD.PORTD2 2 Port D Data Register bit 2
|
||
PORTD.PORTD1 1 Port D Data Register bit 1
|
||
PORTD.PORTD0 0 Port D Data Register bit 0
|
||
RESERVED0013 0x0013 RESERVED
|
||
RESERVED0014 0x0014 RESERVED
|
||
RESERVED0015 0x0015 RESERVED
|
||
PINB 0x0016 Port B Input Pins Address
|
||
PINB.PINB7 7
|
||
PINB.PINB6 6
|
||
PINB.PINB5 5
|
||
PINB.PINB4 4
|
||
PINB.PINB3 3
|
||
PINB.PINB2 2
|
||
PINB.PINB1 1
|
||
PINB.PINB0 0
|
||
DDRB 0x0017 Port B Data Direction Register
|
||
DDRB.DDB7 7 Port B Data Direction Register bit 7
|
||
DDRB.DDB6 6 Port B Data Direction Register bit 6
|
||
DDRB.DDB5 5 Port B Data Direction Register bit 5
|
||
DDRB.DDB4 4 Port B Data Direction Register bit 4
|
||
DDRB.DDB3 3 Port B Data Direction Register bit 3
|
||
DDRB.DDB2 2 Port B Data Direction Register bit 2
|
||
DDRB.DDB1 1 Port B Data Direction Register bit 1
|
||
DDRB.DDB0 0 Port B Data Direction Register bit 0
|
||
PORTB 0x0018 Port B Data Register
|
||
PORTB.PORTB7 7 Port B Data Register bit 7
|
||
PORTB.PORTB6 6 Port B Data Register bit 6
|
||
PORTB.PORTB5 5 Port B Data Register bit 5
|
||
PORTB.PORTB4 4 Port B Data Register bit 4
|
||
PORTB.PORTB3 3 Port B Data Register bit 3
|
||
PORTB.PORTB2 2 Port B Data Register bit 2
|
||
PORTB.PORTB1 1 Port B Data Register bit 1
|
||
PORTB.PORTB0 0 Port B Data Register bit 0
|
||
RESERVED0019 0x0019 RESERVED
|
||
RESERVED001A 0x001A RESERVED
|
||
RESERVED001B 0x001B RESERVED
|
||
EECR 0x001C EEPROM Control Register
|
||
EECR.EEMWE 2 EEPROM Master Write Enable
|
||
EECR.EEWE 1 EEPROM Write Enable
|
||
EECR.EERE 0 EEPROM Read Enable
|
||
EEDR 0x001D EEPROM Data Register
|
||
EEAR 0x001E EEPROM Address Register
|
||
EEAR.EEAR6 6 EEPROM Address 6
|
||
EEAR.EEAR5 5 EEPROM Address 5
|
||
EEAR.EEAR4 4 EEPROM Address 4
|
||
EEAR.EEAR3 3 EEPROM Address 3
|
||
EEAR.EEAR2 2 EEPROM Address 2
|
||
EEAR.EEAR1 1 EEPROM Address 1
|
||
EEAR.EEAR0 0 EEPROM Address 0
|
||
RESERVED001F 0x001F RESERVED
|
||
RESERVED0020 0x0020 RESERVED
|
||
WDTCR 0x0021 Watchdog Timer Control Register
|
||
WDTCR.WDTOE 4 Watchdog Turn-off Enable
|
||
WDTCR.WDE 3 Watchdog Enable
|
||
WDTCR.WDP2 2 Watchdog Timer Prescaler 2
|
||
WDTCR.WDP1 1 Watchdog Timer Prescaler 1
|
||
WDTCR.WDP0 0 Watchdog Timer Prescaler 0
|
||
RESERVED0022 0x0022 RESERVED
|
||
RESERVED0023 0x0023 RESERVED
|
||
ICR1L 0x0024 Timer/Counter1 Input Capture Register low
|
||
ICR1H 0x0025 Timer/Counter1 Input Capture Register high
|
||
RESERVED0026 0x0026 RESERVED
|
||
RESERVED0027 0x0027 RESERVED
|
||
RESERVED0028 0x0028 RESERVED
|
||
RESERVED0029 0x0029 RESERVED
|
||
OCR1AL 0x002A Timer/Counter1 Output Compare Register A low
|
||
OCR1AH 0x002B Timer/Counter1 Output Compare Register A high
|
||
TCNT1L 0x002C Timer/Counter1 low
|
||
TCNT1H 0x002D Timer/Counter1 high
|
||
TCCR1B 0x002E Timer/Counter1 Control Register B
|
||
TCCR1B.ICNC1 7 Input Capture1 Noise Canceler (4 CKs)
|
||
TCCR1B.ICES1 6 Input Capture1 Edge Select
|
||
TCCR1B.CTC1 3 Clear Timer/Counter1 on Compare Match
|
||
TCCR1B.CS12 2 Clock Select1 Bit 2
|
||
TCCR1B.CS11 1 Clock Select1 Bit 1
|
||
TCCR1B.CS10 0 Clock Select1 Bit 0
|
||
TCCR1A 0x002F Timer/Counter1 Control Register A
|
||
TCCR1A.COM1A1 7 Compare Output Mode1, Bits 1
|
||
TCCR1A.COM1A0 6 Compare Output Mode1, Bits 0
|
||
TCCR1A.PWM11 1 Pulse Width Modulator Select Bit 11
|
||
TCCR1A.PWM10 0 Pulse Width Modulator Select Bit 10
|
||
RESERVED0030 0x0030 RESERVED
|
||
RESERVED0031 0x0031 RESERVED
|
||
TCNT0 0x0032 Timer/Counter0
|
||
TCCR0 0x0033 Timer/Counter0 Control Register
|
||
TCCR0.CS02 2 Clock Select0, Bit 2
|
||
TCCR0.CS01 1 Clock Select0, Bit 1
|
||
TCCR0.CS00 0 Clock Select0, Bit 0
|
||
RESERVED0034 0x0034 RESERVED
|
||
MCUCR 0x0035 MCU Control Register
|
||
MCUCR.SE 5 Sleep Enable
|
||
MCUCR.SM 4 Sleep Mode
|
||
MCUCR.ISC11 3 InterruptSense Control 1 Bit 1
|
||
MCUCR.ISC10 2 InterruptSense Control 1 Bit 0
|
||
MCUCR.ISC01 1 Interrupt Sense Control 0 Bit 1
|
||
MCUCR.ISC00 0 Interrupt Sense Control 0 Bit 0
|
||
RESERVED0036 0x0036 RESERVED
|
||
RESERVED0037 0x0037 RESERVED
|
||
TIFR 0x0038 Timer/Counter Interrupt FLAG Register
|
||
TIFR.TOV1 7 Timer/Counter1 Overflow Flag
|
||
TIFR.OCF1A 6 Output Compare Flag 1A
|
||
TIFR.ICF1 3 Input Capture Flag 1
|
||
TIFR.TOV0 1 Timer/Counter0 Overflow Flag
|
||
TIMSK 0x0039 Timer/Counter Interrupt Mask Register
|
||
TIMSK.TOIE1 7 Timer/Counter1 Overflow Interrupt Enable
|
||
TIMSK.OCIE1A 6 Timer/Counter1 Output Compare Match Interrupt Enable
|
||
TIMSK.TICIE1 3 Timer/Counter1 Input Capture Interrupt Enable
|
||
TIMSK.TOIE0 1 Timer/Counter0 Overflow Interrupt Enable
|
||
GIFR 0x003A General Interrupt FLAG Register
|
||
GIFR.INTF1 7 External Interrupt Flag 1
|
||
GIFR.INTF0 6 External Interrupt Flag 0
|
||
GIMSK 0x003B General Interrupt Mask Register
|
||
GIMSK.INT1 7 External Interrupt Request 1 Enable
|
||
GIMSK.INT0 6 External Interrupt Request 0 Enable
|
||
RESERVED003C 0x003C RESERVED
|
||
SPL 0x003D Stack Pointer
|
||
SPL.SP7 7
|
||
SPL.SP6 6
|
||
SPL.SP5 5
|
||
SPL.SP4 4
|
||
SPL.SP3 3
|
||
SPL.SP2 2
|
||
SPL.SP1 1
|
||
SPL.SP0 0
|
||
RESERVED003E 0x003E RESERVED
|
||
SREG 0x003F Status Register
|
||
SREG.I 7 Global Interrupt Enable
|
||
SREG.T 6 Bit Copy Storage
|
||
SREG.H 5 Half-carry Flag
|
||
SREG.S 4 Sign Bit
|
||
SREG.V 3 Two's Complement Overflow Flag
|
||
SREG.N 2 Negative Flag
|
||
SREG.Z 1 Zero Flag
|
||
SREG.C 0 Carry Flag
|
||
|
||
; RESERVED0020 0x0020 RESERVED
|
||
; RESERVED0021 0x0021 RESERVED
|
||
; RESERVED0022 0x0022 RESERVED
|
||
; RESERVED0023 0x0023 RESERVED
|
||
; RESERVED0024 0x0024 RESERVED
|
||
; RESERVED0025 0x0025 RESERVED
|
||
; RESERVED0026 0x0026 RESERVED
|
||
; RESERVED0027 0x0027 RESERVED
|
||
; ACSR 0x0028 Analog Comparator Control and Status Register
|
||
; ACSR.ACD 7 Analog Comparator Disable
|
||
; ACSR.ACO 5 Analog Comparator Output
|
||
; ACSR.ACI 4 Analog Comparator Interrupt Flag
|
||
; ACSR.ACIE 3 Analog Comparator Interrupt Enable
|
||
; ACSR.ACIC 2 Analog Comparator Input Capture Enable
|
||
; ACSR.ACIS1 1 Analog Comparator Interrupt Mode Select 1
|
||
; ACSR.ACIS0 0 Analog Comparator Interrupt Mode Select 0
|
||
; UBRR 0x0029 UART Baud Rate Register
|
||
; UCR 0x002A UART Control Register
|
||
; UCR.RXCIE 7 RX Complete Interrupt Enable
|
||
; UCR.TXCIE 6 TX Complete Interrupt Enable
|
||
; UCR.UDRIE 5 UART Data Register Empty Interrupt Enable
|
||
; UCR.RXEN 4 Receiver Enable
|
||
; UCR.TXEN 3 Transmitter Enable
|
||
; UCR.CHR9 2 9 Bit Characters
|
||
; UCR.RXB8 1 Receive Data Bit 8
|
||
; UCR.TXB8 0 Transmit Data Bit 8
|
||
; USR 0x002B UART Status Register
|
||
; USR.RXC 7 UART Receive Complete
|
||
; USR.TXC 6 UART Transmit Complete
|
||
; USR.UDRE 5 UART Data Register Empty
|
||
; USR.FE 4 Framing Error
|
||
; USR.OR 3 OverRun
|
||
; UDR 0x002C The UART I/O Data Register
|
||
; RESERVED002D 0x002D RESERVED
|
||
; RESERVED002E 0x002E RESERVED
|
||
; RESERVED002F 0x002F RESERVED
|
||
; PIND 0x0030 Port D Input Pins Address
|
||
; PIND.PIND6 6
|
||
; PIND.PIND5 5
|
||
; PIND.PIND4 4
|
||
; PIND.PIND3 3
|
||
; PIND.PIND2 2
|
||
; PIND.PIND1 1
|
||
; PIND.PIND0 0
|
||
; DDRD 0x0031 Port D Data Direction Register
|
||
; DDRD.DDD6 6 Port D Data Direction Register bit 6
|
||
; DDRD.DDD5 5 Port D Data Direction Register bit 5
|
||
; DDRD.DDD4 4 Port D Data Direction Register bit 4
|
||
; DDRD.DDD3 3 Port D Data Direction Register bit 3
|
||
; DDRD.DDD2 2 Port D Data Direction Register bit 2
|
||
; DDRD.DDD1 1 Port D Data Direction Register bit 1
|
||
; DDRD.DDD0 0 Port D Data Direction Register bit 0
|
||
; PORTD 0x0032 Port D Data Register
|
||
; PORTD.PORTD6 6 Port D Data Register bit 6
|
||
; PORTD.PORTD5 5 Port D Data Register bit 5
|
||
; PORTD.PORTD4 4 Port D Data Register bit 4
|
||
; PORTD.PORTD3 3 Port D Data Register bit 3
|
||
; PORTD.PORTD2 2 Port D Data Register bit 2
|
||
; PORTD.PORTD1 1 Port D Data Register bit 1
|
||
; PORTD.PORTD0 0 Port D Data Register bit 0
|
||
; RESERVED0033 0x0033 RESERVED
|
||
; RESERVED0034 0x0034 RESERVED
|
||
; RESERVED0035 0x0035 RESERVED
|
||
; PINB 0x0036 Port B Input Pins Address
|
||
; PINB.PINB7 7
|
||
; PINB.PINB6 6
|
||
; PINB.PINB5 5
|
||
; PINB.PINB4 4
|
||
; PINB.PINB3 3
|
||
; PINB.PINB2 2
|
||
; PINB.PINB1 1
|
||
; PINB.PINB0 0
|
||
; DDRB 0x0037 Port B Data Direction Register
|
||
; DDRB.DDB7 7 Port B Data Direction Register bit 7
|
||
; DDRB.DDB6 6 Port B Data Direction Register bit 6
|
||
; DDRB.DDB5 5 Port B Data Direction Register bit 5
|
||
; DDRB.DDB4 4 Port B Data Direction Register bit 4
|
||
; DDRB.DDB3 3 Port B Data Direction Register bit 3
|
||
; DDRB.DDB2 2 Port B Data Direction Register bit 2
|
||
; DDRB.DDB1 1 Port B Data Direction Register bit 1
|
||
; DDRB.DDB0 0 Port B Data Direction Register bit 0
|
||
; PORTB 0x0038 Port B Data Register
|
||
; PORTB.PORTB7 7 Port B Data Register bit 7
|
||
; PORTB.PORTB6 6 Port B Data Register bit 6
|
||
; PORTB.PORTB5 5 Port B Data Register bit 5
|
||
; PORTB.PORTB4 4 Port B Data Register bit 4
|
||
; PORTB.PORTB3 3 Port B Data Register bit 3
|
||
; PORTB.PORTB2 2 Port B Data Register bit 2
|
||
; PORTB.PORTB1 1 Port B Data Register bit 1
|
||
; PORTB.PORTB0 0 Port B Data Register bit 0
|
||
; RESERVED0039 0x0039 RESERVED
|
||
; RESERVED003A 0x003A RESERVED
|
||
; RESERVED003B 0x003B RESERVED
|
||
; EECR 0x003C EEPROM Control Register
|
||
; EECR.EEMWE 2 EEPROM Master Write Enable
|
||
; EECR.EEWE 1 EEPROM Write Enable
|
||
; EECR.EERE 0 EEPROM Read Enable
|
||
; EEDR 0x003D EEPROM Data Register
|
||
; EEAR 0x003E EEPROM Address Register
|
||
; EEAR.EEAR6 6 EEPROM Address 6
|
||
; EEAR.EEAR5 5 EEPROM Address 5
|
||
; EEAR.EEAR4 4 EEPROM Address 4
|
||
; EEAR.EEAR3 3 EEPROM Address 3
|
||
; EEAR.EEAR2 2 EEPROM Address 2
|
||
; EEAR.EEAR1 1 EEPROM Address 1
|
||
; EEAR.EEAR0 0 EEPROM Address 0
|
||
; RESERVED003F 0x003F RESERVED
|
||
; RESERVED0040 0x0040 RESERVED
|
||
; WDTCR 0x0041 Watchdog Timer Control Register
|
||
; WDTCR.WDTOE 4 Watchdog Turn-off Enable
|
||
; WDTCR.WDE 3 Watchdog Enable
|
||
; WDTCR.WDP2 2 Watchdog Timer Prescaler 2
|
||
; WDTCR.WDP1 1 Watchdog Timer Prescaler 1
|
||
; WDTCR.WDP0 0 Watchdog Timer Prescaler 0
|
||
; RESERVED0042 0x0042 RESERVED
|
||
; RESERVED0043 0x0043 RESERVED
|
||
; ICR1L 0x0044 Timer/Counter1 Input Capture Register low
|
||
; ICR1H 0x0045 Timer/Counter1 Input Capture Register high
|
||
; RESERVED0046 0x0046 RESERVED
|
||
; RESERVED0047 0x0047 RESERVED
|
||
; RESERVED0048 0x0048 RESERVED
|
||
; RESERVED0049 0x0049 RESERVED
|
||
; OCR1AL 0x004A Timer/Counter1 Output Compare Register A low
|
||
; OCR1AH 0x004B Timer/Counter1 Output Compare Register A high
|
||
; TCNT1L 0x004C Timer/Counter1 low
|
||
; TCNT1H 0x004D Timer/Counter1 high
|
||
; TCCR1B 0x004E Timer/Counter1 Control Register B
|
||
; TCCR1B.ICNC1 7 Input Capture1 Noise Canceler (4 CKs)
|
||
; TCCR1B.ICES1 6 Input Capture1 Edge Select
|
||
; TCCR1B.CTC1 3 Clear Timer/Counter1 on Compare Match
|
||
; TCCR1B.CS12 2 Clock Select1 Bit 2
|
||
; TCCR1B.CS11 1 Clock Select1 Bit 1
|
||
; TCCR1B.CS10 0 Clock Select1 Bit 0
|
||
; TCCR1A 0x004F Timer/Counter1 Control Register A
|
||
; TCCR1A.COM1A1 7 Compare Output Mode1, Bits 1
|
||
; TCCR1A.COM1A0 6 Compare Output Mode1, Bits 0
|
||
; TCCR1A.PWM11 1 Pulse Width Modulator Select Bit 11
|
||
; TCCR1A.PWM10 0 Pulse Width Modulator Select Bit 10
|
||
; RESERVED0050 0x0050 RESERVED
|
||
; RESERVED0051 0x0051 RESERVED
|
||
; TCNT0 0x0052 Timer/Counter0
|
||
; TCCR0 0x0053 Timer/Counter0 Control Register
|
||
; TCCR0.CS02 2 Clock Select0, Bit 2
|
||
; TCCR0.CS01 1 Clock Select0, Bit 1
|
||
; TCCR0.CS00 0 Clock Select0, Bit 0
|
||
; RESERVED0054 0x0054 RESERVED
|
||
; MCUCR 0x0055 MCU Control Register
|
||
; MCUCR.SE 5 Sleep Enable
|
||
; MCUCR.SM 4 Sleep Mode
|
||
; MCUCR.ISC11 3 InterruptSense Control 1 Bit 1
|
||
; MCUCR.ISC10 2 InterruptSense Control 1 Bit 0
|
||
; MCUCR.ISC01 1 Interrupt Sense Control 0 Bit 1
|
||
; MCUCR.ISC00 0 Interrupt Sense Control 0 Bit 0
|
||
; RESERVED0056 0x0056 RESERVED
|
||
; RESERVED0057 0x0057 RESERVED
|
||
; TIFR 0x0058 Timer/Counter Interrupt FLAG Register
|
||
; TIFR.TOV1 7 Timer/Counter1 Overflow Flag
|
||
; TIFR.OCF1A 6 Output Compare Flag 1A
|
||
; TIFR.ICF1 3 Input Capture Flag 1
|
||
; TIFR.TOV0 1 Timer/Counter0 Overflow Flag
|
||
; TIMSK 0x0059 Timer/Counter Interrupt Mask Register
|
||
; TIMSK.TOIE1 7 Timer/Counter1 Overflow Interrupt Enable
|
||
; TIMSK.OCIE1A 6 Timer/Counter1 Output Compare Match Interrupt Enable
|
||
; TIMSK.TICIE1 3 Timer/Counter1 Input Capture Interrupt Enable
|
||
; TIMSK.TOIE0 1 Timer/Counter0 Overflow Interrupt Enable
|
||
; GIFR 0x005A General Interrupt FLAG Register
|
||
; GIFR.INTF1 7 External Interrupt Flag 1
|
||
; GIFR.INTF0 6 External Interrupt Flag 0
|
||
; GIMSK 0x005B General Interrupt Mask Register
|
||
; GIMSK.INT1 7 External Interrupt Request 1 Enable
|
||
; GIMSK.INT0 6 External Interrupt Request 0 Enable
|
||
; RESERVED005C 0x005C RESERVED
|
||
; SPL 0x005D Stack Pointer
|
||
; SPL.SP7 7
|
||
; SPL.SP6 6
|
||
; SPL.SP5 5
|
||
; SPL.SP4 4
|
||
; SPL.SP3 3
|
||
; SPL.SP2 2
|
||
; SPL.SP1 1
|
||
; SPL.SP0 0
|
||
; RESERVED005E 0x005E RESERVED
|
||
; SREG 0x005F Status Register
|
||
; SREG.I 7 Global Interrupt Enable
|
||
; SREG.T 6 Bit Copy Storage
|
||
; SREG.H 5 Half-carry Flag
|
||
; SREG.S 4 Sign Bit
|
||
; SREG.V 3 Two's Complement Overflow Flag
|
||
; SREG.N 2 Negative Flag
|
||
; SREG.Z 1 Zero Flag
|
||
; SREG.C 0 Carry Flag
|
||
|
||
|
||
.AT90S2323_43
|
||
SUBARCH=2
|
||
; doc1004.pdf
|
||
;
|
||
|
||
RAM=128
|
||
ROM=2048
|
||
EEPROM=128
|
||
|
||
|
||
; MEMORY MAP
|
||
area DATA GPWR_ 0x0000:0x0020 General Purpose Working Registers
|
||
area DATA FSR_ 0x0020:0x0080 I/O registers
|
||
area DATA SRAM_ 0x0080:0x00E0 SRAM
|
||
|
||
|
||
; Interrupt and reset vector assignments
|
||
|
||
|
||
; INPUT/OUTPUT PORTS
|
||
RESERVED0000 0x0000 RESERVED
|
||
RESERVED0001 0x0001 RESERVED
|
||
RESERVED0002 0x0002 RESERVED
|
||
RESERVED0003 0x0003 RESERVED
|
||
RESERVED0004 0x0004 RESERVED
|
||
RESERVED0005 0x0005 RESERVED
|
||
RESERVED0006 0x0006 RESERVED
|
||
RESERVED0007 0x0007 RESERVED
|
||
RESERVED0008 0x0008 RESERVED
|
||
RESERVED0009 0x0009 RESERVED
|
||
RESERVED000A 0x000A RESERVED
|
||
RESERVED000B 0x000B RESERVED
|
||
RESERVED000C 0x000C RESERVED
|
||
RESERVED000D 0x000D RESERVED
|
||
RESERVED000E 0x000E RESERVED
|
||
RESERVED000F 0x000F RESERVED
|
||
RESERVED0010 0x0010 RESERVED
|
||
RESERVED0011 0x0011 RESERVED
|
||
RESERVED0012 0x0012 RESERVED
|
||
RESERVED0013 0x0013 RESERVED
|
||
RESERVED0014 0x0014 RESERVED
|
||
RESERVED0015 0x0015 RESERVED
|
||
PINB 0x0016 Port B Input Pins Address
|
||
PINB.PINB4 4
|
||
PINB.PINB3 3
|
||
PINB.PINB2 2
|
||
PINB.PINB1 1
|
||
PINB.PINB0 0
|
||
DDRB 0x0017 Port B Data Direction Register
|
||
DDRB.DDB4 4 Port B Data Direction Register bit 4
|
||
DDRB.DDB3 3 Port B Data Direction Register bit 3
|
||
DDRB.DDB2 2 Port B Data Direction Register bit 2
|
||
DDRB.DDB1 1 Port B Data Direction Register bit 1
|
||
DDRB.DDB0 0 Port B Data Direction Register bit 0
|
||
PORTB 0x0018 Port B Data Register
|
||
PORTB.PORTB4 4 Port B Data Register bit 4
|
||
PORTB.PORTB3 3 Port B Data Register bit 3
|
||
PORTB.PORTB2 2 Port B Data Register bit 2
|
||
PORTB.PORTB1 1 Port B Data Register bit 1
|
||
PORTB.PORTB0 0 Port B Data Register bit 0
|
||
RESERVED0019 0x0019 RESERVED
|
||
RESERVED001A 0x001A RESERVED
|
||
RESERVED001B 0x001B RESERVED
|
||
EECR 0x001C EEPROM Control Register
|
||
EECR.EEMWE 2 EEPROM Master Write Enable
|
||
EECR.EEWE 1 EEPROM Write Enable
|
||
EECR.EERE 0 EEPROM Read Enable
|
||
EEDR 0x001D EEPROM Data Register
|
||
EEAR 0x001E EEPROM Address Register
|
||
EEAR.EEAR6 6 EEPROM Address 6
|
||
EEAR.EEAR5 5 EEPROM Address 5
|
||
EEAR.EEAR4 4 EEPROM Address 4
|
||
EEAR.EEAR3 3 EEPROM Address 3
|
||
EEAR.EEAR2 2 EEPROM Address 2
|
||
EEAR.EEAR1 1 EEPROM Address 1
|
||
EEAR.EEAR0 0 EEPROM Address 0
|
||
RESERVED001F 0x001F RESERVED
|
||
RESERVED0020 0x0020 RESERVED
|
||
WDTCR 0x0021 Watchdog Timer Control Register
|
||
WDTCR.WDTOE 4 Watchdog Turn-off Enable
|
||
WDTCR.WDE 3 Watchdog Enable
|
||
WDTCR.WDP2 2 Watchdog Timer Prescaler 2
|
||
WDTCR.WDP1 1 Watchdog Timer Prescaler 1
|
||
WDTCR.WDP0 0 Watchdog Timer Prescaler 0
|
||
RESERVED0022 0x0022 RESERVED
|
||
RESERVED0023 0x0023 RESERVED
|
||
RESERVED0024 0x0024 RESERVED
|
||
RESERVED0025 0x0025 RESERVED
|
||
RESERVED0026 0x0026 RESERVED
|
||
RESERVED0027 0x0027 RESERVED
|
||
RESERVED0028 0x0028 RESERVED
|
||
RESERVED0029 0x0029 RESERVED
|
||
RESERVED002A 0x002A RESERVED
|
||
RESERVED002B 0x002B RESERVED
|
||
RESERVED002C 0x002C RESERVED
|
||
RESERVED002D 0x002D RESERVED
|
||
RESERVED002E 0x002E RESERVED
|
||
RESERVED002F 0x002F RESERVED
|
||
RESERVED0030 0x0030 RESERVED
|
||
RESERVED0031 0x0031 RESERVED
|
||
TCNT0 0x0032 Timer/Counter0
|
||
TCCR0 0x0033 Timer/Counter0 Control Register
|
||
TCCR0.CS02 2 Clock Select0 Bit 2
|
||
TCCR0.CS01 1 Clock Select0 Bit 1
|
||
TCCR0.CS00 0 Clock Select0 Bit 0
|
||
MCUSR 0x0034 MCU Status Register
|
||
MCUSR.EXTRF 1 External Reset Flag
|
||
MCUSR.PORF 0 Power-on Reset Flag
|
||
MCUCR 0x0035 MCU Control Register
|
||
MCUCR.SE 5 Sleep Enable
|
||
MCUCR.SM 4 Sleep Mode
|
||
MCUCR.ISC01 1 Interrupt Sense Control 0 Bit 1
|
||
MCUCR.ISC00 0 Interrupt Sense Control 0 Bit 0
|
||
RESERVED0036 0x0036 RESERVED
|
||
RESERVED0037 0x0037 RESERVED
|
||
TIFR 0x0038 Timer/Counter Interrupt FLAG Register
|
||
TIFR.TOV0 1 Timer/Counter 0 Overflow Flag
|
||
TIMSK 0x0039 Timer/Counter Interrupt Mask Register
|
||
TIMSK.TOIE0 1 Timer/Counter 0 Overflow Interrupt Enable
|
||
GIFR 0x003A General Interrupt Flag Register
|
||
GIFR.INTF0 6 External Interrupt Flag 0
|
||
GIMSK 0x003B General Interrupt Mask Register
|
||
GIMSK.INT0 6 External Interrupt Request 0 Enable
|
||
RESERVED003C 0x003C RESERVED
|
||
SPL 0x003D Stack Pointer
|
||
SPL.SP7 7
|
||
SPL.SP6 6
|
||
SPL.SP5 5
|
||
SPL.SP4 4
|
||
SPL.SP3 3
|
||
SPL.SP2 2
|
||
SPL.SP1 1
|
||
SPL.SP0 0
|
||
RESERVED003E 0x003E RESERVED
|
||
SREG 0x003F Status Register
|
||
SREG.I 7 Global Interrupt Enable
|
||
SREG.T 6 Bit Copy Storage
|
||
SREG.H 5 Half-carry Flag
|
||
SREG.S 4 Sign Bit
|
||
SREG.V 3 Two's Complement Overflow Flag
|
||
SREG.N 2 Negative Flag
|
||
SREG.Z 1 Zero Flag
|
||
SREG.C 0 Carry Flag
|
||
|
||
; RESERVED0020 0x0020 RESERVED
|
||
; RESERVED0021 0x0021 RESERVED
|
||
; RESERVED0022 0x0022 RESERVED
|
||
; RESERVED0023 0x0023 RESERVED
|
||
; RESERVED0024 0x0024 RESERVED
|
||
; RESERVED0025 0x0025 RESERVED
|
||
; RESERVED0026 0x0026 RESERVED
|
||
; RESERVED0027 0x0027 RESERVED
|
||
; RESERVED0028 0x0028 RESERVED
|
||
; RESERVED0029 0x0029 RESERVED
|
||
; RESERVED002A 0x002A RESERVED
|
||
; RESERVED002B 0x002B RESERVED
|
||
; RESERVED002C 0x002C RESERVED
|
||
; RESERVED002D 0x002D RESERVED
|
||
; RESERVED002E 0x002E RESERVED
|
||
; RESERVED002F 0x002F RESERVED
|
||
; RESERVED0030 0x0010 RESERVED
|
||
; RESERVED0031 0x0031 RESERVED
|
||
; RESERVED0032 0x0032 RESERVED
|
||
; RESERVED0033 0x0033 RESERVED
|
||
; RESERVED0034 0x0034 RESERVED
|
||
; RESERVED0035 0x0035 RESERVED
|
||
; PINB 0x0036 Port B Input Pins Address
|
||
; PINB.PINB4 4
|
||
; PINB.PINB3 3
|
||
; PINB.PINB2 2
|
||
; PINB.PINB1 1
|
||
; PINB.PINB0 0
|
||
; DDRB 0x0037 Port B Data Direction Register
|
||
; DDRB.DDB4 4 Port B Data Direction Register bit 4
|
||
; DDRB.DDB3 3 Port B Data Direction Register bit 3
|
||
; DDRB.DDB2 2 Port B Data Direction Register bit 2
|
||
; DDRB.DDB1 1 Port B Data Direction Register bit 1
|
||
; DDRB.DDB0 0 Port B Data Direction Register bit 0
|
||
; PORTB 0x0038 Port B Data Register
|
||
; PORTB.PORTB4 4 Port B Data Register bit 4
|
||
; PORTB.PORTB3 3 Port B Data Register bit 3
|
||
; PORTB.PORTB2 2 Port B Data Register bit 2
|
||
; PORTB.PORTB1 1 Port B Data Register bit 1
|
||
; PORTB.PORTB0 0 Port B Data Register bit 0
|
||
; RESERVED0039 0x0039 RESERVED
|
||
; RESERVED003A 0x003A RESERVED
|
||
; RESERVED003B 0x003B RESERVED
|
||
; EECR 0x003C EEPROM Control Register
|
||
; EECR.EEMWE 2 EEPROM Master Write Enable
|
||
; EECR.EEWE 1 EEPROM Write Enable
|
||
; EECR.EERE 0 EEPROM Read Enable
|
||
; EEDR 0x003D EEPROM Data Register
|
||
; EEAR 0x003E EEPROM Address Register
|
||
; EEAR.EEAR6 6 EEPROM Address 6
|
||
; EEAR.EEAR5 5 EEPROM Address 5
|
||
; EEAR.EEAR4 4 EEPROM Address 4
|
||
; EEAR.EEAR3 3 EEPROM Address 3
|
||
; EEAR.EEAR2 2 EEPROM Address 2
|
||
; EEAR.EEAR1 1 EEPROM Address 1
|
||
; EEAR.EEAR0 0 EEPROM Address 0
|
||
; RESERVED003F 0x003F RESERVED
|
||
; RESERVED0040 0x0040 RESERVED
|
||
; WDTCR 0x0041 Watchdog Timer Control Register
|
||
; WDTCR.WDTOE 4 Watchdog Turn-off Enable
|
||
; WDTCR.WDE 3 Watchdog Enable
|
||
; WDTCR.WDP2 2 Watchdog Timer Prescaler 2
|
||
; WDTCR.WDP1 1 Watchdog Timer Prescaler 1
|
||
; WDTCR.WDP0 0 Watchdog Timer Prescaler 0
|
||
; RESERVED0042 0x0042 RESERVED
|
||
; RESERVED0043 0x0043 RESERVED
|
||
; RESERVED0044 0x0044 RESERVED
|
||
; RESERVED0045 0x0045 RESERVED
|
||
; RESERVED0046 0x0046 RESERVED
|
||
; RESERVED0047 0x0047 RESERVED
|
||
; RESERVED0048 0x0048 RESERVED
|
||
; RESERVED0049 0x0049 RESERVED
|
||
; RESERVED004A 0x004A RESERVED
|
||
; RESERVED004B 0x004B RESERVED
|
||
; RESERVED004C 0x004C RESERVED
|
||
; RESERVED004D 0x004D RESERVED
|
||
; RESERVED004E 0x004E RESERVED
|
||
; RESERVED004F 0x004F RESERVED
|
||
; RESERVED0050 0x0050 RESERVED
|
||
; RESERVED0051 0x0051 RESERVED
|
||
; TCNT0 0x0052 Timer/Counter0
|
||
; TCCR0 0x0053 Timer/Counter0 Control Register
|
||
; TCCR0.CS02 2 Clock Select0 Bit 2
|
||
; TCCR0.CS01 1 Clock Select0 Bit 1
|
||
; TCCR0.CS00 0 Clock Select0 Bit 0
|
||
; MCUSR 0x0054 MCU Status Register
|
||
; MCUSR.EXTRF 1 External Reset Flag
|
||
; MCUSR.PORF 0 Power-on Reset Flag
|
||
; MCUCR 0x0055 MCU Control Register
|
||
; MCUCR.SE 5 Sleep Enable
|
||
; MCUCR.SM 4 Sleep Mode
|
||
; MCUCR.ISC01 1 Interrupt Sense Control 0 Bit 1
|
||
; MCUCR.ISC00 0 Interrupt Sense Control 0 Bit 0
|
||
; RESERVED0056 0x0056 RESERVED
|
||
; RESERVED0057 0x0057 RESERVED
|
||
; TIFR 0x0058 Timer/Counter Interrupt FLAG Register
|
||
; TIFR.TOV0 1 Timer/Counter 0 Overflow Flag
|
||
; TIMSK 0x0059 Timer/Counter Interrupt Mask Register
|
||
; TIMSK.TOIE0 1 Timer/Counter 0 Overflow Interrupt Enable
|
||
; GIFR 0x005A General Interrupt Flag Register
|
||
; GIFR.INTF0 6 External Interrupt Flag 0
|
||
; GIMSK 0x005B General Interrupt Mask Register
|
||
; GIMSK.INT0 6 External Interrupt Request 0 Enable
|
||
; RESERVED005C 0x005C RESERVED
|
||
; SPL 0x005D Stack Pointer
|
||
; SPL.SP7 7
|
||
; SPL.SP6 6
|
||
; SPL.SP5 5
|
||
; SPL.SP4 4
|
||
; SPL.SP3 3
|
||
; SPL.SP2 2
|
||
; SPL.SP1 1
|
||
; SPL.SP0 0
|
||
; RESERVED005E 0x005E RESERVED
|
||
; SREG 0x005F Status Register
|
||
; SREG.I 7 Global Interrupt Enable
|
||
; SREG.T 6 Bit Copy Storage
|
||
; SREG.H 5 Half-carry Flag
|
||
; SREG.S 4 Sign Bit
|
||
; SREG.V 3 Two's Complement Overflow Flag
|
||
; SREG.N 2 Negative Flag
|
||
; SREG.Z 1 Zero Flag
|
||
; SREG.C 0 Carry Flag
|
||
|
||
|
||
.AT90S8515
|
||
SUBARCH=2
|
||
; doc0841.pdf
|
||
;
|
||
|
||
RAM=512
|
||
ROM=8192
|
||
EEPROM=512
|
||
|
||
|
||
; MEMORY MAP
|
||
area DATA GPWR_ 0x0000:0x0020 General Purpose Working Registers
|
||
area DATA FSR_ 0x0020:0x0060 I/O registers
|
||
area DATA I_SRAM 0x0060:0x0260 Internal SRAM
|
||
area DATA E_SRAM 0x0260:0x10000 External SRAM
|
||
|
||
|
||
; Interrupt and reset vector assignments
|
||
entry __RESET 0x0000 External Reset, Power-on Reset and Watchdog Reset
|
||
entry INT0_ 0x0001 External Interrupt Request 0
|
||
entry INT1_ 0x0002 External Interrupt Request 1
|
||
entry TIMER1_CAPT 0x0003 Timer/Counter1 Capture Event
|
||
entry TIMER1_COMPA 0x0004 Timer/Counter1 Compare Match A
|
||
entry TIMER1_COMPB 0x0005 Timer/Counter1 Compare Match B
|
||
entry TIMER1_OVF 0x0006 Timer/Counter1 Overflow
|
||
entry TIMER0_OVF 0x0007 Timer/Counter0 Overflow
|
||
entry SPI_STC 0x0008 Serial Transfer Complete
|
||
entry UART_RX 0x0009 UART, Rx Complete
|
||
entry UART_UDRE 0x000A UART Data Register Empty
|
||
entry UART_TX 0x000B UART, Tx Complete
|
||
entry ANA_COMP 0x000C Analog Comparator
|
||
|
||
|
||
; INPUT/OUTPUT PORTS
|
||
RESERVED0000 0x0000 RESERVED
|
||
RESERVED0001 0x0001 RESERVED
|
||
RESERVED0002 0x0002 RESERVED
|
||
RESERVED0003 0x0003 RESERVED
|
||
RESERVED0004 0x0004 RESERVED
|
||
RESERVED0005 0x0005 RESERVED
|
||
RESERVED0006 0x0006 RESERVED
|
||
RESERVED0007 0x0007 RESERVED
|
||
ACSR 0x0008 Analog Comparator Control and Status Register
|
||
ACSR.ACD 7 Analog Comparator Disable
|
||
ACSR.ACO 5 Analog Comparator Output
|
||
ACSR.ACI 4 Analog Comparator Interrupt Flag
|
||
ACSR.ACIE 3 Analog Comparator Interrupt Enable
|
||
ACSR.ACIC 2 Analog Comparator Input Capture Enable
|
||
ACSR.ACIS1 1 Analog Comparator Interrupt Mode Select 1
|
||
ACSR.ACIS0 0 Analog Comparator Interrupt Mode Select 0
|
||
UBRR 0x0009 UART BAUD Rate Register
|
||
UCR 0x000A UART Control Register
|
||
UCR.RXCIE 7 RX Complete Interrupt Enable
|
||
UCR.TXCIE 6 TX Complete Interrupt Enable
|
||
UCR.UDRIE 5 UART Data Register Empty Interrupt Enable
|
||
UCR.RXEN 4 Receiver Enable
|
||
UCR.TXEN 3 Transmitter Enable
|
||
UCR.CHR9 2 9-bit Characters
|
||
UCR.RXB8 1 Receive Data Bit 8
|
||
UCR.TXB8 0 Transmit Data Bit 8
|
||
USR 0x000B UART Status Register
|
||
USR.RXC 7 UART Receive Complete
|
||
USR.TXC 6 UART Transmit Complete
|
||
USR.UDRE 5 UART Data Register Empty
|
||
USR.FE 4 Framing Error
|
||
USR.OR 3 Overrun
|
||
UDR 0x000C UART I/O Data Register
|
||
SPCR 0x000D SPI Control Register
|
||
SPCR.SPIE 7 SPI Interrupt Enable
|
||
SPCR.SPE 6 SPI Enable
|
||
SPCR.DORD 5 Data Order
|
||
SPCR.MSTR 4 Master/Slave Select
|
||
SPCR.CPOL 3 Clock Polarity
|
||
SPCR.CPHA 2 Clock Phase
|
||
SPCR.SPR1 1 SPI Clock Rate Select 1
|
||
SPCR.SPR0 0 SPI Clock Rate Select 0
|
||
SPSR 0x000E SPI Status Register
|
||
SPSR.SPIF 7 SPI Interrupt Flag
|
||
SPSR.WCOL 6 Write Collision Flag
|
||
SPDR 0x000F SPI Data Register
|
||
PIND 0x0010 Port D Input Pins Address
|
||
PIND.PIND7 7
|
||
PIND.PIND6 6
|
||
PIND.PIND5 5
|
||
PIND.PIND4 4
|
||
PIND.PIND3 3
|
||
PIND.PIND2 2
|
||
PIND.PIND1 1
|
||
PIND.PIND0 0
|
||
DDRD 0x0011 Port D Data Direction Register
|
||
DDRD.DDD7 7 Port D Data Direction Register bit 7
|
||
DDRD.DDD6 6 Port D Data Direction Register bit 6
|
||
DDRD.DDD5 5 Port D Data Direction Register bit 5
|
||
DDRD.DDD4 4 Port D Data Direction Register bit 4
|
||
DDRD.DDD3 3 Port D Data Direction Register bit 3
|
||
DDRD.DDD2 2 Port D Data Direction Register bit 2
|
||
DDRD.DDD1 1 Port D Data Direction Register bit 1
|
||
DDRD.DDD0 0 Port D Data Direction Register bit 0
|
||
PORTD 0x0012 Port D Data Register
|
||
PORTD.PORTD7 7 Port D Data Register bit 7
|
||
PORTD.PORTD6 6 Port D Data Register bit 6
|
||
PORTD.PORTD5 5 Port D Data Register bit 5
|
||
PORTD.PORTD4 4 Port D Data Register bit 4
|
||
PORTD.PORTD3 3 Port D Data Register bit 3
|
||
PORTD.PORTD2 2 Port D Data Register bit 2
|
||
PORTD.PORTD1 1 Port D Data Register bit 1
|
||
PORTD.PORTD0 0 Port D Data Register bit 0
|
||
PINC 0x0013 Port C Input Pins Address
|
||
PINC.PINC7 7
|
||
PINC.PINC6 6
|
||
PINC.PINC5 5
|
||
PINC.PINC4 4
|
||
PINC.PINC3 3
|
||
PINC.PINC2 2
|
||
PINC.PINC1 1
|
||
PINC.PINC0 0
|
||
DDRC 0x0014 Port C Data Direction Register
|
||
DDRC.DDC7 7 Port C Data Direction Register bit 7
|
||
DDRC.DDC6 6 Port C Data Direction Register bit 6
|
||
DDRC.DDC5 5 Port C Data Direction Register bit 5
|
||
DDRC.DDC4 4 Port C Data Direction Register bit 4
|
||
DDRC.DDC3 3 Port C Data Direction Register bit 3
|
||
DDRC.DDC2 2 Port C Data Direction Register bit 2
|
||
DDRC.DDC1 1 Port C Data Direction Register bit 1
|
||
DDRC.DDC0 0 Port C Data Direction Register bit 0
|
||
PORTC 0x0015 Port C Data Register
|
||
PORTC.PORTC7 7 Port C Data Register bit 7
|
||
PORTC.PORTC6 6 Port C Data Register bit 6
|
||
PORTC.PORTC5 5 Port C Data Register bit 5
|
||
PORTC.PORTC4 4 Port C Data Register bit 4
|
||
PORTC.PORTC3 3 Port C Data Register bit 3
|
||
PORTC.PORTC2 2 Port C Data Register bit 2
|
||
PORTC.PORTC1 1 Port C Data Register bit 1
|
||
PORTC.PORTC0 0 Port C Data Register bit 0
|
||
PINB 0x0016 Port B Input Pins Address
|
||
PINB.PINB7 7
|
||
PINB.PINB6 6
|
||
PINB.PINB5 5
|
||
PINB.PINB4 4
|
||
PINB.PINB3 3
|
||
PINB.PINB2 2
|
||
PINB.PINB1 1
|
||
PINB.PINB0 0
|
||
DDRB 0x0017 Port B Data Direction Register
|
||
DDRB.DDB7 7 Port B Data Direction Register bit 7
|
||
DDRB.DDB6 6 Port B Data Direction Register bit 6
|
||
DDRB.DDB5 5 Port B Data Direction Register bit 5
|
||
DDRB.DDB4 4 Port B Data Direction Register bit 4
|
||
DDRB.DDB3 3 Port B Data Direction Register bit 3
|
||
DDRB.DDB2 2 Port B Data Direction Register bit 2
|
||
DDRB.DDB1 1 Port B Data Direction Register bit 1
|
||
DDRB.DDB0 0 Port B Data Direction Register bit 0
|
||
PORTB 0x0018 Port B Data Register
|
||
PORTB.PORTB7 7 Port B Data Register bit 7
|
||
PORTB.PORTB6 6 Port B Data Register bit 6
|
||
PORTB.PORTB5 5 Port B Data Register bit 5
|
||
PORTB.PORTB4 4 Port B Data Register bit 4
|
||
PORTB.PORTB3 3 Port B Data Register bit 3
|
||
PORTB.PORTB2 2 Port B Data Register bit 2
|
||
PORTB.PORTB1 1 Port B Data Register bit 1
|
||
PORTB.PORTB0 0 Port B Data Register bit 0
|
||
PINA 0x0019 Port A Input Pins Address
|
||
PINA.PINA7 7
|
||
PINA.PINA6 6
|
||
PINA.PINA5 5
|
||
PINA.PINA4 4
|
||
PINA.PINA3 3
|
||
PINA.PINA2 2
|
||
PINA.PINA1 1
|
||
PINA.PINA0 0
|
||
DDRA 0x001A Port A Data Direction Register
|
||
DDRA.DDA7 7 Port A Data Direction Register bit 7
|
||
DDRA.DDA6 6 Port A Data Direction Register bit 6
|
||
DDRA.DDA5 5 Port A Data Direction Register bit 5
|
||
DDRA.DDA4 4 Port A Data Direction Register bit 4
|
||
DDRA.DDA3 3 Port A Data Direction Register bit 3
|
||
DDRA.DDA2 2 Port A Data Direction Register bit 2
|
||
DDRA.DDA1 1 Port A Data Direction Register bit 1
|
||
DDRA.DDA0 0 Port A Data Direction Register bit 0
|
||
PORTA 0x001B Port A Data Register
|
||
PORTA.PORTA7 7 Port A Data Register bit 7
|
||
PORTA.PORTA6 6 Port A Data Register bit 6
|
||
PORTA.PORTA5 5 Port A Data Register bit 5
|
||
PORTA.PORTA4 4 Port A Data Register bit 4
|
||
PORTA.PORTA3 3 Port A Data Register bit 3
|
||
PORTA.PORTA2 2 Port A Data Register bit 2
|
||
PORTA.PORTA1 1 Port A Data Register bit 1
|
||
PORTA.PORTA0 0 Port A Data Register bit 0
|
||
EECR 0x001C EEPROM Control Register
|
||
EECR.EEMWE 2 EEPROM Master Write Enable
|
||
EECR.EEWE 1 EEPROM Write Enable
|
||
EECR.EERE 0 EEPROM Read Enable
|
||
EEDR 0x001D EEPROM Data Register
|
||
EEARL 0x001E EEPROM Address Register Low
|
||
EEARL.EEAR7 7
|
||
EEARL.EEAR6 6
|
||
EEARL.EEAR5 5
|
||
EEARL.EEAR4 4
|
||
EEARL.EEAR3 3
|
||
EEARL.EEAR2 2
|
||
EEARL.EEAR1 1
|
||
EEARL.EEAR0 0
|
||
EEARH 0x001F EEPROM Address Register High
|
||
EEARH.EEAR8 8
|
||
RESERVED0020 0x0020 RESERVED
|
||
WDTCR 0x0021 Watchdog Timer Control Register
|
||
WDTCR.WDTOE 4 Watchdog Turn-off Enable
|
||
WDTCR.WDE 3 Watchdog Enable
|
||
WDTCR.WDP2 2 Watchdog Timer Prescaler 2
|
||
WDTCR.WDP1 1 Watchdog Timer Prescaler 1
|
||
WDTCR.WDP0 0 Watchdog Timer Prescaler 0
|
||
RESERVED0022 0x0022 RESERVED
|
||
RESERVED0023 0x0023 RESERVED
|
||
ICR1L 0x0024 Timer/Counter1 Input Capture Register Low
|
||
ICR1H 0x0025 Timer/Counter1 Input Capture Register High
|
||
RESERVED0026 0x0026 RESERVED
|
||
RESERVED0027 0x0027 RESERVED
|
||
OCR1BL 0x0028 Timer/Counter1 Output Compare Register Low
|
||
OCR1BH 0x0029 Timer/Counter1 Output Compare Register High
|
||
OCR1AL 0x002A Timer/Counter1 Output Compare Register Low
|
||
OCR1AH 0x002B Timer/Counter1 Output Compare Register High
|
||
TCNT1L 0x002C Timer/Counter1 Low
|
||
TCNT1H 0x002D Timer/Counter1 High
|
||
TCCR1B 0x002E Timer/Counter1 Control Register B
|
||
TCCR1B.ICNC1 7 Input Capture1 Noise Canceler (4 CKs)
|
||
TCCR1B.ICES1 6 Input Capture1 Edge Select
|
||
TCCR1B.CTC1 3 Clear Timer/Counter1 on Compare Match
|
||
TCCR1B.CS12 2 Clock Select1, Bit 2
|
||
TCCR1B.CS11 1 Clock Select1, Bit 1
|
||
TCCR1B.CS10 0 Clock Select1, Bit 0
|
||
TCCR1A 0x002F Timer/Counter1 Control Register A
|
||
TCCR1A.COM1A1 7 Compare Output Mode1A, Bit 1
|
||
TCCR1A.COM1A0 6 Compare Output Mode1A, Bit 0
|
||
TCCR1A.COM1B1 5 Compare Output Mode1B, Bit 1
|
||
TCCR1A.COM1B0 4 Compare Output Mode1B, Bit 0
|
||
TCCR1A.PWM11 1 Pulse Width Modulator Select Bit 1
|
||
TCCR1A.PWM10 0 Pulse Width Modulator Select Bit 0
|
||
RESERVED0030 0x0030 RESERVED
|
||
RESERVED0031 0x0031 RESERVED
|
||
TCNT0 0x0032 Timer Counter0
|
||
TCCR0 0x0033 Timer/Counter0 Control Register
|
||
TCCR0.CS02 2 Clock Select0, Bit 2
|
||
TCCR0.CS01 1 Clock Select0, Bit 1
|
||
TCCR0.CS00 0 Clock Select0, Bit 0
|
||
RESERVED0034 0x0034 RESERVED
|
||
MCUCR 0x0035 MCU Control Register
|
||
MCUCR.SRE 7 External SRAM Enable
|
||
MCUCR.SRW 6 External SRAM Wait State
|
||
MCUCR.SE 5 Sleep Enable
|
||
MCUCR.SM 4 Sleep Mode
|
||
MCUCR.ISC11 3 Interrupt Sense Control 1, Bit 1
|
||
MCUCR.ISC10 2 Interrupt Sense Control 1, Bit
|
||
MCUCR.ISC01 1 Interrupt Sense Control 0, Bit 1
|
||
MCUCR.ISC00 0 Interrupt Sense Control 0, Bit 0
|
||
RESERVED0036 0x0036 RESERVED
|
||
RESERVED0037 0x0037 RESERVED
|
||
TIFR 0x0038 Timer/Counter Interrupt Flag Register
|
||
TIFR.TOV1 7 Timer/Counter1 Overflow Flag
|
||
TIFR.OCF1A 6 Output Compare Flag 1A
|
||
TIFR.OCIFB 5 Output Compare Flag 1B
|
||
TIFR.ICF1 3 Input Capture Flag 1
|
||
TIFR.TOV0 1 Timer/Counter0 Overflow Flag
|
||
TIMSK 0x0039 Timer/Counter Interrupt Mask Register
|
||
TIMSK.TOIE1 7 Timer/Counter1 Overflow Interrupt Enable
|
||
TIMSK.OCIE1A 6 Timer/Counter1 Output CompareA Match Interrupt Enable
|
||
TIMSK.OCIE1B 5 Timer/Counter1 Output CompareB Match Interrupt Enable
|
||
TIMSK.TICIE1 3 Timer/Counter1 Input Capture Interrupt Enable
|
||
TIMSK.TOIE0 1 Timer/Counter0 Overflow Interrupt Enable
|
||
GIFR 0x003A General Interrupt Flag Register
|
||
GIFR.INTF1 7 External Interrupt Flag1
|
||
GIFR.INTF0 6 External Interrupt Flag0
|
||
GIMSK 0x003B General Interrupt Mask Register
|
||
GIMSK.INT1 7 External Interrupt Request 1 Enable
|
||
GIMSK.INT0 6 External Interrupt Request 0 Enable
|
||
RESERVED003C 0x003C RESERVED
|
||
SPL 0x003D Stack Pointer Low
|
||
SPL.SP7 7
|
||
SPL.SP6 6
|
||
SPL.SP5 5
|
||
SPL.SP4 4
|
||
SPL.SP3 3
|
||
SPL.SP2 2
|
||
SPL.SP1 1
|
||
SPL.SP0 0
|
||
SPH 0x003E Stack Pointer High
|
||
SPH.SP15 15
|
||
SPH.SP14 14
|
||
SPH.SP13 13
|
||
SPH.SP12 12
|
||
SPH.SP11 11
|
||
SPH.SP10 10
|
||
SPH.SP9 9
|
||
SPH.SP8 8
|
||
SREG 0x003F Status Register
|
||
SREG.I 7 Global Interrupt Enable
|
||
SREG.T 6 Bit Copy Storage
|
||
SREG.H 5 Half-carry Flag
|
||
SREG.S 4 Sign Bit
|
||
SREG.V 3 Two's Complement Overflow Flag
|
||
SREG.N 2 Negative Flag
|
||
SREG.Z 1 Zero Flag
|
||
SREG.C 0 Carry Flag
|
||
|
||
|
||
; RESERVED0020 0x0020 RESERVED
|
||
; RESERVED0021 0x0021 RESERVED
|
||
; RESERVED0022 0x0022 RESERVED
|
||
; RESERVED0023 0x0023 RESERVED
|
||
; RESERVED0024 0x0024 RESERVED
|
||
; RESERVED0025 0x0025 RESERVED
|
||
; RESERVED0026 0x0026 RESERVED
|
||
; RESERVED0027 0x0027 RESERVED
|
||
; ACSR 0x0028 Analog Comparator Control and Status Register
|
||
; ACSR.ACD 7 Analog Comparator Disable
|
||
; ACSR.ACO 5 Analog Comparator Output
|
||
; ACSR.ACI 4 Analog Comparator Interrupt Flag
|
||
; ACSR.ACIE 3 Analog Comparator Interrupt Enable
|
||
; ACSR.ACIC 2 Analog Comparator Input Capture Enable
|
||
; ACSR.ACIS1 1 Analog Comparator Interrupt Mode Select 1
|
||
; ACSR.ACIS0 0 Analog Comparator Interrupt Mode Select 0
|
||
; UBRR 0x0029 UART BAUD Rate Register
|
||
; UCR 0x002A UART Control Register
|
||
; UCR.RXCIE 7 RX Complete Interrupt Enable
|
||
; UCR.TXCIE 6 TX Complete Interrupt Enable
|
||
; UCR.UDRIE 5 UART Data Register Empty Interrupt Enable
|
||
; UCR.RXEN 4 Receiver Enable
|
||
; UCR.TXEN 3 Transmitter Enable
|
||
; UCR.CHR9 2 9-bit Characters
|
||
; UCR.RXB8 1 Receive Data Bit 8
|
||
; UCR.TXB8 0 Transmit Data Bit 8
|
||
; USR 0x002B UART Status Register
|
||
; USR.RXC 7 UART Receive Complete
|
||
; USR.TXC 6 UART Transmit Complete
|
||
; USR.UDRE 5 UART Data Register Empty
|
||
; USR.FE 4 Framing Error
|
||
; USR.OR 3 Overrun
|
||
; UDR 0x002C UART I/O Data Register
|
||
; SPCR 0x002D SPI Control Register
|
||
; SPCR.SPIE 7 SPI Interrupt Enable
|
||
; SPCR.SPE 6 SPI Enable
|
||
; SPCR.DORD 5 Data Order
|
||
; SPCR.MSTR 4 Master/Slave Select
|
||
; SPCR.CPOL 3 Clock Polarity
|
||
; SPCR.CPHA 2 Clock Phase
|
||
; SPCR.SPR1 1 SPI Clock Rate Select 1
|
||
; SPCR.SPR0 0 SPI Clock Rate Select 0
|
||
; SPSR 0x002E SPI Status Register
|
||
; SPSR.SPIF 7 SPI Interrupt Flag
|
||
; SPSR.WCOL 6 Write Collision Flag
|
||
; SPDR 0x002F SPI Data Register
|
||
; PIND 0x0030 Port D Input Pins Address
|
||
; PIND.PIND7 7
|
||
; PIND.PIND6 6
|
||
; PIND.PIND5 5
|
||
; PIND.PIND4 4
|
||
; PIND.PIND3 3
|
||
; PIND.PIND2 2
|
||
; PIND.PIND1 1
|
||
; PIND.PIND0 0
|
||
; DDRD 0x0031 Port D Data Direction Register
|
||
; DDRD.DDD7 7 Port D Data Direction Register bit 7
|
||
; DDRD.DDD6 6 Port D Data Direction Register bit 6
|
||
; DDRD.DDD5 5 Port D Data Direction Register bit 5
|
||
; DDRD.DDD4 4 Port D Data Direction Register bit 4
|
||
; DDRD.DDD3 3 Port D Data Direction Register bit 3
|
||
; DDRD.DDD2 2 Port D Data Direction Register bit 2
|
||
; DDRD.DDD1 1 Port D Data Direction Register bit 1
|
||
; DDRD.DDD0 0 Port D Data Direction Register bit 0
|
||
; PORTD 0x0032 Port D Data Register
|
||
; PORTD.PORTD7 7 Port D Data Register bit 7
|
||
; PORTD.PORTD6 6 Port D Data Register bit 6
|
||
; PORTD.PORTD5 5 Port D Data Register bit 5
|
||
; PORTD.PORTD4 4 Port D Data Register bit 4
|
||
; PORTD.PORTD3 3 Port D Data Register bit 3
|
||
; PORTD.PORTD2 2 Port D Data Register bit 2
|
||
; PORTD.PORTD1 1 Port D Data Register bit 1
|
||
; PORTD.PORTD0 0 Port D Data Register bit 0
|
||
; PINC 0x0033 Port C Input Pins Address
|
||
; PINC.PINC7 7
|
||
; PINC.PINC6 6
|
||
; PINC.PINC5 5
|
||
; PINC.PINC4 4
|
||
; PINC.PINC3 3
|
||
; PINC.PINC2 2
|
||
; PINC.PINC1 1
|
||
; PINC.PINC0 0
|
||
; DDRC 0x0034 Port C Data Direction Register
|
||
; DDRC.DDC7 7 Port C Data Direction Register bit 7
|
||
; DDRC.DDC6 6 Port C Data Direction Register bit 6
|
||
; DDRC.DDC5 5 Port C Data Direction Register bit 5
|
||
; DDRC.DDC4 4 Port C Data Direction Register bit 4
|
||
; DDRC.DDC3 3 Port C Data Direction Register bit 3
|
||
; DDRC.DDC2 2 Port C Data Direction Register bit 2
|
||
; DDRC.DDC1 1 Port C Data Direction Register bit 1
|
||
; DDRC.DDC0 0 Port C Data Direction Register bit 0
|
||
; PORTC 0x0035 Port C Data Register
|
||
; PORTC.PORTC7 7 Port C Data Register bit 7
|
||
; PORTC.PORTC6 6 Port C Data Register bit 6
|
||
; PORTC.PORTC5 5 Port C Data Register bit 5
|
||
; PORTC.PORTC4 4 Port C Data Register bit 4
|
||
; PORTC.PORTC3 3 Port C Data Register bit 3
|
||
; PORTC.PORTC2 2 Port C Data Register bit 2
|
||
; PORTC.PORTC1 1 Port C Data Register bit 1
|
||
; PORTC.PORTC0 0 Port C Data Register bit 0
|
||
; PINB 0x0036 Port B Input Pins Address
|
||
; PINB.PINB7 7
|
||
; PINB.PINB6 6
|
||
; PINB.PINB5 5
|
||
; PINB.PINB4 4
|
||
; PINB.PINB3 3
|
||
; PINB.PINB2 2
|
||
; PINB.PINB1 1
|
||
; PINB.PINB0 0
|
||
; DDRB 0x0037 Port B Data Direction Register
|
||
; DDRB.DDB7 7 Port B Data Direction Register bit 7
|
||
; DDRB.DDB6 6 Port B Data Direction Register bit 6
|
||
; DDRB.DDB5 5 Port B Data Direction Register bit 5
|
||
; DDRB.DDB4 4 Port B Data Direction Register bit 4
|
||
; DDRB.DDB3 3 Port B Data Direction Register bit 3
|
||
; DDRB.DDB2 2 Port B Data Direction Register bit 2
|
||
; DDRB.DDB1 1 Port B Data Direction Register bit 1
|
||
; DDRB.DDB0 0 Port B Data Direction Register bit 0
|
||
; PORTB 0x0038 Port B Data Register
|
||
; PORTB.PORTB7 7 Port B Data Register bit 7
|
||
; PORTB.PORTB6 6 Port B Data Register bit 6
|
||
; PORTB.PORTB5 5 Port B Data Register bit 5
|
||
; PORTB.PORTB4 4 Port B Data Register bit 4
|
||
; PORTB.PORTB3 3 Port B Data Register bit 3
|
||
; PORTB.PORTB2 2 Port B Data Register bit 2
|
||
; PORTB.PORTB1 1 Port B Data Register bit 1
|
||
; PORTB.PORTB0 0 Port B Data Register bit 0
|
||
; PINA 0x0039 Port A Input Pins Address
|
||
; PINA.PINA7 7
|
||
; PINA.PINA6 6
|
||
; PINA.PINA5 5
|
||
; PINA.PINA4 4
|
||
; PINA.PINA3 3
|
||
; PINA.PINA2 2
|
||
; PINA.PINA1 1
|
||
; PINA.PINA0 0
|
||
; DDRA 0x003A Port A Data Direction Register
|
||
; DDRA.DDA7 7 Port A Data Direction Register bit 7
|
||
; DDRA.DDA6 6 Port A Data Direction Register bit 6
|
||
; DDRA.DDA5 5 Port A Data Direction Register bit 5
|
||
; DDRA.DDA4 4 Port A Data Direction Register bit 4
|
||
; DDRA.DDA3 3 Port A Data Direction Register bit 3
|
||
; DDRA.DDA2 2 Port A Data Direction Register bit 2
|
||
; DDRA.DDA1 1 Port A Data Direction Register bit 1
|
||
; DDRA.DDA0 0 Port A Data Direction Register bit 0
|
||
; PORTA 0x003B Port A Data Register
|
||
; PORTA.PORTA7 7 Port A Data Register bit 7
|
||
; PORTA.PORTA6 6 Port A Data Register bit 6
|
||
; PORTA.PORTA5 5 Port A Data Register bit 5
|
||
; PORTA.PORTA4 4 Port A Data Register bit 4
|
||
; PORTA.PORTA3 3 Port A Data Register bit 3
|
||
; PORTA.PORTA2 2 Port A Data Register bit 2
|
||
; PORTA.PORTA1 1 Port A Data Register bit 1
|
||
; PORTA.PORTA0 0 Port A Data Register bit 0
|
||
; EECR 0x003C EEPROM Control Register
|
||
; EECR.EEMWE 2 EEPROM Master Write Enable
|
||
; EECR.EEWE 1 EEPROM Write Enable
|
||
; EECR.EERE 0 EEPROM Read Enable
|
||
; EEDR 0x003D EEPROM Data Register
|
||
; EEARL 0x003E EEPROM Address Register Low
|
||
; EEARL.EEAR7 7
|
||
; EEARL.EEAR6 6
|
||
; EEARL.EEAR5 5
|
||
; EEARL.EEAR4 4
|
||
; EEARL.EEAR3 3
|
||
; EEARL.EEAR2 2
|
||
; EEARL.EEAR1 1
|
||
; EEARL.EEAR0 0
|
||
; EEARH 0x003F EEPROM Address Register High
|
||
; EEARH.EEAR8 8
|
||
; RESERVED0040 0x0040 RESERVED
|
||
; WDTCR 0x0041 Watchdog Timer Control Register
|
||
; WDTCR.WDTOE 4 Watchdog Turn-off Enable
|
||
; WDTCR.WDE 3 Watchdog Enable
|
||
; WDTCR.WDP2 2 Watchdog Timer Prescaler 2
|
||
; WDTCR.WDP1 1 Watchdog Timer Prescaler 1
|
||
; WDTCR.WDP0 0 Watchdog Timer Prescaler 0
|
||
; RESERVED0042 0x0042 RESERVED
|
||
; RESERVED0043 0x0043 RESERVED
|
||
; ICR1L 0x0044 Timer/Counter1 Input Capture Register Low
|
||
; ICR1H 0x0045 Timer/Counter1 Input Capture Register High
|
||
; RESERVED0046 0x0046 RESERVED
|
||
; RESERVED0047 0x0047 RESERVED
|
||
; OCR1BL 0x0048 Timer/Counter1 Output Compare Register Low
|
||
; OCR1BH 0x0049 Timer/Counter1 Output Compare Register High
|
||
; OCR1AL 0x004A Timer/Counter1 Output Compare Register Low
|
||
; OCR1AH 0x004B Timer/Counter1 Output Compare Register High
|
||
; TCNT1L 0x004C Timer/Counter1 Low
|
||
; TCNT1H 0x004D Timer/Counter1 High
|
||
; TCCR1B 0x004E Timer/Counter1 Control Register B
|
||
; TCCR1B.ICNC1 7 Input Capture1 Noise Canceler (4 CKs)
|
||
; TCCR1B.ICES1 6 Input Capture1 Edge Select
|
||
; TCCR1B.CTC1 3 Clear Timer/Counter1 on Compare Match
|
||
; TCCR1B.CS12 2 Clock Select1, Bit 2
|
||
; TCCR1B.CS11 1 Clock Select1, Bit 1
|
||
; TCCR1B.CS10 0 Clock Select1, Bit 0
|
||
; TCCR1A 0x004F Timer/Counter1 Control Register A
|
||
; TCCR1A.COM1A1 7 Compare Output Mode1A, Bit 1
|
||
; TCCR1A.COM1A0 6 Compare Output Mode1A, Bit 0
|
||
; TCCR1A.COM1B1 5 Compare Output Mode1B, Bit 1
|
||
; TCCR1A.COM1B0 4 Compare Output Mode1B, Bit 0
|
||
; TCCR1A.PWM11 1 Pulse Width Modulator Select Bit 1
|
||
; TCCR1A.PWM10 0 Pulse Width Modulator Select Bit 0
|
||
; RESERVED0050 0x0050 RESERVED
|
||
; RESERVED0051 0x0051 RESERVED
|
||
; TCNT0 0x0052 Timer Counter0
|
||
; TCCR0 0x0053 Timer/Counter0 Control Register
|
||
; TCCR0.CS02 2 Clock Select0, Bit 2
|
||
; TCCR0.CS01 1 Clock Select0, Bit 1
|
||
; TCCR0.CS00 0 Clock Select0, Bit 0
|
||
; RESERVED0054 0x0054 RESERVED
|
||
; MCUCR 0x0055 MCU Control Register
|
||
; MCUCR.SRE 7 External SRAM Enable
|
||
; MCUCR.SRW 6 External SRAM Wait State
|
||
; MCUCR.SE 5 Sleep Enable
|
||
; MCUCR.SM 4 Sleep Mode
|
||
; MCUCR.ISC11 3 Interrupt Sense Control 1, Bit 1
|
||
; MCUCR.ISC10 2 Interrupt Sense Control 1, Bit
|
||
; MCUCR.ISC01 1 Interrupt Sense Control 0, Bit 1
|
||
; MCUCR.ISC00 0 Interrupt Sense Control 0, Bit 0
|
||
; RESERVED0056 0x0056 RESERVED
|
||
; RESERVED0057 0x0057 RESERVED
|
||
; TIFR 0x0058 Timer/Counter Interrupt Flag Register
|
||
; TIFR.TOV1 7 Timer/Counter1 Overflow Flag
|
||
; TIFR.OCF1A 6 Output Compare Flag 1A
|
||
; TIFR.OCIFB 5 Output Compare Flag 1B
|
||
; TIFR.ICF1 3 Input Capture Flag 1
|
||
; TIFR.TOV0 1 Timer/Counter0 Overflow Flag
|
||
; TIMSK 0x0059 Timer/Counter Interrupt Mask Register
|
||
; TIMSK.TOIE1 7 Timer/Counter1 Overflow Interrupt Enable
|
||
; TIMSK.OCIE1A 6 Timer/Counter1 Output CompareA Match Interrupt Enable
|
||
; TIMSK.OCIE1B 5 Timer/Counter1 Output CompareB Match Interrupt Enable
|
||
; TIMSK.TICIE1 3 Timer/Counter1 Input Capture Interrupt Enable
|
||
; TIMSK.TOIE0 1 Timer/Counter0 Overflow Interrupt Enable
|
||
; GIFR 0x005A General Interrupt Flag Register
|
||
; GIFR.INTF1 7 External Interrupt Flag1
|
||
; GIFR.INTF0 6 External Interrupt Flag0
|
||
; GIMSK 0x005B General Interrupt Mask Register
|
||
; GIMSK.INT1 7 External Interrupt Request 1 Enable
|
||
; GIMSK.INT0 6 External Interrupt Request 0 Enable
|
||
; RESERVED005C 0x005C RESERVED
|
||
; SPL 0x005D Stack Pointer Low
|
||
; SPL.SP7 7
|
||
; SPL.SP6 6
|
||
; SPL.SP5 5
|
||
; SPL.SP4 4
|
||
; SPL.SP3 3
|
||
; SPL.SP2 2
|
||
; SPL.SP1 1
|
||
; SPL.SP0 0
|
||
; SPH 0x005E Stack Pointer High
|
||
; SPH.SP15 15
|
||
; SPH.SP14 14
|
||
; SPH.SP13 13
|
||
; SPH.SP12 12
|
||
; SPH.SP11 11
|
||
; SPH.SP10 10
|
||
; SPH.SP9 9
|
||
; SPH.SP8 8
|
||
; SREG 0x005F Status Register
|
||
; SREG.I 7 Global Interrupt Enable
|
||
; SREG.T 6 Bit Copy Storage
|
||
; SREG.H 5 Half-carry Flag
|
||
; SREG.S 4 Sign Bit
|
||
; SREG.V 3 Two's Complement Overflow Flag
|
||
; SREG.N 2 Negative Flag
|
||
; SREG.Z 1 Zero Flag
|
||
; SREG.C 0 Carry Flag
|
||
|
||
|
||
.AT90S_L4433
|
||
SUBARCH=2
|
||
; doc1042.pdf
|
||
;
|
||
|
||
RAM=128
|
||
ROM=4096
|
||
EEPROM=256
|
||
|
||
|
||
; MEMORY MAP
|
||
area DATA GPWR_ 0x0000:0x0020 General Purpose Working Registers
|
||
area DATA FSR_ 0x0020:0x0080 I/O registers
|
||
area DATA SRAM_ 0x0080:0x00E0 SRAM
|
||
|
||
|
||
; Interrupt and reset vector assignments
|
||
entry __RESET 0x0000 External Pin, Power-on Reset, Brown-out Reset and Watchdog Reset
|
||
entry INT0_ 0x0001 External Interrupt Request 0
|
||
entry INT1_ 0x0002 External Interrupt Request 1
|
||
entry TIMER1_CAPT 0x0003 Timer/Counter1 Capture Event
|
||
entry TIMER1_COMP 0x0004 Timer/Counter1 Compare Match
|
||
entry TIMER1_OVF 0x0005 Timer/Counter1 Overflow
|
||
entry TIMER0_OVF 0x0006 Timer/Counter0 Overflow
|
||
entry SPI_STC 0x0007 Serial Transfer Complete
|
||
entry UART_RX 0x0008 UART, Rx Complete
|
||
entry UART_UDRE 0x0009 UART Data Register Empty
|
||
entry UART_TX 0x000A UART, Tx Complete
|
||
entry ADC_ 0x000B ADC Conversion Complete
|
||
entry EE_RDY 0x000C EEPROM Ready
|
||
entry ANA_COMP 0x000D Analog Comparator
|
||
|
||
|
||
; INPUT/OUTPUT PORTS
|
||
RESERVED0000 0x0000 RESERVED
|
||
RESERVED0001 0x0001 RESERVED
|
||
RESERVED0002 0x0002 RESERVED
|
||
UBRRHI 0x0003 UART Baud Rate Register High
|
||
ADCL 0x0004 ADC Data Register low
|
||
ADCL.ADC7 7
|
||
ADCL.ADC6 6
|
||
ADCL.ADC5 5
|
||
ADCL.ADC4 4
|
||
ADCL.ADC3 3
|
||
ADCL.ADC2 2
|
||
ADCL.ADC1 1
|
||
ADCL.ADC0 0
|
||
ADCH 0x0005 ADC Data Register high
|
||
ADCH.ADC9 9
|
||
ADCH.ADC8 8
|
||
ADCSR 0x0006 ADC Control and Status Register
|
||
ADCSR.ADEN 7 ADC Enable
|
||
ADCSR.ADSC 6 ADC Start Conversion
|
||
ADCSR.ADFR 5 ADC Free Run Select
|
||
ADCSR.ADIF 4 ADC Interrupt Flag
|
||
ADCSR.ADIE 3 ADC Interrupt Enable
|
||
ADCSR.ADPS2 2 ADC Prescaler Select Bit 2
|
||
ADCSR.ADPS1 1 ADC Prescaler Select Bit 1
|
||
ADCSR.ADPS0 0 ADC Prescaler Select Bit 0
|
||
ADMUX 0x0007 ADC Multiplexer Select Register
|
||
ADMUX.ADCBG 6 ADC Bandgap Select
|
||
ADMUX.MUX2 2 Analog Channel Select Bit 2
|
||
ADMUX.MUX1 1 Analog Channel Select Bit 1
|
||
ADMUX.MUX0 0 Analog Channel Select Bit 0
|
||
ACSR 0x0008 Analog Comparator Control and Status Register
|
||
ACSR.ACD 7 Analog Comparator Disable
|
||
ACSR.AINBG 6 Analog Comparator Bandgap Select
|
||
ACSR.ACO 5 Analog Comparator Output
|
||
ACSR.ACI 4 Analog Comparator Interrupt Flag
|
||
ACSR.ACIE 3 Analog Comparator Interrupt Enable
|
||
ACSR.ACIC 2 Analog Comparator Input Capture Enable
|
||
ACSR.ACIS1 1 Analog Comparator Interrupt Mode Select 1
|
||
ACSR.ACIS0 0 Analog Comparator Interrupt Mode Select 0
|
||
UBRR 0x0009 UART Baud Rate Register Low
|
||
UCSRB 0x000A UART Control and Status Register
|
||
UCSRB.RXCIE 7 RX Complete Interrupt Enable
|
||
UCSRB.TXCIE 6 TX Complete Interrupt Enable
|
||
UCSRB.UDRIE 5 UART Data Register Empty Interrupt Enable
|
||
UCSRB.RXEN 4 Receiver Enable
|
||
UCSRB.TXEN 3 Transmitter Enable
|
||
UCSRB.CHR9 2 9-bit Characters
|
||
UCSRB.RXB8 1 Receive Data Bit 8
|
||
UCSRB.TXB8 0 Transmit Data Bit 8
|
||
UCSRA 0x000B UART Control and Status Register A
|
||
UCSRA.RXC 7 UART Receive Complete
|
||
UCSRA.TXC 6 UART Transmit Complete
|
||
UCSRA.UDRE 5 UART Data Register Empty
|
||
UCSRA.FE 4 Framing Error
|
||
UCSRA.OR 3 OverRun
|
||
UCSRA.MPCM 0 Multi-processor Communication Mode
|
||
UDR 0x000C UART I/O Data Register
|
||
SPCR 0x000D SPI Control Register
|
||
SPCR.SPIE 7 SPI Interrupt Enable
|
||
SPCR.SPE 6 SPI Enable
|
||
SPCR.DORD 5 Data Order
|
||
SPCR.MSTR 4 Master/Slave Select
|
||
SPCR.CPOL 3 Clock Polarity
|
||
SPCR.CPHA 2 Clock Phase
|
||
SPCR.SPR1 1 SPI Clock Rate Select 1
|
||
SPCR.SPR0 0 SPI Clock Rate Select 0
|
||
SPSR 0x000E SPI Status Register
|
||
SPSR.SPIF 7 SPI Interrupt Flag
|
||
SPSR.WCOL 6 Write Collision Flag
|
||
SPDR 0x000F SPI Data Register
|
||
PIND 0x0010 Port D Input Pins Address
|
||
PIND.PIND7 7
|
||
PIND.PIND6 6
|
||
PIND.PIND5 5
|
||
PIND.PIND4 4
|
||
PIND.PIND3 3
|
||
PIND.PIND2 2
|
||
PIND.PIND1 1
|
||
PIND.PIND0 0
|
||
DDRD 0x0011 Port D Data Direction Register
|
||
DDRD.DDD7 7 Port D Data Direction Register bit 7
|
||
DDRD.DDD6 6 Port D Data Direction Register bit 6
|
||
DDRD.DDD5 5 Port D Data Direction Register bit 5
|
||
DDRD.DDD4 4 Port D Data Direction Register bit 4
|
||
DDRD.DDD3 3 Port D Data Direction Register bit 3
|
||
DDRD.DDD2 2 Port D Data Direction Register bit 2
|
||
DDRD.DDD1 1 Port D Data Direction Register bit 1
|
||
DDRD.DDD0 0 Port D Data Direction Register bit 0
|
||
PORTD 0x0012 Port D Data Register
|
||
PORTD.PORTD7 7 Port D Data Register bit 7
|
||
PORTD.PORTD6 6 Port D Data Register bit 6
|
||
PORTD.PORTD5 5 Port D Data Register bit 5
|
||
PORTD.PORTD4 4 Port D Data Register bit 4
|
||
PORTD.PORTD3 3 Port D Data Register bit 3
|
||
PORTD.PORTD2 2 Port D Data Register bit 2
|
||
PORTD.PORTD1 1 Port D Data Register bit 1
|
||
PORTD.PORTD0 0 Port D Data Register bit 0
|
||
PINC 0x0013 Port C Input Pins Address
|
||
PINC.PINC5 5
|
||
PINC.PINC4 4
|
||
PINC.PINC3 3
|
||
PINC.PINC2 2
|
||
PINC.PINC1 1
|
||
PINC.PINC0 0
|
||
DDRC 0x0014 Port C Data Direction Register
|
||
DDRC.DDC5 5 Port C Data Direction Register bit 5
|
||
DDRC.DDC4 4 Port C Data Direction Register bit 4
|
||
DDRC.DDC3 3 Port C Data Direction Register bit 3
|
||
DDRC.DDC2 2 Port C Data Direction Register bit 2
|
||
DDRC.DDC1 1 Port C Data Direction Register bit 1
|
||
DDRC.DDC0 0 Port C Data Direction Register bit 0
|
||
PORTC 0x0015 Port C Data Register
|
||
PORTC.PORTC5 5 Port C Data Register bit 5
|
||
PORTC.PORTC4 4 Port C Data Register bit 4
|
||
PORTC.PORTC3 3 Port C Data Register bit 3
|
||
PORTC.PORTC2 2 Port C Data Register bit 2
|
||
PORTC.PORTC1 1 Port C Data Register bit 1
|
||
PORTC.PORTC0 0 Port C Data Register bit 0
|
||
PINB 0x0016 Port B Input Pins Address
|
||
PINB.PINB5 5
|
||
PINB.PINB4 4
|
||
PINB.PINB3 3
|
||
PINB.PINB2 2
|
||
PINB.PINB1 1
|
||
PINB.PINB0 0
|
||
DDRB 0x0017 Port B Data Direction Register
|
||
DDRB.DDB5 5 Port B Data Direction Register bit 5
|
||
DDRB.DDB4 4 Port B Data Direction Register bit 4
|
||
DDRB.DDB3 3 Port B Data Direction Register bit 3
|
||
DDRB.DDB2 2 Port B Data Direction Register bit 2
|
||
DDRB.DDB1 1 Port B Data Direction Register bit 1
|
||
DDRB.DDB0 0 Port B Data Direction Register bit 0
|
||
PORTB 0x0018 Port B Data Register
|
||
PORTB.PORTB5 5 Port B Data Register bit 5
|
||
PORTB.PORTB4 4 Port B Data Register bit 4
|
||
PORTB.PORTB3 3 Port B Data Register bit 3
|
||
PORTB.PORTB2 2 Port B Data Register bit 2
|
||
PORTB.PORTB1 1 Port B Data Register bit 1
|
||
PORTB.PORTB0 0 Port B Data Register bit 0
|
||
RESERVED0019 0x0019 RESERVED
|
||
RESERVED001A 0x001A RESERVED
|
||
RESERVED001B 0x001B RESERVED
|
||
EECR 0x001C EEPROM Control Register
|
||
EECR.EERIE 3 EEPROM Ready Interrupt Enable
|
||
EECR.EEMWE 2 EEPROM Master Write Enable
|
||
EECR.EEWE 1 EEPROM Write Enable
|
||
EECR.EERE 0 EEPROM Read Enable
|
||
EEDR 0x001D EEPROM Data Register
|
||
EEAR 0x001E EEPROM Address Register
|
||
EEAR.EEAR7 7
|
||
EEAR.EEAR6 6
|
||
EEAR.EEAR5 5
|
||
EEAR.EEAR4 4
|
||
EEAR.EEAR3 3
|
||
EEAR.EEAR2 2
|
||
EEAR.EEAR1 1
|
||
EEAR.EEAR0 0
|
||
RESERVED001F 0x001F RESERVED
|
||
RESERVED0020 0x0020 RESERVED
|
||
WDTCR 0x0021 Watchdog Timer Control Register
|
||
WDTCR.WDTOE 4 Watchdog Turn-off Enable
|
||
WDTCR.WDE 3 Watchdog Enable
|
||
WDTCR.WDP2 2 Watchdog Timer Prescaler 2
|
||
WDTCR.WDP1 1 Watchdog Timer Prescaler 1
|
||
WDTCR.WDP0 0 Watchdog Timer Prescaler 0
|
||
RESERVED0022 0x0022 RESERVED
|
||
RESERVED0023 0x0023 RESERVED
|
||
RESERVED0024 0x0024 RESERVED
|
||
RESERVED0025 0x0025 RESERVED
|
||
ICR1L 0x0026 Timer/Counter1 Input Capture Register Low
|
||
ICR1H 0x0027 Timer/Counter1 Input Capture Register High
|
||
RESERVED0028 0x0028 RESERVED
|
||
RESERVED0029 0x0029 RESERVED
|
||
OCR1L 0x002A Timer/Counter1 Output Compare Register Low
|
||
OCR1H 0x002B Timer/Counter1 Output Compare Register High
|
||
TCNT1L 0x002C Timer/Counter1 Low
|
||
TCNT1H 0x002D Timer/Counter1 High
|
||
TCCR1B 0x002E Timer/Counter1 Control Register B
|
||
TCCR1B.ICNC1 7 Input Capture1 Noise Canceler (4 CKs)
|
||
TCCR1B.ICES1 6 Input Capture1 Edge Select
|
||
TCCR1B.CTC1 3 Clear Timer/Counter1 on Compare Match
|
||
TCCR1B.CS12 2 Clock Select1 Bit 2
|
||
TCCR1B.CS11 1 Clock Select1 Bit 1
|
||
TCCR1B.CS10 0 Clock Select1 Bit 0
|
||
TCCR1A 0x002F Timer/Counter1 Control Register A
|
||
TCCR1A.COM11 7 Compare Output Mode1, Bit 1
|
||
TCCR1A.COM10 6 Compare Output Mode1, Bit 0
|
||
TCCR1A.PWM11 1 Pulse Width Modulator Select Bit 1
|
||
TCCR1A.PWM10 0 Pulse Width Modulator Select Bit 0
|
||
RESERVED0030 0x0030 RESERVED
|
||
RESERVED0031 0x0031 RESERVED
|
||
TCNT0 0x0032 Timer Counter 0
|
||
TCCR0 0x0033 Timer/Counter 0 Control Register
|
||
TCCR0.CS02 2 Clock Select0, Bit 2
|
||
TCCR0.CS01 1 Clock Select0, Bit 1
|
||
TCCR0.CS00 0 Clock Select0, Bit 0
|
||
MCUSR 0x0034 MCU Status Register
|
||
MCUSR.WDRF 3 Watchdog Reset Flag
|
||
MCUSR.BORF 2 Brown-out Reset Flag
|
||
MCUSR.EXTRF 1 External Reset Flag
|
||
MCUSR.PORF 0 Power-on Reset Flag
|
||
MCUCR 0x0035 MCU Control Register
|
||
MCUCR.SE 5 Sleep Enable
|
||
MCUCR.SM 4 Sleep Mode
|
||
MCUCR.ISC11 3 Interrupt Sense Control 1 Bit 1
|
||
MCUCR.ISC10 2 Interrupt Sense Control 1 Bit 0
|
||
MCUCR.ISC01 1 Interrupt Sense Control 0 Bit 1
|
||
MCUCR.ISC00 0 Interrupt Sense Control 0 Bit 0
|
||
RESERVED0036 0x0036 RESERVED
|
||
RESERVED0037 0x0037 RESERVED
|
||
TIFR 0x0038 Timer/Counter Interrupt Flag Register
|
||
TIFR.TOV1 7 Timer/Counter 1 Overflow Flag
|
||
TIFR.OCF1 6 Output Compare Flag 1
|
||
TIFR.ICF1 3 Input Capture Flag 1
|
||
TIFR.TOV0 1 Timer/Counter 0 Overflow Flag
|
||
TIMSK 0x0039 Timer/Counter Interrupt Mask Register
|
||
TIMSK.TOIE1 7 Timer/Counter1 Overflow Interrupt Enable
|
||
TIMSK.OCIE1 6 Timer/Counter1 Output Compare Match Interrupt Enable
|
||
TIMSK.TICIE1 3 Timer/Counter1 Input Capture Interrupt Enable
|
||
TIMSK.TOIE0 1 Timer/Counter0 Overflow Interrupt Enable
|
||
GIFR 0x003A General Interrupt Flag Register
|
||
GIFR.INTF1 7 External Interrupt Flag 1
|
||
GIFR.INTF0 6 External Interrupt Flag 0
|
||
GIMSK 0x003B General Interrupt Mask Register
|
||
GIMSK.INT1 7 External Interrupt Request 1 Enable
|
||
GIMSK.INT0 6 External Interrupt Request 0 Enable
|
||
RESERVED003C 0x003C RESERVED
|
||
SP 0x003D Stack Pointer
|
||
SP.SP7 7
|
||
SP.SP6 6
|
||
SP.SP5 5
|
||
SP.SP4 4
|
||
SP.SP3 3
|
||
SP.SP2 2
|
||
SP.SP1 1
|
||
SP.SP0 0
|
||
RESERVED003E 0x003E RESERVED
|
||
SREG 0x003F Status Register
|
||
SREG.I 7 Global Interrupt Enable
|
||
SREG.T 6 Bit Copy Storage
|
||
SREG.H 5 Half-carry Flag
|
||
SREG.S 4 Sign Bit
|
||
SREG.V 3 Two's Complement Overflow Flag
|
||
SREG.N 2 Negative Flag
|
||
SREG.Z 1 Zero Flag
|
||
SREG.C 0 Carry Flag
|
||
|
||
; RESERVED0020 0x0020 RESERVED
|
||
; RESERVED0021 0x0021 RESERVED
|
||
; RESERVED0022 0x0022 RESERVED
|
||
; UBRRHI 0x0023 UART Baud Rate Register High
|
||
; ADCL 0x0024 ADC Data Register low
|
||
; ADCL.ADC7 7
|
||
; ADCL.ADC6 6
|
||
; ADCL.ADC5 5
|
||
; ADCL.ADC4 4
|
||
; ADCL.ADC3 3
|
||
; ADCL.ADC2 2
|
||
; ADCL.ADC1 1
|
||
; ADCL.ADC0 0
|
||
; ADCH 0x0025 ADC Data Register high
|
||
; ADCH.ADC8 8
|
||
; ADCH.ADC9 9
|
||
; ADCSR 0x0026 ADC Control and Status Register
|
||
; ADCSR.ADEN 7 ADC Enable
|
||
; ADCSR.ADSC 6 ADC Start Conversion
|
||
; ADCSR.ADFR 5 ADC Free Run Select
|
||
; ADCSR.ADIF 4 ADC Interrupt Flag
|
||
; ADCSR.ADIE 3 ADC Interrupt Enable
|
||
; ADCSR.ADPS2 2 ADC Prescaler Select Bit 2
|
||
; ADCSR.ADPS1 1 ADC Prescaler Select Bit 1
|
||
; ADCSR.ADPS0 0 ADC Prescaler Select Bit 0
|
||
; ADMUX 0x0027 ADC Multiplexer Select Register
|
||
; ADMUX.ADCBG 6 ADC Bandgap Select
|
||
; ADMUX.MUX2 2 Analog Channel Select Bit 2
|
||
; ADMUX.MUX1 1 Analog Channel Select Bit 1
|
||
; ADMUX.MUX0 0 Analog Channel Select Bit 0
|
||
; ACSR 0x0028 Analog Comparator Control and Status Register
|
||
; ACSR.ACD 7 Analog Comparator Disable
|
||
; ACSR.AINBG 6 Analog Comparator Bandgap Select
|
||
; ACSR.ACO 5 Analog Comparator Output
|
||
; ACSR.ACI 4 Analog Comparator Interrupt Flag
|
||
; ACSR.ACIE 3 Analog Comparator Interrupt Enable
|
||
; ACSR.ACIC 2 Analog Comparator Input Capture Enable
|
||
; ACSR.ACIS1 1 Analog Comparator Interrupt Mode Select 1
|
||
; ACSR.ACIS0 0 Analog Comparator Interrupt Mode Select 0
|
||
; UBRR 0x0029 UART Baud Rate Register Low
|
||
; UCSRB 0x002A UART Control and Status Register
|
||
; UCSRB.RXCIE 7 RX Complete Interrupt Enable
|
||
; UCSRB.TXCIE 6 TX Complete Interrupt Enable
|
||
; UCSRB.UDRIE 5 UART Data Register Empty Interrupt Enable
|
||
; UCSRB.RXEN 4 Receiver Enable
|
||
; UCSRB.TXEN 3 Transmitter Enable
|
||
; UCSRB.CHR9 2 9-bit Characters
|
||
; UCSRB.RXB8 1 Receive Data Bit 8
|
||
; UCSRB.TXB8 0 Transmit Data Bit 8
|
||
; UCSRA 0x002B UART Control and Status Register A
|
||
; UCSRA.RXC 7 UART Receive Complete
|
||
; UCSRA.TXC 6 UART Transmit Complete
|
||
; UCSRA.UDRE 5 UART Data Register Empty
|
||
; UCSRA.FE 4 Framing Error
|
||
; UCSRA.OR 3 OverRun
|
||
; UCSRA.MPCM 0 Multi-processor Communication Mode
|
||
; UDR 0x002C UART I/O Data Register
|
||
; SPCR 0x002D SPI Control Register
|
||
; SPCR.SPIE 7 SPI Interrupt Enable
|
||
; SPCR.SPE 6 SPI Enable
|
||
; SPCR.DORD 5 Data Order
|
||
; SPCR.MSTR 4 Master/Slave Select
|
||
; SPCR.CPOL 3 Clock Polarity
|
||
; SPCR.CPHA 2 Clock Phase
|
||
; SPCR.SPR1 1 SPI Clock Rate Select 1
|
||
; SPCR.SPR0 0 SPI Clock Rate Select 0
|
||
; SPSR 0x002E SPI Status Register
|
||
; SPSR.SPIF 7 SPI Interrupt Flag
|
||
; SPSR.WCOL 6 Write Collision Flag
|
||
; SPDR 0x002F SPI Data Register
|
||
; PIND 0x0030 Port D Input Pins Address
|
||
; PIND.PIND7 7
|
||
; PIND.PIND6 6
|
||
; PIND.PIND5 5
|
||
; PIND.PIND4 4
|
||
; PIND.PIND3 3
|
||
; PIND.PIND2 2
|
||
; PIND.PIND1 1
|
||
; PIND.PIND0 0
|
||
; DDRD 0x0031 Port D Data Direction Register
|
||
; DDRD.DDD7 7 Port D Data Direction Register bit 7
|
||
; DDRD.DDD6 6 Port D Data Direction Register bit 6
|
||
; DDRD.DDD5 5 Port D Data Direction Register bit 5
|
||
; DDRD.DDD4 4 Port D Data Direction Register bit 4
|
||
; DDRD.DDD3 3 Port D Data Direction Register bit 3
|
||
; DDRD.DDD2 2 Port D Data Direction Register bit 2
|
||
; DDRD.DDD1 1 Port D Data Direction Register bit 1
|
||
; DDRD.DDD0 0 Port D Data Direction Register bit 0
|
||
; PORTD 0x0032 Port D Data Register
|
||
; PORTD.PORTD7 7 Port D Data Register bit 7
|
||
; PORTD.PORTD6 6 Port D Data Register bit 6
|
||
; PORTD.PORTD5 5 Port D Data Register bit 5
|
||
; PORTD.PORTD4 4 Port D Data Register bit 4
|
||
; PORTD.PORTD3 3 Port D Data Register bit 3
|
||
; PORTD.PORTD2 2 Port D Data Register bit 2
|
||
; PORTD.PORTD1 1 Port D Data Register bit 1
|
||
; PORTD.PORTD0 0 Port D Data Register bit 0
|
||
; PINC 0x0033 Port C Input Pins Address
|
||
; PINC.PINC5 5
|
||
; PINC.PINC4 4
|
||
; PINC.PINC3 3
|
||
; PINC.PINC2 2
|
||
; PINC.PINC1 1
|
||
; PINC.PINC0 0
|
||
; DDRC 0x0034 Port C Data Direction Register
|
||
; DDRC.DDC5 5 Port C Data Direction Register bit 5
|
||
; DDRC.DDC4 4 Port C Data Direction Register bit 4
|
||
; DDRC.DDC3 3 Port C Data Direction Register bit 3
|
||
; DDRC.DDC2 2 Port C Data Direction Register bit 2
|
||
; DDRC.DDC1 1 Port C Data Direction Register bit 1
|
||
; DDRC.DDC0 0 Port C Data Direction Register bit 0
|
||
; PORTC 0x0035 Port C Data Register
|
||
; PORTC.PORTC5 5 Port C Data Register bit 5
|
||
; PORTC.PORTC4 4 Port C Data Register bit 4
|
||
; PORTC.PORTC3 3 Port C Data Register bit 3
|
||
; PORTC.PORTC2 2 Port C Data Register bit 2
|
||
; PORTC.PORTC1 1 Port C Data Register bit 1
|
||
; PORTC.PORTC0 0 Port C Data Register bit 0
|
||
; PINB 0x0036 Port B Input Pins Address
|
||
; PINB.PINB5 5
|
||
; PINB.PINB4 4
|
||
; PINB.PINB3 3
|
||
; PINB.PINB2 2
|
||
; PINB.PINB1 1
|
||
; PINB.PINB0 0
|
||
; DDRB 0x0037 Port B Data Direction Register
|
||
; DDRB.DDB5 5 Port B Data Direction Register bit 5
|
||
; DDRB.DDB4 4 Port B Data Direction Register bit 4
|
||
; DDRB.DDB3 3 Port B Data Direction Register bit 3
|
||
; DDRB.DDB2 2 Port B Data Direction Register bit 2
|
||
; DDRB.DDB1 1 Port B Data Direction Register bit 1
|
||
; DDRB.DDB0 0 Port B Data Direction Register bit 0
|
||
; PORTB 0x0038 Port B Data Register
|
||
; PORTB.PORTB5 5 Port B Data Register bit 5
|
||
; PORTB.PORTB4 4 Port B Data Register bit 4
|
||
; PORTB.PORTB3 3 Port B Data Register bit 3
|
||
; PORTB.PORTB2 2 Port B Data Register bit 2
|
||
; PORTB.PORTB1 1 Port B Data Register bit 1
|
||
; PORTB.PORTB0 0 Port B Data Register bit 0
|
||
; RESERVED0039 0x0039 RESERVED
|
||
; RESERVED003A 0x003A RESERVED
|
||
; RESERVED003B 0x003B RESERVED
|
||
; EECR 0x003C EEPROM Control Register
|
||
; EECR.EERIE 3 EEPROM Ready Interrupt Enable
|
||
; EECR.EEMWE 2 EEPROM Master Write Enable
|
||
; EECR.EEWE 1 EEPROM Write Enable
|
||
; EECR.EERE 0 EEPROM Read Enable
|
||
; EEDR 0x003D EEPROM Data Register
|
||
; EEAR 0x003E EEPROM Address Register
|
||
; EEAR.EEAR7 7
|
||
; EEAR.EEAR6 6
|
||
; EEAR.EEAR5 5
|
||
; EEAR.EEAR4 4
|
||
; EEAR.EEAR3 3
|
||
; EEAR.EEAR2 2
|
||
; EEAR.EEAR1 1
|
||
; EEAR.EEAR0 0
|
||
; RESERVED003F 0x003F RESERVED
|
||
; RESERVED0040 0x0040 RESERVED
|
||
; WDTCR 0x0041 Watchdog Timer Control Register
|
||
; WDTCR.WDTOE 4 Watchdog Turn-off Enable
|
||
; WDTCR.WDE 3 Watchdog Enable
|
||
; WDTCR.WDP2 2 Watchdog Timer Prescaler 2
|
||
; WDTCR.WDP1 1 Watchdog Timer Prescaler 1
|
||
; WDTCR.WDP0 0 Watchdog Timer Prescaler 0
|
||
; RESERVED0042 0x0042 RESERVED
|
||
; RESERVED0043 0x0043 RESERVED
|
||
; RESERVED0044 0x0044 RESERVED
|
||
; RESERVED0045 0x0045 RESERVED
|
||
; ICR1L 0x0046 Timer/Counter1 Input Capture Register Low
|
||
; ICR1H 0x0047 Timer/Counter1 Input Capture Register High
|
||
; RESERVED0048 0x0048 RESERVED
|
||
; RESERVED0049 0x0049 RESERVED
|
||
; OCR1L 0x004A Timer/Counter1 Output Compare Register Low
|
||
; OCR1H 0x004B Timer/Counter1 Output Compare Register High
|
||
; TCNT1L 0x004C Timer/Counter1 Low
|
||
; TCNT1H 0x004D Timer/Counter1 High
|
||
; TCCR1B 0x004E Timer/Counter1 Control Register B
|
||
; TCCR1B.ICNC1 7 Input Capture1 Noise Canceler (4 CKs)
|
||
; TCCR1B.ICES1 6 Input Capture1 Edge Select
|
||
; TCCR1B.CTC1 3 Clear Timer/Counter1 on Compare Match
|
||
; TCCR1B.CS12 2 Clock Select1 Bit 2
|
||
; TCCR1B.CS11 1 Clock Select1 Bit 1
|
||
; TCCR1B.CS10 0 Clock Select1 Bit 0
|
||
; TCCR1A 0x004F Timer/Counter1 Control Register A
|
||
; TCCR1A.COM11 7 Compare Output Mode1, Bit 1
|
||
; TCCR1A.COM10 6 Compare Output Mode1, Bit 0
|
||
; TCCR1A.PWM11 1 Pulse Width Modulator Select Bit 1
|
||
; TCCR1A.PWM10 0 Pulse Width Modulator Select Bit 0
|
||
; RESERVED0050 0x0050 RESERVED
|
||
; RESERVED0051 0x0051 RESERVED
|
||
; TCNT0 0x0052 Timer Counter 0
|
||
; TCCR0 0x0053 Timer/Counter 0 Control Register
|
||
; TCCR0.CS02 2 Clock Select0, Bit 2
|
||
; TCCR0.CS01 1 Clock Select0, Bit 1
|
||
; TCCR0.CS00 0 Clock Select0, Bit 0
|
||
; MCUSR 0x0054 MCU Status Register
|
||
; MCUSR.WDRF 3 Watchdog Reset Flag
|
||
; MCUSR.BORF 2 Brown-out Reset Flag
|
||
; MCUSR.EXTRF 1 External Reset Flag
|
||
; MCUSR.PORF 0 Power-on Reset Flag
|
||
; MCUCR 0x0055 MCU Control Register
|
||
; MCUCR.SE 5 Sleep Enable
|
||
; MCUCR.SM 4 Sleep Mode
|
||
; MCUCR.ISC11 3 Interrupt Sense Control 1 Bit 1
|
||
; MCUCR.ISC10 2 Interrupt Sense Control 1 Bit 0
|
||
; MCUCR.ISC01 1 Interrupt Sense Control 0 Bit 1
|
||
; MCUCR.ISC00 0 Interrupt Sense Control 0 Bit 0
|
||
; RESERVED0056 0x0056 RESERVED
|
||
; RESERVED0057 0x0057 RESERVED
|
||
; TIFR 0x0058 Timer/Counter Interrupt Flag Register
|
||
; TIFR.TOV1 7 Timer/Counter 1 Overflow Flag
|
||
; TIFR.OCF1 6 Output Compare Flag 1
|
||
; TIFR.ICF1 3 Input Capture Flag 1
|
||
; TIFR.TOV0 1 Timer/Counter 0 Overflow Flag
|
||
; TIMSK 0x0059 Timer/Counter Interrupt Mask Register
|
||
; TIMSK.TOIE1 7 Timer/Counter1 Overflow Interrupt Enable
|
||
; TIMSK.OCIE1 6 Timer/Counter1 Output Compare Match Interrupt Enable
|
||
; TIMSK.TICIE1 3 Timer/Counter1 Input Capture Interrupt Enable
|
||
; TIMSK.TOIE0 1 Timer/Counter0 Overflow Interrupt Enable
|
||
; GIFR 0x005A General Interrupt Flag Register
|
||
; GIFR.INTF1 7 External Interrupt Flag 1
|
||
; GIFR.INTF0 6 External Interrupt Flag 0
|
||
; GIMSK 0x005B General Interrupt Mask Register
|
||
; GIMSK.INT1 7 External Interrupt Request 1 Enable
|
||
; GIMSK.INT0 6 External Interrupt Request 0 Enable
|
||
; RESERVED005C 0x005C RESERVED
|
||
; SP 0x005D Stack Pointer
|
||
; SP.SP7 7
|
||
; SP.SP6 6
|
||
; SP.SP5 5
|
||
; SP.SP4 4
|
||
; SP.SP3 3
|
||
; SP.SP2 2
|
||
; SP.SP1 1
|
||
; SP.SP0 0
|
||
; RESERVED005E 0x005E RESERVED
|
||
; SREG 0x005F Status Register
|
||
; SREG.I 7 Global Interrupt Enable
|
||
; SREG.T 6 Bit Copy Storage
|
||
; SREG.H 5 Half-carry Flag
|
||
; SREG.S 4 Sign Bit
|
||
; SREG.V 3 Two's Complement Overflow Flag
|
||
; SREG.N 2 Negative Flag
|
||
; SREG.Z 1 Zero Flag
|
||
; SREG.C 0 Carry Flag
|
||
|
||
|
||
.AT90S_LS8535
|
||
SUBARCH=2
|
||
; doc1041.pdf
|
||
;
|
||
|
||
RAM=512
|
||
ROM=8192
|
||
EEPROM=512
|
||
|
||
|
||
; MEMORY MAP
|
||
area DATA GPWR_ 0x0000:0x0020 General Purpose Working Registers
|
||
area DATA FSR_ 0x0020:0x0060 I/O registers
|
||
area DATA SRAM_ 0x0060:0x0260 Internal SRAM
|
||
|
||
|
||
; Interrupt and reset vector assignments
|
||
entry __RESET 0x0000 Hardware Pin, Power-on Reset and Watchdog Reset
|
||
entry INT0_ 0x0001 External Interrupt Request 0
|
||
entry INT1_ 0x0002 External Interrupt Request 1
|
||
entry TIMER2_COMP 0x0003 Timer/Counter2 Compare Match
|
||
entry TIMER2_OVF 0x0004 Timer/Counter2 Overflow
|
||
entry TIMER1_CAPT 0x0005 Timer/Counter1 Capture Event
|
||
entry TIMER1_COMPA 0x0006 Timer/Counter1 Compare Match A
|
||
entry TIMER1_COMPB 0x0007 Timer/Counter1 Compare Match B
|
||
entry TIMER1_OVF 0x0008 Timer/Counter1 Overflow
|
||
entry TIMER0_OVF 0x0009 Timer/Counter0 Overflow
|
||
entry SPI_STC 0x000A SPI Serial Transfer Complete
|
||
entry UART_RX 0x000B UART, Rx Complete
|
||
|
||
|
||
; INPUT/OUTPUT PORTS
|
||
RESERVED0000 0x0000 RESERVED
|
||
RESERVED0001 0x0001 RESERVED
|
||
RESERVED0002 0x0002 RESERVED
|
||
RESERVED0003 0x0003 RESERVED
|
||
ADCL 0x0004 ADC Data Register Low
|
||
ADCL.ADC7 7 Conversion result 7
|
||
ADCL.ADC6 6 Conversion result 6
|
||
ADCL.ADC5 5 Conversion result 5
|
||
ADCL.ADC4 4 Conversion result 4
|
||
ADCL.ADC3 3 Conversion result 3
|
||
ADCL.ADC2 2 Conversion result 2
|
||
ADCL.ADC1 1 Conversion result 1
|
||
ADCL.ADC0 0 Conversion result 0
|
||
ADCH 0x0005 ADC Data Register High
|
||
ADCH.ADC8 8 Conversion result 8
|
||
ADCH.ADC9 9 Conversion result 9
|
||
ADCSR 0x0006 ADC Control and Status Register
|
||
ADCSR.ADEN 7 ADC Enable
|
||
ADCSR.ADSC 6 ADC Start Conversion
|
||
ADCSR.ADFR 5 ADC Free Running Select
|
||
ADCSR.ADIF 4 ADC Interrupt Flag
|
||
ADCSR.ADIE 3 ADC Interrupt Enable
|
||
ADCSR.ADPS2 2 ADC Prescaler Select Bit 2
|
||
ADCSR.ADPS1 1 ADC Prescaler Select Bit 1
|
||
ADCSR.ADPS0 0 ADC Prescaler Select Bit 0
|
||
ADMUX 0x0007 ADC Multiplexer Select Register
|
||
ADMUX.MUX2 2 Analog Channel Select Bit 2
|
||
ADMUX.MUX1 1 Analog Channel Select Bit 1
|
||
ADMUX.MUX0 0 Analog Channel Select Bit 0
|
||
ACSR 0x0008 Analog Comparator Control and Status Register
|
||
ACSR.ACD 7 Analog Comparator Disable
|
||
ACSR.ACO 5 Analog Comparator Output
|
||
ACSR.ACI 4 Analog Comparator Interrupt Flag
|
||
ACSR.ACIE 3 Analog Comparator Interrupt Enable
|
||
ACSR.ACIC 2 Analog Comparator Input Capture Enable
|
||
ACSR.ACIS1 1 Analog Comparator Interrupt Mode Select 1
|
||
ACSR.ACIS0 0 Analog Comparator Interrupt Mode Select 0
|
||
UBRR 0x0009 UART Baud Rate Register
|
||
UCR 0x000A UART Control Register
|
||
UCR.RXCIE 7 RX Complete Interrupt Enable
|
||
UCR.TXCIE 6 TX Complete Interrupt Enable
|
||
UCR.UDRIE 5 UART Data Register Empty Interrupt Enable
|
||
UCR.RXEN 4 Receiver Enable
|
||
UCR.TXEN 3 Transmitter Enable
|
||
UCR.CHR9 2 9 Bit Characters
|
||
UCR.RXB8 1 Receive Data Bit 8
|
||
UCR.TXB8 0 Transmit Data Bit 8
|
||
USR 0x000B UART Status Register
|
||
USR.RXC 7 UART Receive Complete
|
||
USR.TXC 6 UART Transmit Complete
|
||
USR.UDRE 5 UART Data Register Empty
|
||
USR.FE 4 Framing Error
|
||
USR.OR 3 OverRun
|
||
UDR 0x000C UART I/O Data Register
|
||
SPCR 0x000D SPI Control Register
|
||
SPCR.SPIE 7 SPI Interrupt Enable
|
||
SPCR.SPE 6 SPI Enable
|
||
SPCR.DORD 5 Data Order
|
||
SPCR.MSTR 4 Master/Slave Select
|
||
SPCR.CPOL 3 Clock Polarity
|
||
SPCR.CPHA 2 Clock Phase
|
||
SPCR.SPR1 1 SPI Clock Rate Select 1
|
||
SPCR.SPR0 0 SPI Clock Rate Select 0
|
||
SPSR 0x000E SPI Status Register
|
||
SPSR.SPIF 7 SPI Interrupt Flag
|
||
SPSR.WCOL 6 Write Collision flag
|
||
SPDR 0x000F SPI Data Register
|
||
PIND 0x0010 Port D Input Pins Address
|
||
PIND.PIND7 7
|
||
PIND.PIND6 6
|
||
PIND.PIND5 5
|
||
PIND.PIND4 4
|
||
PIND.PIND3 3
|
||
PIND.PIND2 2
|
||
PIND.PIND1 1
|
||
PIND.PIND0 0
|
||
DDRD 0x0011 Port D Data Direction Register
|
||
DDRD.DDD7 7 Port D Data Direction Register bit 7
|
||
DDRD.DDD6 6 Port D Data Direction Register bit 6
|
||
DDRD.DDD5 5 Port D Data Direction Register bit 5
|
||
DDRD.DDD4 4 Port D Data Direction Register bit 4
|
||
DDRD.DDD3 3 Port D Data Direction Register bit 3
|
||
DDRD.DDD2 2 Port D Data Direction Register bit 2
|
||
DDRD.DDD1 1 Port D Data Direction Register bit 1
|
||
DDRD.DDD0 0 Port D Data Direction Register bit 0
|
||
PORTD 0x0012 Port D Data Register
|
||
PORTD.PORTD7 7 Port D Data Register bit 7
|
||
PORTD.PORTD6 6 Port D Data Register bit 6
|
||
PORTD.PORTD5 5 Port D Data Register bit 5
|
||
PORTD.PORTD4 4 Port D Data Register bit 4
|
||
PORTD.PORTD3 3 Port D Data Register bit 3
|
||
PORTD.PORTD2 2 Port D Data Register bit 2
|
||
PORTD.PORTD1 1 Port D Data Register bit 1
|
||
PORTD.PORTD0 0 Port D Data Register bit 0
|
||
PINC 0x0013 Port C Input Pins Address
|
||
PINC.PINC7 7
|
||
PINC.PINC6 6
|
||
PINC.PINC5 5
|
||
PINC.PINC4 4
|
||
PINC.PINC3 3
|
||
PINC.PINC2 2
|
||
PINC.PINC1 1
|
||
PINC.PINC0 0
|
||
DDRC 0x0014 Port C Data Direction Register
|
||
DDRC.DDC7 7 Port C Data Direction Register bit 7
|
||
DDRC.DDC6 6 Port C Data Direction Register bit 6
|
||
DDRC.DDC5 5 Port C Data Direction Register bit 5
|
||
DDRC.DDC4 4 Port C Data Direction Register bit 4
|
||
DDRC.DDC3 3 Port C Data Direction Register bit 3
|
||
DDRC.DDC2 2 Port C Data Direction Register bit 2
|
||
DDRC.DDC1 1 Port C Data Direction Register bit 1
|
||
DDRC.DDC0 0 Port C Data Direction Register bit 0
|
||
PORTC 0x0015 Port C Data Register
|
||
PORTC.PORTC7 7 Port C Data Register bit 7
|
||
PORTC.PORTC6 6 Port C Data Register bit 6
|
||
PORTC.PORTC5 5 Port C Data Register bit 5
|
||
PORTC.PORTC4 4 Port C Data Register bit 4
|
||
PORTC.PORTC3 3 Port C Data Register bit 3
|
||
PORTC.PORTC2 2 Port C Data Register bit 2
|
||
PORTC.PORTC1 1 Port C Data Register bit 1
|
||
PORTC.PORTC0 0 Port C Data Register bit 0
|
||
PINB 0x0016 Port B Input Pins Address
|
||
PINB.PINB7 7
|
||
PINB.PINB6 6
|
||
PINB.PINB5 5
|
||
PINB.PINB4 4
|
||
PINB.PINB3 3
|
||
PINB.PINB2 2
|
||
PINB.PINB1 1
|
||
PINB.PINB0 0
|
||
DDRB 0x0017 Port B Data Direction Register
|
||
DDRB.DDB7 7 Port B Data Direction Register bit 7
|
||
DDRB.DDB6 6 Port B Data Direction Register bit 6
|
||
DDRB.DDB5 5 Port B Data Direction Register bit 5
|
||
DDRB.DDB4 4 Port B Data Direction Register bit 4
|
||
DDRB.DDB3 3 Port B Data Direction Register bit 3
|
||
DDRB.DDB2 2 Port B Data Direction Register bit 2
|
||
DDRB.DDB1 1 Port B Data Direction Register bit 1
|
||
DDRB.DDB0 0 Port B Data Direction Register bit 0
|
||
PORTB 0x0018 Port B Data Register
|
||
PORTB.PORTB7 7 Port B Data Register bit 7
|
||
PORTB.PORTB6 6 Port B Data Register bit 6
|
||
PORTB.PORTB5 5 Port B Data Register bit 5
|
||
PORTB.PORTB4 4 Port B Data Register bit 4
|
||
PORTB.PORTB3 3 Port B Data Register bit 3
|
||
PORTB.PORTB2 2 Port B Data Register bit 2
|
||
PORTB.PORTB1 1 Port B Data Register bit 1
|
||
PORTB.PORTB0 0 Port B Data Register bit 0
|
||
PINA 0x0019 Port A Input Pins Address
|
||
PINA.PINA7 7
|
||
PINA.PINA6 6
|
||
PINA.PINA5 5
|
||
PINA.PINA4 4
|
||
PINA.PINA3 3
|
||
PINA.PINA2 2
|
||
PINA.PINA1 1
|
||
PINA.PINA0 0
|
||
DDRA 0x001A Port A Data Direction Register
|
||
DDRA.DDA7 7 Port A Data Direction Register bit 7
|
||
DDRA.DDA6 6 Port A Data Direction Register bit 6
|
||
DDRA.DDA5 5 Port A Data Direction Register bit 5
|
||
DDRA.DDA4 4 Port A Data Direction Register bit 4
|
||
DDRA.DDA3 3 Port A Data Direction Register bit 3
|
||
DDRA.DDA2 2 Port A Data Direction Register bit 2
|
||
DDRA.DDA1 1 Port A Data Direction Register bit 1
|
||
DDRA.DDA0 0 Port A Data Direction Register bit 0
|
||
PORTA 0x001B Port A Data Register
|
||
PORTA.PORTA7 7 Port A Data Register bit 7
|
||
PORTA.PORTA6 6 Port A Data Register bit 6
|
||
PORTA.PORTA5 5 Port A Data Register bit 5
|
||
PORTA.PORTA4 4 Port A Data Register bit 4
|
||
PORTA.PORTA3 3 Port A Data Register bit 3
|
||
PORTA.PORTA2 2 Port A Data Register bit 2
|
||
PORTA.PORTA1 1 Port A Data Register bit 1
|
||
PORTA.PORTA0 0 Port A Data Register bit 0
|
||
EECR 0x001C EEPROM Control Register
|
||
EECR.EERIE 3 EEPROM Ready Interrupt Enable
|
||
EECR.EEMWE 2 EEPROM Master Write Enable
|
||
EECR.EEWE 1 EEPROM Write Enable
|
||
EECR.EERE 0 EEPROM Read Enable
|
||
EEDR 0x001D EEPROM Data Register
|
||
EEARL 0x001E EEPROM Address Register Low
|
||
EEARH 0x001F EEPROM Address Register High
|
||
RESERVED0020 0x0020 RESERVED
|
||
WDTCR 0x0021 Watchdog Timer Control Register
|
||
WDTCR.WDTOE 4 Watchdog Turn-off Enable
|
||
WDTCR.WDE 3 Watchdog Enable
|
||
WDTCR.WDP2 2 Watchdog Timer Prescaler 2
|
||
WDTCR.WDP1 1 Watchdog Timer Prescaler 1
|
||
WDTCR.WDP0 0 Watchdog Timer Prescaler 0
|
||
ASSR 0x0022 Asynchronous Status Register
|
||
ASSR.AS2 3 Asynchronous Timer/Counter2
|
||
ASSR.TCN2UB 2 Timer/Counter2 Update Busy
|
||
ASSR.OCR2UB 1 Output Compare Register2 Update Busy
|
||
ASSR.TCR2UB 0 Timer/Counter Control Register2 Update Busy
|
||
OCR2 0x0023 Timer/Counter2 Output Compare Register
|
||
TCNT2 0x0024 Timer/Counter2
|
||
TCCR2 0x0025 Timer/Counter2 Control Register
|
||
TCCR2.PWM2 6 Pulse Width Modulator Enable
|
||
TCCR2.COM21 5 Compare Output Mode, Bits 1
|
||
TCCR2.COM20 4 Compare Output Mode, Bits 0
|
||
TCCR2.CTC2 3 Clear Timer/Counter on Compare Match
|
||
TCCR2.CS22 2 Clock Select Bit 2
|
||
TCCR2.CS21 1 Clock Select Bit 1
|
||
TCCR2.CS20 0 Clock Select Bit 0
|
||
ICR1L 0x0026 Timer/Counter1 Input Capture Register Low
|
||
ICR1H 0x0027 Timer/Counter1 Input Capture Register High
|
||
OCR1BL 0x0028 Timer/Counter1 Output Compare Register Low
|
||
OCR1BH 0x0029 Timer/Counter1 Output Compare Register High
|
||
OCR1AL 0x002A Timer/Counter1 Output Compare Register Low
|
||
OCR1AH 0x002B Timer/Counter1 Output Compare Register High
|
||
TCNT1L 0x002C Timer/Counter1 Low
|
||
TCNT1H 0x002D Timer/Counter1 High
|
||
TCCR1B 0x002E Timer/Counter1 Control Register B
|
||
TCCR1B.ICNC1 7 Input Capture1 Noise Canceler (4 CKs)
|
||
TCCR1B.ICES1 6 Input Capture1 Edge Select
|
||
TCCR1B.CTC1 3 Clear Timer/Counter1 on Compare Match
|
||
TCCR1B.CS12 2 Clock Select1, Bit 2
|
||
TCCR1B.CS11 1 Clock Select1, Bit 1
|
||
TCCR1B.CS10 0 Clock Select1, Bit 0
|
||
TCCR1A 0x002F Timer/Counter1 Control Register A
|
||
TCCR1A.COM1A1 7 Compare Output Mode1A, Bit 1
|
||
TCCR1A.COM1A0 6 Compare Output Mode1A, Bit 0
|
||
TCCR1A.COM1B1 5 Compare Output Mode1B, Bit 1
|
||
TCCR1A.COM1B0 4 Compare Output Mode1B, Bit 0
|
||
TCCR1A.PWM11 1 Pulse Width Modulator Select Bit 1
|
||
TCCR1A.PWM10 0 Pulse Width Modulator Select Bit 0
|
||
RESERVED0030 0x0030 RESERVED
|
||
RESERVED0031 0x0031 RESERVED
|
||
TCNT0 0x0032 Timer Counter 0
|
||
TCCR0 0x0033 Timer/Counter0 Control Register
|
||
TCCR0.CS02 2 Clock Select0, Bit 2
|
||
TCCR0.CS01 1 Clock Select0, Bit 1
|
||
TCCR0.CS00 0 Clock Select0, Bit 0
|
||
MCUSR 0x0034 MCU Status Register
|
||
MCUSR.EXTRF 1 External Reset Flag
|
||
MCUSR.PORF 0 Power-on Reset Flag
|
||
MCUCR 0x0035 MCU Control Register
|
||
MCUCR.SE 6 Sleep Enable
|
||
MCUCR.SM1 5 Sleep Mode Select Bit 1
|
||
MCUCR.SM0 4 Sleep Mode Select Bit 0
|
||
MCUCR.ISC11 3 Interrupt Sense Control 1 Bit 1
|
||
MCUCR.ISC10 2 Interrupt Sense Control 1 Bit 0
|
||
MCUCR.ISC01 1 Interrupt Sense Control 0 Bit 1
|
||
MCUCR.ISC00 0 Interrupt Sense Control 0 Bit 0
|
||
RESERVED0036 0x0036 RESERVED
|
||
RESERVED0037 0x0037 RESERVED
|
||
TIFR 0x0038 Timer/Counter Interrupt Flag Register
|
||
TIFR.OCF2 7 Output Compare Flag 2
|
||
TIFR.TOV2 6 Timer/Counter2 Overflow Flag
|
||
TIFR.ICF1 5 Input Capture Flag 1
|
||
TIFR.OCF1A 4 Output Compare Flag 1A
|
||
TIFR.OCF1B 3 Output Compare Flag 1B
|
||
TIFR.TOV1 2 Timer/Counter1 Overflow Flag
|
||
TIFR.TOV0 0 Timer/Counter0 Overflow Flag
|
||
TIMSK 0x0039 Timer/Counter Interrupt Mask Register
|
||
TIMSK.OCIE2 7 Timer/Counter2 Output Compare Match Interrupt Enable
|
||
TIMSK.TOIE2 6 Timer/Counter2 Overflow Interrupt Enable
|
||
TIMSK.TICIE1 5 Timer/Counter1 Input Capture Interrupt Enable
|
||
TIMSK.OCIE1A 4 Timer/Counter1 Output CompareA Match Interrupt Enable
|
||
TIMSK.OCIE1B 3 Timer/Counter1 Output CompareB Match Interrupt Enable
|
||
TIMSK.TOIE1 2 Timer/Counter1 Overflow Interrupt Enable
|
||
TIMSK.TOIE0 0 Timer/Counter0 Overflow Interrupt Enable
|
||
GIFR 0x003A General Interrupt Flag Register
|
||
GIFR.INTF1 7 External Interrupt Flag1
|
||
GIFR.INTF0 6 External Interrupt Flag0
|
||
GIMSK 0x003B General Interrupt Mask Register
|
||
GIMSK.INT1 7 External Interrupt Request 1 Enable
|
||
GIMSK.INT0 6 External Interrupt Request 0 Enable
|
||
RESERVED003C 0x003C RESERVED
|
||
SPL 0x003D Stack Pointer
|
||
SPL.SP7 7
|
||
SPL.SP6 6
|
||
SPL.SP5 5
|
||
SPL.SP4 4
|
||
SPL.SP3 3
|
||
SPL.SP2 2
|
||
SPL.SP1 1
|
||
SPL.SP0 0
|
||
SPH 0x003E Stack Pointer
|
||
SPH.SP9 9
|
||
SPH.SP8 8
|
||
SREG 0x003F Status Register
|
||
SREG.I 7 Global Interrupt Enable
|
||
SREG.T 6 Bit Copy Storage
|
||
SREG.H 5 Half-carry Flag
|
||
SREG.S 4 Sign Bit
|
||
SREG.V 3 Two's Complement Overflow Flag
|
||
SREG.N 2 Negative Flag
|
||
SREG.Z 1 Zero Flag
|
||
SREG.C 0 Carry Flag
|
||
|
||
; RESERVED0020 0x0020 RESERVED
|
||
; RESERVED0021 0x0021 RESERVED
|
||
; RESERVED0022 0x0022 RESERVED
|
||
; RESERVED0023 0x0023 RESERVED
|
||
; ADCL 0x0024 ADC Data Register Low
|
||
; ADCL.ADC7 7 Conversion result 7
|
||
; ADCL.ADC6 6 Conversion result 6
|
||
; ADCL.ADC5 5 Conversion result 5
|
||
; ADCL.ADC4 4 Conversion result 4
|
||
; ADCL.ADC3 3 Conversion result 3
|
||
; ADCL.ADC2 2 Conversion result 2
|
||
; ADCL.ADC1 1 Conversion result 1
|
||
; ADCL.ADC0 0 Conversion result 0
|
||
; ADCH 0x0025 ADC Data Register High
|
||
; ADCH.ADC8 8 Conversion result 8
|
||
; ADCH.ADC9 9 Conversion result 9
|
||
; ADCSR 0x0026 ADC Control and Status Register
|
||
; ADCSR.ADEN 7 ADC Enable
|
||
; ADCSR.ADSC 6 ADC Start Conversion
|
||
; ADCSR.ADFR 5 ADC Free Running Select
|
||
; ADCSR.ADIF 4 ADC Interrupt Flag
|
||
; ADCSR.ADIE 3 ADC Interrupt Enable
|
||
; ADCSR.ADPS2 2 ADC Prescaler Select Bit 2
|
||
; ADCSR.ADPS1 1 ADC Prescaler Select Bit 1
|
||
; ADCSR.ADPS0 0 ADC Prescaler Select Bit 0
|
||
; ADMUX 0x0027 ADC Multiplexer Select Register
|
||
; ADMUX.MUX2 2 Analog Channel Select Bit 2
|
||
; ADMUX.MUX1 1 Analog Channel Select Bit 1
|
||
; ADMUX.MUX0 0 Analog Channel Select Bit 0
|
||
; ACSR 0x0028 Analog Comparator Control and Status Register
|
||
; ACSR.ACD 7 Analog Comparator Disable
|
||
; ACSR.ACO 5 Analog Comparator Output
|
||
; ACSR.ACI 4 Analog Comparator Interrupt Flag
|
||
; ACSR.ACIE 3 Analog Comparator Interrupt Enable
|
||
; ACSR.ACIC 2 Analog Comparator Input Capture Enable
|
||
; ACSR.ACIS1 1 Analog Comparator Interrupt Mode Select 1
|
||
; ACSR.ACIS0 0 Analog Comparator Interrupt Mode Select 0
|
||
; UBRR 0x0029 UART Baud Rate Register
|
||
; UCR 0x002A UART Control Register
|
||
; UCR.RXCIE 7 RX Complete Interrupt Enable
|
||
; UCR.TXCIE 6 TX Complete Interrupt Enable
|
||
; UCR.UDRIE 5 UART Data Register Empty Interrupt Enable
|
||
; UCR.RXEN 4 Receiver Enable
|
||
; UCR.TXEN 3 Transmitter Enable
|
||
; UCR.CHR9 2 9 Bit Characters
|
||
; UCR.RXB8 1 Receive Data Bit 8
|
||
; UCR.TXB8 0 Transmit Data Bit 8
|
||
; USR 0x002B UART Status Register
|
||
; USR.RXC 7 UART Receive Complete
|
||
; USR.TXC 6 UART Transmit Complete
|
||
; USR.UDRE 5 UART Data Register Empty
|
||
; USR.FE 4 Framing Error
|
||
; USR.OR 3 OverRun
|
||
; UDR 0x002C UART I/O Data Register
|
||
; SPCR 0x002D SPI Control Register
|
||
; SPCR.SPIE 7 SPI Interrupt Enable
|
||
; SPCR.SPE 6 SPI Enable
|
||
; SPCR.DORD 5 Data Order
|
||
; SPCR.MSTR 4 Master/Slave Select
|
||
; SPCR.CPOL 3 Clock Polarity
|
||
; SPCR.CPHA 2 Clock Phase
|
||
; SPCR.SPR1 1 SPI Clock Rate Select 1
|
||
; SPCR.SPR0 0 SPI Clock Rate Select 0
|
||
; SPSR 0x002E SPI Status Register
|
||
; SPSR.SPIF 7 SPI Interrupt Flag
|
||
; SPSR.WCOL 6 Write Collision flag
|
||
; SPDR 0x002F SPI Data Register
|
||
; PIND 0x0030 Port D Input Pins Address
|
||
; DDRD 0x0031 Port D Data Direction Register
|
||
; DDRD.DDD7 7 Port D Data Direction Register bit 7
|
||
; DDRD.DDD6 6 Port D Data Direction Register bit 6
|
||
; DDRD.DDD5 5 Port D Data Direction Register bit 5
|
||
; DDRD.DDD4 4 Port D Data Direction Register bit 4
|
||
; DDRD.DDD3 3 Port D Data Direction Register bit 3
|
||
; DDRD.DDD2 2 Port D Data Direction Register bit 2
|
||
; DDRD.DDD1 1 Port D Data Direction Register bit 1
|
||
; DDRD.DDD0 0 Port D Data Direction Register bit 0
|
||
; PORTD 0x0032 Port D Data Register
|
||
; PORTD.PORTD7 7 Port D Data Register bit 7
|
||
; PORTD.PORTD6 6 Port D Data Register bit 6
|
||
; PORTD.PORTD5 5 Port D Data Register bit 5
|
||
; PORTD.PORTD4 4 Port D Data Register bit 4
|
||
; PORTD.PORTD3 3 Port D Data Register bit 3
|
||
; PORTD.PORTD2 2 Port D Data Register bit 2
|
||
; PORTD.PORTD1 1 Port D Data Register bit 1
|
||
; PORTD.PORTD0 0 Port D Data Register bit 0
|
||
; PINC 0x0033 Port C Input Pins Address
|
||
; PINC.PINC7 7
|
||
; PINC.PINC6 6
|
||
; PINC.PINC5 5
|
||
; PINC.PINC4 4
|
||
; PINC.PINC3 3
|
||
; PINC.PINC2 2
|
||
; PINC.PINC1 1
|
||
; PINC.PINC0 0
|
||
; DDRC 0x0034 Port C Data Direction Register
|
||
; DDRC.DDC7 7 Port C Data Direction Register bit 7
|
||
; DDRC.DDC6 6 Port C Data Direction Register bit 6
|
||
; DDRC.DDC5 5 Port C Data Direction Register bit 5
|
||
; DDRC.DDC4 4 Port C Data Direction Register bit 4
|
||
; DDRC.DDC3 3 Port C Data Direction Register bit 3
|
||
; DDRC.DDC2 2 Port C Data Direction Register bit 2
|
||
; DDRC.DDC1 1 Port C Data Direction Register bit 1
|
||
; DDRC.DDC0 0 Port C Data Direction Register bit 0
|
||
; PORTC 0x0035 Port C Data Register
|
||
; PORTC.PORTC7 7 Port C Data Register bit 7
|
||
; PORTC.PORTC6 6 Port C Data Register bit 6
|
||
; PORTC.PORTC5 5 Port C Data Register bit 5
|
||
; PORTC.PORTC4 4 Port C Data Register bit 4
|
||
; PORTC.PORTC3 3 Port C Data Register bit 3
|
||
; PORTC.PORTC2 2 Port C Data Register bit 2
|
||
; PORTC.PORTC1 1 Port C Data Register bit 1
|
||
; PORTC.PORTC0 0 Port C Data Register bit 0
|
||
; PINB 0x0036 Port B Input Pins Address
|
||
; PINB.PINB7 7
|
||
; PINB.PINB6 6
|
||
; PINB.PINB5 5
|
||
; PINB.PINB4 4
|
||
; PINB.PINB3 3
|
||
; PINB.PINB2 2
|
||
; PINB.PINB1 1
|
||
; PINB.PINB0 0
|
||
; DDRB 0x0037 Port B Data Direction Register
|
||
; DDRB.DDB7 7 Port B Data Direction Register bit 7
|
||
; DDRB.DDB6 6 Port B Data Direction Register bit 6
|
||
; DDRB.DDB5 5 Port B Data Direction Register bit 5
|
||
; DDRB.DDB4 4 Port B Data Direction Register bit 4
|
||
; DDRB.DDB3 3 Port B Data Direction Register bit 3
|
||
; DDRB.DDB2 2 Port B Data Direction Register bit 2
|
||
; DDRB.DDB1 1 Port B Data Direction Register bit 1
|
||
; DDRB.DDB0 0 Port B Data Direction Register bit 0
|
||
; PORTB 0x0038 Port B Data Register
|
||
; PORTB.PORTB7 7 Port B Data Register bit 7
|
||
; PORTB.PORTB6 6 Port B Data Register bit 6
|
||
; PORTB.PORTB5 5 Port B Data Register bit 5
|
||
; PORTB.PORTB4 4 Port B Data Register bit 4
|
||
; PORTB.PORTB3 3 Port B Data Register bit 3
|
||
; PORTB.PORTB2 2 Port B Data Register bit 2
|
||
; PORTB.PORTB1 1 Port B Data Register bit 1
|
||
; PORTB.PORTB0 0 Port B Data Register bit 0
|
||
; PINA 0x0039 Port A Input Pins Address
|
||
; PINA.PINA7 7
|
||
; PINA.PINA6 6
|
||
; PINA.PINA5 5
|
||
; PINA.PINA4 4
|
||
; PINA.PINA3 3
|
||
; PINA.PINA2 2
|
||
; PINA.PINA1 1
|
||
; PINA.PINA0 0
|
||
; DDRA 0x003A Port A Data Direction Register
|
||
; DDRA.DDA7 7 Port A Data Direction Register bit 7
|
||
; DDRA.DDA6 6 Port A Data Direction Register bit 6
|
||
; DDRA.DDA5 5 Port A Data Direction Register bit 5
|
||
; DDRA.DDA4 4 Port A Data Direction Register bit 4
|
||
; DDRA.DDA3 3 Port A Data Direction Register bit 3
|
||
; DDRA.DDA2 2 Port A Data Direction Register bit 2
|
||
; DDRA.DDA1 1 Port A Data Direction Register bit 1
|
||
; DDRA.DDA0 0 Port A Data Direction Register bit 0
|
||
; PORTA 0x003B Port A Data Register
|
||
; PORTA.PORTA7 7 Port A Data Register bit 7
|
||
; PORTA.PORTA6 6 Port A Data Register bit 6
|
||
; PORTA.PORTA5 5 Port A Data Register bit 5
|
||
; PORTA.PORTA4 4 Port A Data Register bit 4
|
||
; PORTA.PORTA3 3 Port A Data Register bit 3
|
||
; PORTA.PORTA2 2 Port A Data Register bit 2
|
||
; PORTA.PORTA1 1 Port A Data Register bit 1
|
||
; PORTA.PORTA0 0 Port A Data Register bit 0
|
||
; EECR 0x003C EEPROM Control Register
|
||
; EECR.EERIE 3 EEPROM Ready Interrupt Enable
|
||
; EECR.EEMWE 2 EEPROM Master Write Enable
|
||
; EECR.EEWE 1 EEPROM Write Enable
|
||
; EECR.EERE 0 EEPROM Read Enable
|
||
; EEDR 0x003D EEPROM Data Register
|
||
; EEARL 0x003E EEPROM Address Register Low
|
||
; EEARH 0x003F EEPROM Address Register High
|
||
; RESERVED0040 0x0040 RESERVED
|
||
; WDTCR 0x0041 Watchdog Timer Control Register
|
||
; WDTCR.WDTOE 4 Watchdog Turn-off Enable
|
||
; WDTCR.WDE 3 Watchdog Enable
|
||
; WDTCR.WDP2 2 Watchdog Timer Prescaler 2
|
||
; WDTCR.WDP1 1 Watchdog Timer Prescaler 1
|
||
; WDTCR.WDP0 0 Watchdog Timer Prescaler 0
|
||
; ASSR 0x0042 Asynchronous Status Register
|
||
; ASSR.AS2 3 Asynchronous Timer/Counter2
|
||
; ASSR.TCN2UB 2 Timer/Counter2 Update Busy
|
||
; ASSR.OCR2UB 1 Output Compare Register2 Update Busy
|
||
; ASSR.TCR2UB 0 Timer/Counter Control Register2 Update Busy
|
||
; OCR2 0x0043 Timer/Counter2 Output Compare Register
|
||
; TCNT2 0x0044 Timer/Counter2
|
||
; TCCR2 0x0045 Timer/Counter2 Control Register
|
||
; TCCR2.PWM2 6 Pulse Width Modulator Enable
|
||
; TCCR2.COM21 5 Compare Output Mode, Bits 1
|
||
; TCCR2.COM20 4 Compare Output Mode, Bits 0
|
||
; TCCR2.CTC2 3 Clear Timer/Counter on Compare Match
|
||
; TCCR2.CS22 2 Clock Select Bit 2
|
||
; TCCR2.CS21 1 Clock Select Bit 1
|
||
; TCCR2.CS20 0 Clock Select Bit 0
|
||
; ICR1L 0x0046 Timer/Counter1 Input Capture Register Low
|
||
; ICR1H 0x0047 Timer/Counter1 Input Capture Register High
|
||
; OCR1BL 0x0048 Timer/Counter1 Output Compare Register Low
|
||
; OCR1BH 0x0049 Timer/Counter1 Output Compare Register High
|
||
; OCR1AL 0x004A Timer/Counter1 Output Compare Register Low
|
||
; OCR1AH 0x004B Timer/Counter1 Output Compare Register High
|
||
; TCNT1L 0x004C Timer/Counter1 Low
|
||
; TCNT1H 0x004D Timer/Counter1 High
|
||
; TCCR1B 0x004E Timer/Counter1 Control Register B
|
||
; TCCR1B.ICNC1 7 Input Capture1 Noise Canceler (4 CKs)
|
||
; TCCR1B.ICES1 6 Input Capture1 Edge Select
|
||
; TCCR1B.CTC1 3 Clear Timer/Counter1 on Compare Match
|
||
; TCCR1B.CS12 2 Clock Select1, Bit 2
|
||
; TCCR1B.CS11 1 Clock Select1, Bit 1
|
||
; TCCR1B.CS10 0 Clock Select1, Bit 0
|
||
; TCCR1A 0x004F Timer/Counter1 Control Register A
|
||
; TCCR1A.COM1A1 7 Compare Output Mode1A, Bit 1
|
||
; TCCR1A.COM1A0 6 Compare Output Mode1A, Bit 0
|
||
; TCCR1A.COM1B1 5 Compare Output Mode1B, Bit 1
|
||
; TCCR1A.COM1B0 4 Compare Output Mode1B, Bit 0
|
||
; TCCR1A.PWM11 1 Pulse Width Modulator Select Bit 1
|
||
; TCCR1A.PWM10 0 Pulse Width Modulator Select Bit 0
|
||
; RESERVED0050 0x0050 RESERVED
|
||
; RESERVED0051 0x0051 RESERVED
|
||
; TCNT0 0x0052 Timer Counter 0
|
||
; TCCR0 0x0053 Timer/Counter0 Control Register
|
||
; TCCR0.CS02 2 Clock Select0, Bit 2
|
||
; TCCR0.CS01 1 Clock Select0, Bit 1
|
||
; TCCR0.CS00 0 Clock Select0, Bit 0
|
||
; MCUSR 0x0054 MCU Status Register
|
||
; MCUSR.EXTRF 1 External Reset Flag
|
||
; MCUSR.PORF 0 Power-on Reset Flag
|
||
; MCUCR 0x0055 MCU Control Register
|
||
; MCUCR.SE 6 Sleep Enable
|
||
; MCUCR.SM1 5 Sleep Mode Select Bit 1
|
||
; MCUCR.SM0 4 Sleep Mode Select Bit 0
|
||
; MCUCR.ISC11 3 Interrupt Sense Control 1 Bit 1
|
||
; MCUCR.ISC10 2 Interrupt Sense Control 1 Bit 0
|
||
; MCUCR.ISC01 1 Interrupt Sense Control 0 Bit 1
|
||
; MCUCR.ISC00 0 Interrupt Sense Control 0 Bit 0
|
||
; RESERVED0056 0x0056 RESERVED
|
||
; RESERVED0057 0x0057 RESERVED
|
||
; TIFR 0x0058 Timer/Counter Interrupt Flag Register
|
||
; TIFR.OCF2 7 Output Compare Flag 2
|
||
; TIFR.TOV2 6 Timer/Counter2 Overflow Flag
|
||
; TIFR.ICF1 5 Input Capture Flag 1
|
||
; TIFR.OCF1A 4 Output Compare Flag 1A
|
||
; TIFR.OCF1B 3 Output Compare Flag 1B
|
||
; TIFR.TOV1 2 Timer/Counter1 Overflow Flag
|
||
; TIFR.TOV0 0 Timer/Counter0 Overflow Flag
|
||
; TIMSK 0x0059 Timer/Counter Interrupt Mask Register
|
||
; TIMSK.OCIE2 7 Timer/Counter2 Output Compare Match Interrupt Enable
|
||
; TIMSK.TOIE2 6 Timer/Counter2 Overflow Interrupt Enable
|
||
; TIMSK.TICIE1 5 Timer/Counter1 Input Capture Interrupt Enable
|
||
; TIMSK.OCIE1A 4 Timer/Counter1 Output CompareA Match Interrupt Enable
|
||
; TIMSK.OCIE1B 3 Timer/Counter1 Output CompareB Match Interrupt Enable
|
||
; TIMSK.TOIE1 2 Timer/Counter1 Overflow Interrupt Enable
|
||
; TIMSK.TOIE0 0 Timer/Counter0 Overflow Interrupt Enable
|
||
; GIFR 0x005A General Interrupt Flag Register
|
||
; GIFR.INTF1 7 External Interrupt Flag1
|
||
; GIFR.INTF0 6 External Interrupt Flag0
|
||
; GIMSK 0x005B General Interrupt Mask Register
|
||
; GIMSK.INT1 7 External Interrupt Request 1 Enable
|
||
; GIMSK.INT0 6 External Interrupt Request 0 Enable
|
||
; RESERVED003C 0x005C RESERVED
|
||
; SPL 0x005D Stack Pointer
|
||
; SPL.SP7 7
|
||
; SPL.SP6 6
|
||
; SPL.SP5 5
|
||
; SPL.SP4 4
|
||
; SPL.SP3 3
|
||
; SPL.SP2 2
|
||
; SPL.SP1 1
|
||
; SPL.SP0 0
|
||
; SPH 0x005E Stack Pointer
|
||
; SPH.SP9 9
|
||
; SPH.SP8 8
|
||
; SREG 0x005F Status Register
|
||
; SREG.I 7 Global Interrupt Enable
|
||
; SREG.T 6 Bit Copy Storage
|
||
; SREG.H 5 Half-carry Flag
|
||
; SREG.S 4 Sign Bit
|
||
; SREG.V 3 Two's Complement Overflow Flag
|
||
; SREG.N 2 Negative Flag
|
||
; SREG.Z 1 Zero Flag
|
||
; SREG.C 0 Carry Flag
|
||
|
||
|
||
.ATmega103_L
|
||
SUBARCH=31
|
||
; doc0945.pdf
|
||
;
|
||
|
||
RAM=4096
|
||
ROM=131072
|
||
EEPROM=4096
|
||
|
||
|
||
; MEMORY MAP
|
||
; Memory Configuration A
|
||
area DATA FSR_ 0x0000:0x0060
|
||
area DATA I_SRAM 0x0060:0x1000 Internal SRAM
|
||
; Memory Configuration B
|
||
; area DATA FSR_ 0x0000:0x0060
|
||
; area DATA I_SRAM 0x0060:0x1000 Internal SRAM
|
||
; area DATA E_SRAM 0x1000:0x10000 External SRAM
|
||
|
||
|
||
; Interrupt and reset vector assignments
|
||
entry __RESET 0x0000 Hardware Pin, Power-on Reset and Watchdog Reset
|
||
entry INT0_ 0x0002 External Interrupt Request 0
|
||
entry INT1_ 0x0004 External Interrupt Request 1
|
||
entry INT2_ 0x0006 External Interrupt Request 2
|
||
entry INT3_ 0x0008 External Interrupt Request 3
|
||
entry INT4_ 0x000A External Interrupt Request 4
|
||
entry INT5_ 0x000C External Interrupt Request 5
|
||
entry INT6_ 0x000E External Interrupt Request 6
|
||
entry INT7_ 0x0010 External Interrupt Request 7
|
||
entry TIMER2_COMP 0x0012 Timer/Counter2 Compare Match
|
||
entry TIMER2_OVF 0x0014 Timer/Counter2 Overflow
|
||
entry TIMER1_CAPT 0x0016 Timer/Counter1 Capture Event
|
||
entry TIMER1_COMPA 0x0018 Timer/Counter1 Compare Match A
|
||
entry TIMER1_COMPB 0x001A Timer/Counter1 Compare Match B
|
||
entry TIMER1_OVF 0x001C Timer/Counter1 Overflow
|
||
entry TIMER0_COMP 0x001E Timer/Counter0 Compare Match
|
||
entry TIMER0_OVF 0x0020 Timer/Counter0 Overflow
|
||
entry SPI_STC 0x0022 SPI Serial Transfer Complete
|
||
entry UART_RX 0x0024 UART, Rx Complete
|
||
entry UART_UDRE 0x0026 UART Data Register Empty
|
||
entry UART_TX 0x0028 UART, Tx Complete
|
||
entry ADC_ 0x002A ADC Conversion Complete
|
||
entry EE_READY 0x002C EEPROM Ready
|
||
entry ANALOG_COMP 0x002E Analog Comparator
|
||
|
||
|
||
; INPUT/OUTPUT PORTS
|
||
PINF 0x0000 Port F Input Pins Address
|
||
PINF.PINF7 7
|
||
PINF.PINF6 6
|
||
PINF.PINF5 5
|
||
PINF.PINF4 4
|
||
PINF.PINF3 3
|
||
PINF.PINF2 2
|
||
PINF.PINF1 1
|
||
PINF.PINF0 0
|
||
PINE 0x0001 Port E Input Pins Address
|
||
PINE.PINE7 7
|
||
PINE.PINE6 6
|
||
PINE.PINE5 5
|
||
PINE.PINE4 4
|
||
PINE.PINE3 3
|
||
PINE.PINE2 2
|
||
PINE.PINE1 1
|
||
PINE.PINE0 0
|
||
DDRE 0x0002 Port E Data Direction Register
|
||
DDRE.DDE7 7 Port E Data Direction Register bit 7
|
||
DDRE.DDE6 6 Port E Data Direction Register bit 6
|
||
DDRE.DDE5 5 Port E Data Direction Register bit 5
|
||
DDRE.DDE4 4 Port E Data Direction Register bit 4
|
||
DDRE.DDE3 3 Port E Data Direction Register bit 3
|
||
DDRE.DDE2 2 Port E Data Direction Register bit 2
|
||
DDRE.DDE1 1 Port E Data Direction Register bit 1
|
||
DDRE.DDE0 0 Port E Data Direction Register bit 0
|
||
PORTE 0x0003 Port E Data Register
|
||
PORTE.PORTE7 7 Port E Data Register bit 7
|
||
PORTE.PORTE6 6 Port E Data Register bit 6
|
||
PORTE.PORTE5 5 Port E Data Register bit 5
|
||
PORTE.PORTE4 4 Port E Data Register bit 4
|
||
PORTE.PORTE3 3 Port E Data Register bit 3
|
||
PORTE.PORTE2 2 Port E Data Register bit 2
|
||
PORTE.PORTE1 1 Port E Data Register bit 1
|
||
PORTE.PORTE0 0 Port E Data Register bit 0
|
||
ADCL 0x0004 ADC Data Register Low
|
||
ADCL.ADC7 7
|
||
ADCL.ADC6 6
|
||
ADCL.ADC5 5
|
||
ADCL.ADC4 4
|
||
ADCL.ADC3 3
|
||
ADCL.ADC2 2
|
||
ADCL.ADC1 1
|
||
ADCL.ADC0 0
|
||
ADCH 0x0005 ADC Data Register High
|
||
ADCH.ADC9 9
|
||
ADCH.ADC8 8
|
||
ADCSR 0x0006 ADC Control and Status Register
|
||
ADCSR.ADEN 7 ADC Enable
|
||
ADCSR.ADSC 6 ADC Start Conversion
|
||
ADCSR.ADIF 4 ADC Interrupt Flag
|
||
ADCSR.ADIE 3 ADC Interrupt Enable
|
||
ADCSR.ADPS2 2 ADC Prescaler Select Bit 2
|
||
ADCSR.ADPS1 1 ADC Prescaler Select Bit 1
|
||
ADCSR.ADPS0 0 ADC Prescaler Select Bit 0
|
||
ADMUX 0x0007 ADC Multiplexer Select Register
|
||
ADMUX.MUX2 2 Analog Channel Select Bit 2
|
||
ADMUX.MUX1 1 Analog Channel Select Bit 1
|
||
ADMUX.MUX0 0 Analog Channel Select Bit 0
|
||
ACSR 0x0008 Analog Comparator Control and Status Register
|
||
ACSR.ACD 7 Analog Comparator Disable
|
||
ACSR.ACO 6 Analog Comparator Output
|
||
ACSR.ACI 4 Analog Comparator Interrupt Flag
|
||
ACSR.ACIE 3 Analog Comparator Interrupt Enable
|
||
ACSR.ACIC 2 Analog Comparator Input Capture Enable
|
||
ACSR.ACIS1 1 Analog Comparator Interrupt Mode Select 1
|
||
ACSR.ACIS0 0 Analog Comparator Interrupt Mode Select 0
|
||
UBRR 0x0009 UART Baud Rate Register
|
||
UCR 0x000A UART Control Register
|
||
UCR.RXCIE 7 RX Complete Interrupt Enable
|
||
UCR.TXCIE 6 TX Complete Interrupt Enable
|
||
UCR.UDRIE 5 UART Data Register Empty Interrupt Enable
|
||
UCR.RXEN 4 Receiver Enable
|
||
UCR.TXEN 3 Transmitter Enable
|
||
UCR.CHR9 2 9-bit Characters
|
||
UCR.RXB8 1 Receive Data Bit 8
|
||
UCR.TXB8 0 Transmit Data Bit 8
|
||
USR 0x000B UART Status Register
|
||
USR.RXC 7 UART Receive Complete
|
||
USR.TXC 6 UART Transmit Complete
|
||
USR.UDRE 5 UART Data Register Empty
|
||
USR.FE 4 Framing Error
|
||
USR.OR 3 OverRun
|
||
UDR 0x000C UART I/O Data Register
|
||
SPCR 0x000D SPI Control Register
|
||
SPCR.SPIE 7 SPI Interrupt Enable
|
||
SPCR.SPE 6 SPI Enable
|
||
SPCR.DORD 5 Data Order
|
||
SPCR.MSTR 4 Master/Slave Select
|
||
SPCR.CPOL 3 Clock Polarity
|
||
SPCR.CPHA 2 Clock Phase
|
||
SPCR.SPR1 1 SPI Clock Rate Select 1
|
||
SPCR.SPR0 0 SPI Clock Rate Select 0
|
||
SPSR 0x000E SPI Status Register
|
||
SPSR.SPIF 7 SPI Interrupt Flag
|
||
SPSR.WCOL 6 Write Collision Flag
|
||
SPDR 0x000F SPI Data Register
|
||
PIND 0x0010 Port D Input Pins Address
|
||
PIND.PIND7 7
|
||
PIND.PIND6 6
|
||
PIND.PIND5 5
|
||
PIND.PIND4 4
|
||
PIND.PIND3 3
|
||
PIND.PIND2 2
|
||
PIND.PIND1 1
|
||
PIND.PIND0 0
|
||
DDRD 0x0011 Port D Data Direction Register
|
||
DDRD.DDD7 7 Port D Data Direction Register bit 7
|
||
DDRD.DDD6 6 Port D Data Direction Register bit 6
|
||
DDRD.DDD5 5 Port D Data Direction Register bit 5
|
||
DDRD.DDD4 4 Port D Data Direction Register bit 4
|
||
DDRD.DDD3 3 Port D Data Direction Register bit 3
|
||
DDRD.DDD2 2 Port D Data Direction Register bit 2
|
||
DDRD.DDD1 1 Port D Data Direction Register bit 1
|
||
DDRD.DDD0 0 Port D Data Direction Register bit 0
|
||
PORTD 0x0012 Port D Data Register
|
||
PORTD.PORTD7 7 Port D Data Register bit 7
|
||
PORTD.PORTD6 6 Port D Data Register bit 6
|
||
PORTD.PORTD5 5 Port D Data Register bit 5
|
||
PORTD.PORTD4 4 Port D Data Register bit 4
|
||
PORTD.PORTD3 3 Port D Data Register bit 3
|
||
PORTD.PORTD2 2 Port D Data Register bit 2
|
||
PORTD.PORTD1 1 Port D Data Register bit 1
|
||
PORTD.PORTD0 0 Port D Data Register bit 0
|
||
RESERVED0013 0x0013 RESERVED
|
||
RESERVED0014 0x0014 RESERVED
|
||
PORTC 0x0015 The Port C Data Register
|
||
PORTC.PORTC7 7 Port C Data Register bit 7
|
||
PORTC.PORTC6 6 Port C Data Register bit 6
|
||
PORTC.PORTC5 5 Port C Data Register bit 5
|
||
PORTC.PORTC4 4 Port C Data Register bit 4
|
||
PORTC.PORTC3 3 Port C Data Register bit 3
|
||
PORTC.PORTC2 2 Port C Data Register bit 2
|
||
PORTC.PORTC1 1 Port C Data Register bit 1
|
||
PORTC.PORTC0 0 Port C Data Register bit 0
|
||
PINB 0x0016 Port B Input Pins Address
|
||
DDRB 0x0017 Port B Data Direction Register
|
||
DDRB.DDB7 7 Port B Data Direction Register bit 7
|
||
DDRB.DDB6 6 Port B Data Direction Register bit 6
|
||
DDRB.DDB5 5 Port B Data Direction Register bit 5
|
||
DDRB.DDB4 4 Port B Data Direction Register bit 4
|
||
DDRB.DDB3 3 Port B Data Direction Register bit 3
|
||
DDRB.DDB2 2 Port B Data Direction Register bit 2
|
||
DDRB.DDB1 1 Port B Data Direction Register bit 1
|
||
DDRB.DDB0 0 Port B Data Direction Register bit 0
|
||
PORTB 0x0018 Port B Data Register
|
||
PORTB.PORTB7 7 Port B Data Register bit 7
|
||
PORTB.PORTB6 6 Port B Data Register bit 6
|
||
PORTB.PORTB5 5 Port B Data Register bit 5
|
||
PORTB.PORTB4 4 Port B Data Register bit 4
|
||
PORTB.PORTB3 3 Port B Data Register bit 3
|
||
PORTB.PORTB2 2 Port B Data Register bit 2
|
||
PORTB.PORTB1 1 Port B Data Register bit 1
|
||
PORTB.PORTB0 0 Port B Data Register bit 0
|
||
PINA 0x0019 Port A Input Pins Address
|
||
PINA.PINA7 7
|
||
PINA.PINA6 6
|
||
PINA.PINA5 5
|
||
PINA.PINA4 4
|
||
PINA.PINA3 3
|
||
PINA.PINA2 2
|
||
PINA.PINA1 1
|
||
PINA.PINA0 0
|
||
DDRA 0x001A Port A Data Direction Register
|
||
DDRA.DDA7 7 Port A Data Direction Register bit 7
|
||
DDRA.DDA6 6 Port A Data Direction Register bit 6
|
||
DDRA.DDA5 5 Port A Data Direction Register bit 5
|
||
DDRA.DDA4 4 Port A Data Direction Register bit 4
|
||
DDRA.DDA3 3 Port A Data Direction Register bit 3
|
||
DDRA.DDA2 2 Port A Data Direction Register bit 2
|
||
DDRA.DDA1 1 Port A Data Direction Register bit 1
|
||
DDRA.DDA0 0 Port A Data Direction Register bit 0
|
||
PORTA 0x001B Port A Data Register
|
||
PORTA.PORTA7 7 Port A Data Register bit 7
|
||
PORTA.PORTA6 6 Port A Data Register bit 6
|
||
PORTA.PORTA5 5 Port A Data Register bit 5
|
||
PORTA.PORTA4 4 Port A Data Register bit 4
|
||
PORTA.PORTA3 3 Port A Data Register bit 3
|
||
PORTA.PORTA2 2 Port A Data Register bit 2
|
||
PORTA.PORTA1 1 Port A Data Register bit 1
|
||
PORTA.PORTA0 0 Port A Data Register bit 0
|
||
EECR 0x001C EEPROM Control Register
|
||
EECR.EERIE 3 EEPROM Ready Interrupt Enable
|
||
EECR.EEMWE 2 EEPROM Master Write Enable
|
||
EECR.EEWE 1 EEPROM Write Enable
|
||
EECR.EERE 0 EEPROM Read Enable
|
||
EEDR 0x001D EEPROM Data Register
|
||
EEARL 0x001E EEPROM Address Register Low
|
||
EEARL.EEAR7 7
|
||
EEARL.EEAR6 6
|
||
EEARL.EEAR5 5
|
||
EEARL.EEAR4 4
|
||
EEARL.EEAR3 3
|
||
EEARL.EEAR2 2
|
||
EEARL.EEAR1 1
|
||
EEARL.EEAR0 0
|
||
EEARH 0x001F EEPROM Address Register High
|
||
EEARH.EEAR11 11
|
||
EEARH.EEAR10 10
|
||
EEARH.EEAR9 9
|
||
EEARH.EEAR8 8
|
||
RESERVED0020 0x0020 RESERVED
|
||
WDTCR 0x0021 Watchdog Timer Control Register
|
||
WDTCR.WDTOE 4 Watchdog Turn-off Enable
|
||
WDTCR.WDE 3 Watchdog Enable
|
||
WDTCR.WDP2 2 Watchdog Timer Prescaler 2
|
||
WDTCR.WDP1 1 Watchdog Timer Prescaler 1
|
||
WDTCR.WDP0 0 Watchdog Timer Prescaler 0
|
||
RESERVED0022 0x0022 RESERVED
|
||
OCR2 0x0023 Timer/Counter2 Output Compare Register
|
||
TCNT2 0x0024 Timer/Counter2
|
||
TCCR2 0x0025 Timer/Counter2 Control Register
|
||
TCCR2.PWM2 6 Pulse Width Modulator Enable
|
||
TCCR2.COM21 5 Compare Output Mode, Bit 1
|
||
TCCR2.COM20 4 Compare Output Mode, Bits0
|
||
TCCR2.CTC2 3 Clear Timer/Counter on Compare Match
|
||
TCCR2.CS22 2 Clock Select Bit 2
|
||
TCCR2.CS21 1 Clock Select Bit 1
|
||
TCCR2.CS20 0 Clock Select Bit 0
|
||
ICR1L 0x0026 Timer/Counter1 Input Capture Register Low
|
||
ICR1H 0x0027 Timer/Counter1 Input Capture Register High
|
||
OCR1BL 0x0028 Timer/Counter1 Output Compare Register Low
|
||
OCR1BH 0x0029 Timer/Counter1 Output Compare Register High
|
||
OCR1AL 0x002A Timer/Counter1 Output Compare Register Low
|
||
OCR1AH 0x002B Timer/Counter1 Output Compare Register High
|
||
TCNT1L 0x002C Timer/Counter1 Low
|
||
TCNT1H 0x002D Timer/Counter1 High
|
||
TCCR1B 0x002E Timer/Counter1 Control Register B
|
||
TCCR1B.ICNC1 7 Input Capture1 Noise Canceler (4 CKs)
|
||
TCCR1B.ICES1 6 Input Capture1 Edge Select
|
||
TCCR1B.CTC1 3 Clear Timer/Counter1 on Compare Match
|
||
TCCR1B.CS12 2 Clock Select1, Bit 2
|
||
TCCR1B.CS11 1 Clock Select1, Bit 1
|
||
TCCR1B.CS10 0 Clock Select1, Bit 0
|
||
TCCR1A 0x002F Timer/Counter1 Control Register A
|
||
TCCR1A.COM1A1 7 Compare Output Mode1A, Bit 1
|
||
TCCR1A.COM1A0 6 Compare Output Mode1A, Bit 0
|
||
TCCR1A.COM1B1 5 Compare Output Mode1B, Bit 1
|
||
TCCR1A.COM1B0 4 Compare Output Mode1B, Bit 0
|
||
TCCR1A.PWM11 1 Pulse Width Modulator Select Bit 1
|
||
TCCR1A.PWM10 0 Pulse Width Modulator Select Bit 0
|
||
ASSR 0x0030 Asynchronous Status Register
|
||
ASSR.AS0 3 Asynchronous Timer/Counter0
|
||
ASSR.TCN0UB 2 Timer/Counter0 Update Busy
|
||
ASSR.OCR0UB 1 Output Compare Register0 Update Busy
|
||
ASSR.TCR0UB 0 Timer/Counter Control Register0 Update Busy
|
||
OCR0 0x0031 Timer/Counter0 Output Compare Register
|
||
TCNT0 0x0032 Timer/Counter0
|
||
TCCR0 0x0033 Timer/Counter0 Control Register
|
||
TCCR0.PWM0 6 Pulse Width Modulator Enable
|
||
TCCR0.COM01 5 Compare Output Mode, Bit 1
|
||
TCCR0.COM00 4 Compare Output Mode, Bit 0
|
||
TCCR0.CTC0 3 Clear Timer/Counter on Compare Match
|
||
TCCR0.CS02 2 Clock Select Bit 2
|
||
TCCR0.CS01 1 Clock Select Bit 1
|
||
TCCR0.CS00 0 Clock Select Bit 0
|
||
MCUSR 0x0034 MCU Status Register
|
||
MCUSR.EXTRF 1 External Reset Flag
|
||
MCUSR.PORF 0 Power-on Reset Flag
|
||
MCUCR 0x0035 MCU Control Register
|
||
MCUCR.SRE 7 External SRAM Enable
|
||
MCUCR.SRW 6 External SRAM Wait State
|
||
MCUCR.SE 5 Sleep Enable
|
||
MCUCR.SM1 4 Sleep Mode Select Bit 1
|
||
MCUCR.SM0 3 Sleep Mode Select Bit 0
|
||
TIFR 0x0036 Timer/Counter Interrupt Flag Register
|
||
TIFR.OCF2 7 Output Compare Flag 2
|
||
TIFR.TOV2 6 Timer/Counter2 Overflow Flag
|
||
TIFR.ICF1 5 Input Capture Flag 1
|
||
TIFR.OCF1A 4 Output Compare Flag 1A
|
||
TIFR.OCF1B 3 Output Compare Flag 1B
|
||
TIFR.TOV1 2 Timer/Counter1 Overflow Flag
|
||
TIFR.OCF0 1 Output Compare Flag 0
|
||
TIFR.TOV0 0 Timer/Counter0 Overflow Flag
|
||
TIMSK 0x0037 Timer/Counter Interrupt Mask Register
|
||
TIMSK.OCIE2 7 Timer/Counter2 Output Compare Interrupt Enable
|
||
TIMSK.TOIE2 6 Timer/Counter2 Overflow Interrupt Enable
|
||
TIMSK.TICIE1 5 Timer/Counter1 Input Capture Interrupt Enable
|
||
TIMSK.OCIE1A 4 Timer/Counter1 Output CompareA Match Interrupt Enable
|
||
TIMSK.OCIE1B 3 Timer/Counter1 Output CompareB Match Interrupt Enable
|
||
TIMSK.TOIE1 2 Timer/Counter1 Overflow Interrupt Enable
|
||
TIMSK.OCIE0 1 Timer/Counter0 Output Compare Interrupt Enable
|
||
TIMSK.TOIE0 0 Timer/Counter0 Overflow Interrupt Enable
|
||
EIFR 0x0038 External Interrupt Flag Register
|
||
EIFR.INTF7 7 External Interrupt 7 Flag
|
||
EIFR.INTF6 6 External Interrupt 6 Flag
|
||
EIFR.INTF5 5 External Interrupt 5 Flag
|
||
EIFR.INTF4 4 External Interrupt 4 Flag
|
||
EIMSK 0x0039 External Interrupt Mask Register
|
||
EIMSK.INT7 7 External Interrupt Request 7 Enable
|
||
EIMSK.INT6 6 External Interrupt Request 6 Enable
|
||
EIMSK.INT5 5 External Interrupt Request 5 Enable
|
||
EIMSK.INT4 4 External Interrupt Request 4 Enable
|
||
EIMSK.INT3 3 External Interrupt Request 3 Enable
|
||
EIMSK.INT2 2 External Interrupt Request 2 Enable
|
||
EIMSK.INT1 1 External Interrupt Request 1 Enable
|
||
EIMSK.INT0 0 External Interrupt Request 0 Enable
|
||
EICR 0x003A External Interrupt Control Register
|
||
EICR.ISC71 7 External Interrupt 7 Sense Control Bit 1
|
||
EICR.ISC70 6 External Interrupt 7 Sense Control Bit 0
|
||
EICR.ISC61 5 External Interrupt 6 Sense Control Bit 1
|
||
EICR.ISC60 4 External Interrupt 6 Sense Control Bit 0
|
||
EICR.ISC51 3 External Interrupt 5 Sense Control Bit 1
|
||
EICR.ISC50 2 External Interrupt 5 Sense Control Bit 0
|
||
EICR.ISC41 1 External Interrupt 4 Sense Control Bit 1
|
||
EICR.ISC40 0 External Interrupt 4 Sense Control Bit 0
|
||
RAMPZ 0x003B RAM Page Z Select Register
|
||
RAMPZ.RAMPZ0 0
|
||
XDIV 0x003C XTAL Divide Control Register
|
||
XDIV.XDIVEN 7 XTAL Divide Enable
|
||
XDIV.XDIV6 6 XTAL Divide Select Bit 6
|
||
XDIV.XDIV5 5 XTAL Divide Select Bit 5
|
||
XDIV.XDIV4 4 XTAL Divide Select Bit 4
|
||
XDIV.XDIV3 3 XTAL Divide Select Bit 3
|
||
XDIV.XDIV2 2 XTAL Divide Select Bit 2
|
||
XDIV.XDIV1 1 XTAL Divide Select Bit 1
|
||
XDIV.XDIV0 0 XTAL Divide Select Bit 0
|
||
SPL 0x003D Stack Pointer Low
|
||
SPL.SP7 7
|
||
SPL.SP6 6
|
||
SPL.SP5 5
|
||
SPL.SP4 4
|
||
SPL.SP3 3
|
||
SPL.SP2 2
|
||
SPL.SP1 1
|
||
SPL.SP0 0
|
||
SPH 0x003E Stack Pointer High
|
||
SPH.SP15 15
|
||
SPH.SP14 14
|
||
SPH.SP13 13
|
||
SPH.SP12 12
|
||
SPH.SP11 11
|
||
SPH.SP10 10
|
||
SPH.SP9 9
|
||
SPH.SP8 8
|
||
SREG 0x003F Status Register
|
||
SREG.I 7 Global Interrupt Enable
|
||
SREG.T 6 Bit Copy Storage
|
||
SREG.H 5 Half-carry Flag
|
||
SREG.S 4 Sign Bit
|
||
SREG.V 3 Two's Complement Overflow Flag
|
||
SREG.N 2 Negative Flag
|
||
SREG.Z 1 Zero Flag
|
||
SREG.C 0 Carry Flag
|
||
|
||
; PINF 0x0020 Port F Input Pins Address
|
||
; PINF.PINF7 7
|
||
; PINF.PINF6 6
|
||
; PINF.PINF5 5
|
||
; PINF.PINF4 4
|
||
; PINF.PINF3 3
|
||
; PINF.PINF2 2
|
||
; PINF.PINF1 1
|
||
; PINF.PINF0 0
|
||
; PINE 0x0021 Port E Input Pins Address
|
||
; PINE.PINE7 7
|
||
; PINE.PINE6 6
|
||
; PINE.PINE5 5
|
||
; PINE.PINE4 4
|
||
; PINE.PINE3 3
|
||
; PINE.PINE2 2
|
||
; PINE.PINE1 1
|
||
; PINE.PINE0 0
|
||
; DDRE 0x0022 Port E Data Direction Register
|
||
; DDRE.DDE7 7 Port E Data Direction Register bit 7
|
||
; DDRE.DDE6 6 Port E Data Direction Register bit 6
|
||
; DDRE.DDE5 5 Port E Data Direction Register bit 5
|
||
; DDRE.DDE4 4 Port E Data Direction Register bit 4
|
||
; DDRE.DDE3 3 Port E Data Direction Register bit 3
|
||
; DDRE.DDE2 2 Port E Data Direction Register bit 2
|
||
; DDRE.DDE1 1 Port E Data Direction Register bit 1
|
||
; DDRE.DDE0 0 Port E Data Direction Register bit 0
|
||
; PORTE 0x0023 Port E Data Register
|
||
; PORTE.PORTE7 7 Port E Data Register bit 7
|
||
; PORTE.PORTE6 6 Port E Data Register bit 6
|
||
; PORTE.PORTE5 5 Port E Data Register bit 5
|
||
; PORTE.PORTE4 4 Port E Data Register bit 4
|
||
; PORTE.PORTE3 3 Port E Data Register bit 3
|
||
; PORTE.PORTE2 2 Port E Data Register bit 2
|
||
; PORTE.PORTE1 1 Port E Data Register bit 1
|
||
; PORTE.PORTE0 0 Port E Data Register bit 0
|
||
; ADCL 0x0024 ADC Data Register Low
|
||
; ADCL.ADC7 7
|
||
; ADCL.ADC6 6
|
||
; ADCL.ADC5 5
|
||
; ADCL.ADC4 4
|
||
; ADCL.ADC3 3
|
||
; ADCL.ADC2 2
|
||
; ADCL.ADC1 1
|
||
; ADCL.ADC0 0
|
||
; ADCH 0x0025 ADC Data Register High
|
||
; ADCH.ADC9 9
|
||
; ADCH.ADC8 8
|
||
; ADCSR 0x0026 ADC Control and Status Register
|
||
; ADCSR.ADEN 7 ADC Enable
|
||
; ADCSR.ADSC 6 ADC Start Conversion
|
||
; ADCSR.ADIF 4 ADC Interrupt Flag
|
||
; ADCSR.ADIE 3 ADC Interrupt Enable
|
||
; ADCSR.ADPS2 2 ADC Prescaler Select Bit 2
|
||
; ADCSR.ADPS1 1 ADC Prescaler Select Bit 1
|
||
; ADCSR.ADPS0 0 ADC Prescaler Select Bit 0
|
||
; ADMUX 0x0027 ADC Multiplexer Select Register
|
||
; ADMUX.MUX2 2 Analog Channel Select Bit 2
|
||
; ADMUX.MUX1 1 Analog Channel Select Bit 1
|
||
; ADMUX.MUX0 0 Analog Channel Select Bit 0
|
||
; ACSR 0x0028 Analog Comparator Control and Status Register
|
||
; ACSR.ACD 7 Analog Comparator Disable
|
||
; ACSR.ACO 6 Analog Comparator Output
|
||
; ACSR.ACI 4 Analog Comparator Interrupt Flag
|
||
; ACSR.ACIE 3 Analog Comparator Interrupt Enable
|
||
; ACSR.ACIC 2 Analog Comparator Input Capture Enable
|
||
; ACSR.ACIS1 1 Analog Comparator Interrupt Mode Select 1
|
||
; ACSR.ACIS0 0 Analog Comparator Interrupt Mode Select 0
|
||
; UBRR 0x0029 UART Baud Rate Register
|
||
; UCR 0x002A UART Control Register
|
||
; UCR.RXCIE 7 RX Complete Interrupt Enable
|
||
; UCR.TXCIE 6 TX Complete Interrupt Enable
|
||
; UCR.UDRIE 5 UART Data Register Empty Interrupt Enable
|
||
; UCR.RXEN 4 Receiver Enable
|
||
; UCR.TXEN 3 Transmitter Enable
|
||
; UCR.CHR9 2 9-bit Characters
|
||
; UCR.RXB8 1 Receive Data Bit 8
|
||
; UCR.TXB8 0 Transmit Data Bit 8
|
||
; USR 0x002B UART Status Register
|
||
; USR.RXC 7 UART Receive Complete
|
||
; USR.TXC 6 UART Transmit Complete
|
||
; USR.UDRE 5 UART Data Register Empty
|
||
; USR.FE 4 Framing Error
|
||
; USR.OR 3 OverRun
|
||
; UDR 0x002C UART I/O Data Register
|
||
; SPCR 0x002D SPI Control Register
|
||
; SPCR.SPIE 7 SPI Interrupt Enable
|
||
; SPCR.SPE 6 SPI Enable
|
||
; SPCR.DORD 5 Data Order
|
||
; SPCR.MSTR 4 Master/Slave Select
|
||
; SPCR.CPOL 3 Clock Polarity
|
||
; SPCR.CPHA 2 Clock Phase
|
||
; SPCR.SPR1 1 SPI Clock Rate Select 1
|
||
; SPCR.SPR0 0 SPI Clock Rate Select 0
|
||
; SPSR 0x002E SPI Status Register
|
||
; SPSR.SPIF 7 SPI Interrupt Flag
|
||
; SPSR.WCOL 6 Write Collision Flag
|
||
; SPDR 0x002F SPI Data Register
|
||
; PIND 0x0030 Port D Input Pins Address
|
||
; PIND.PIND7 7
|
||
; PIND.PIND6 6
|
||
; PIND.PIND5 5
|
||
; PIND.PIND4 4
|
||
; PIND.PIND3 3
|
||
; PIND.PIND2 2
|
||
; PIND.PIND1 1
|
||
; PIND.PIND0 0
|
||
; DDRD 0x0031 Port D Data Direction Register
|
||
; DDRD.DDD7 7 Port D Data Direction Register bit 7
|
||
; DDRD.DDD6 6 Port D Data Direction Register bit 6
|
||
; DDRD.DDD5 5 Port D Data Direction Register bit 5
|
||
; DDRD.DDD4 4 Port D Data Direction Register bit 4
|
||
; DDRD.DDD3 3 Port D Data Direction Register bit 3
|
||
; DDRD.DDD2 2 Port D Data Direction Register bit 2
|
||
; DDRD.DDD1 1 Port D Data Direction Register bit 1
|
||
; DDRD.DDD0 0 Port D Data Direction Register bit 0
|
||
; PORTD 0x0032 Port D Data Register
|
||
; PORTD.PORTD7 7 Port D Data Register bit 7
|
||
; PORTD.PORTD6 6 Port D Data Register bit 6
|
||
; PORTD.PORTD5 5 Port D Data Register bit 5
|
||
; PORTD.PORTD4 4 Port D Data Register bit 4
|
||
; PORTD.PORTD3 3 Port D Data Register bit 3
|
||
; PORTD.PORTD2 2 Port D Data Register bit 2
|
||
; PORTD.PORTD1 1 Port D Data Register bit 1
|
||
; PORTD.PORTD0 0 Port D Data Register bit 0
|
||
; RESERVED0033 0x0033 RESERVED
|
||
; RESERVED0034 0x0034 RESERVED
|
||
; PORTC 0x0035 The Port C Data Register
|
||
; PORTC.PORTC7 7 Port C Data Register bit 7
|
||
; PORTC.PORTC6 6 Port C Data Register bit 6
|
||
; PORTC.PORTC5 5 Port C Data Register bit 5
|
||
; PORTC.PORTC4 4 Port C Data Register bit 4
|
||
; PORTC.PORTC3 3 Port C Data Register bit 3
|
||
; PORTC.PORTC2 2 Port C Data Register bit 2
|
||
; PORTC.PORTC1 1 Port C Data Register bit 1
|
||
; PORTC.PORTC0 0 Port C Data Register bit 0
|
||
; PINB 0x0036 Port B Input Pins Address
|
||
; DDRB 0x0037 Port B Data Direction Register
|
||
; DDRB.DDB7 7 Port B Data Direction Register bit 7
|
||
; DDRB.DDB6 6 Port B Data Direction Register bit 6
|
||
; DDRB.DDB5 5 Port B Data Direction Register bit 5
|
||
; DDRB.DDB4 4 Port B Data Direction Register bit 4
|
||
; DDRB.DDB3 3 Port B Data Direction Register bit 3
|
||
; DDRB.DDB2 2 Port B Data Direction Register bit 2
|
||
; DDRB.DDB1 1 Port B Data Direction Register bit 1
|
||
; DDRB.DDB0 0 Port B Data Direction Register bit 0
|
||
; PORTB 0x0038 Port B Data Register
|
||
; PORTB.PORTB7 7 Port B Data Register bit 7
|
||
; PORTB.PORTB6 6 Port B Data Register bit 6
|
||
; PORTB.PORTB5 5 Port B Data Register bit 5
|
||
; PORTB.PORTB4 4 Port B Data Register bit 4
|
||
; PORTB.PORTB3 3 Port B Data Register bit 3
|
||
; PORTB.PORTB2 2 Port B Data Register bit 2
|
||
; PORTB.PORTB1 1 Port B Data Register bit 1
|
||
; PORTB.PORTB0 0 Port B Data Register bit 0
|
||
; PINA 0x0039 Port A Input Pins Address
|
||
; PINA.PINA7 7
|
||
; PINA.PINA6 6
|
||
; PINA.PINA5 5
|
||
; PINA.PINA4 4
|
||
; PINA.PINA3 3
|
||
; PINA.PINA2 2
|
||
; PINA.PINA1 1
|
||
; PINA.PINA0 0
|
||
; DDRA 0x003A Port A Data Direction Register
|
||
; DDRA.DDA7 7 Port A Data Direction Register bit 7
|
||
; DDRA.DDA6 6 Port A Data Direction Register bit 6
|
||
; DDRA.DDA5 5 Port A Data Direction Register bit 5
|
||
; DDRA.DDA4 4 Port A Data Direction Register bit 4
|
||
; DDRA.DDA3 3 Port A Data Direction Register bit 3
|
||
; DDRA.DDA2 2 Port A Data Direction Register bit 2
|
||
; DDRA.DDA1 1 Port A Data Direction Register bit 1
|
||
; DDRA.DDA0 0 Port A Data Direction Register bit 0
|
||
; PORTA 0x003B Port A Data Register
|
||
; PORTA.PORTA7 7 Port A Data Register bit 7
|
||
; PORTA.PORTA6 6 Port A Data Register bit 6
|
||
; PORTA.PORTA5 5 Port A Data Register bit 5
|
||
; PORTA.PORTA4 4 Port A Data Register bit 4
|
||
; PORTA.PORTA3 3 Port A Data Register bit 3
|
||
; PORTA.PORTA2 2 Port A Data Register bit 2
|
||
; PORTA.PORTA1 1 Port A Data Register bit 1
|
||
; PORTA.PORTA0 0 Port A Data Register bit 0
|
||
; EECR 0x003C EEPROM Control Register
|
||
; EECR.EERIE 3 EEPROM Ready Interrupt Enable
|
||
; EECR.EEMWE 2 EEPROM Master Write Enable
|
||
; EECR.EEWE 1 EEPROM Write Enable
|
||
; EECR.EERE 0 EEPROM Read Enable
|
||
; EEDR 0x003D EEPROM Data Register
|
||
; EEARL 0x003E EEPROM Address Register Low
|
||
; EEARL.EEAR7 7
|
||
; EEARL.EEAR6 6
|
||
; EEARL.EEAR5 5
|
||
; EEARL.EEAR4 4
|
||
; EEARL.EEAR3 3
|
||
; EEARL.EEAR2 2
|
||
; EEARL.EEAR1 1
|
||
; EEARL.EEAR0 0
|
||
; EEARH 0x003F EEPROM Address Register High
|
||
; EEARH.EEAR11 11
|
||
; EEARH.EEAR10 10
|
||
; EEARH.EEAR9 9
|
||
; EEARH.EEAR8 8
|
||
; RESERVED0040 0x0040 RESERVED
|
||
; WDTCR 0x0041 Watchdog Timer Control Register
|
||
; WDTCR.WDTOE 4 Watchdog Turn-off Enable
|
||
; WDTCR.WDE 3 Watchdog Enable
|
||
; WDTCR.WDP2 2 Watchdog Timer Prescaler 2
|
||
; WDTCR.WDP1 1 Watchdog Timer Prescaler 1
|
||
; WDTCR.WDP0 0 Watchdog Timer Prescaler 0
|
||
; RESERVED0042 0x0042 RESERVED
|
||
; OCR2 0x0043 Timer/Counter2 Output Compare Register
|
||
; TCNT2 0x0044 Timer/Counter2
|
||
; TCCR2 0x0045 Timer/Counter2 Control Register
|
||
; TCCR2.PWM2 6 Pulse Width Modulator Enable
|
||
; TCCR2.COM21 5 Compare Output Mode, Bit 1
|
||
; TCCR2.COM20 4 Compare Output Mode, Bits0
|
||
; TCCR2.CTC2 3 Clear Timer/Counter on Compare Match
|
||
; TCCR2.CS22 2 Clock Select Bit 2
|
||
; TCCR2.CS21 1 Clock Select Bit 1
|
||
; TCCR2.CS20 0 Clock Select Bit 0
|
||
; ICR1L 0x0046 Timer/Counter1 Input Capture Register Low
|
||
; ICR1H 0x0047 Timer/Counter1 Input Capture Register High
|
||
; OCR1BL 0x0048 Timer/Counter1 Output Compare Register Low
|
||
; OCR1BH 0x0049 Timer/Counter1 Output Compare Register High
|
||
; OCR1AL 0x004A Timer/Counter1 Output Compare Register Low
|
||
; OCR1AH 0x004B Timer/Counter1 Output Compare Register High
|
||
; TCNT1L 0x004C Timer/Counter1 Low
|
||
; TCNT1H 0x004D Timer/Counter1 High
|
||
; TCCR1B 0x004E Timer/Counter1 Control Register B
|
||
; TCCR1B.ICNC1 7 Input Capture1 Noise Canceler (4 CKs)
|
||
; TCCR1B.ICES1 6 Input Capture1 Edge Select
|
||
; TCCR1B.CTC1 3 Clear Timer/Counter1 on Compare Match
|
||
; TCCR1B.CS12 2 Clock Select1, Bit 2
|
||
; TCCR1B.CS11 1 Clock Select1, Bit 1
|
||
; TCCR1B.CS10 0 Clock Select1, Bit 0
|
||
; TCCR1A 0x004F Timer/Counter1 Control Register A
|
||
; TCCR1A.COM1A1 7 Compare Output Mode1A, Bit 1
|
||
; TCCR1A.COM1A0 6 Compare Output Mode1A, Bit 0
|
||
; TCCR1A.COM1B1 5 Compare Output Mode1B, Bit 1
|
||
; TCCR1A.COM1B0 4 Compare Output Mode1B, Bit 0
|
||
; TCCR1A.PWM11 1 Pulse Width Modulator Select Bit 1
|
||
; TCCR1A.PWM10 0 Pulse Width Modulator Select Bit 0
|
||
; ASSR 0x0050 Asynchronous Status Register
|
||
; ASSR.AS0 3 Asynchronous Timer/Counter0
|
||
; ASSR.TCN0UB 2 Timer/Counter0 Update Busy
|
||
; ASSR.OCR0UB 1 Output Compare Register0 Update Busy
|
||
; ASSR.TCR0UB 0 Timer/Counter Control Register0 Update Busy
|
||
; OCR0 0x0051 Timer/Counter0 Output Compare Register
|
||
; TCNT0 0x0052 Timer/Counter0
|
||
; TCCR0 0x0053 Timer/Counter0 Control Register
|
||
; TCCR0.PWM0 6 Pulse Width Modulator Enable
|
||
; TCCR0.COM01 5 Compare Output Mode, Bit 1
|
||
; TCCR0.COM00 4 Compare Output Mode, Bit 0
|
||
; TCCR0.CTC0 3 Clear Timer/Counter on Compare Match
|
||
; TCCR0.CS02 2 Clock Select Bit 2
|
||
; TCCR0.CS01 1 Clock Select Bit 1
|
||
; TCCR0.CS00 0 Clock Select Bit 0
|
||
; MCUSR 0x0054 MCU Status Register
|
||
; MCUSR.EXTRF 1 External Reset Flag
|
||
; MCUSR.PORF 0 Power-on Reset Flag
|
||
; MCUCR 0x0055 MCU Control Register
|
||
; MCUCR.SRE 7 External SRAM Enable
|
||
; MCUCR.SRW 6 External SRAM Wait State
|
||
; MCUCR.SE 5 Sleep Enable
|
||
; MCUCR.SM1 4 Sleep Mode Select Bit 1
|
||
; MCUCR.SM0 3 Sleep Mode Select Bit 0
|
||
; TIFR 0x0056 Timer/Counter Interrupt Flag Register
|
||
; TIFR.OCF2 7 Output Compare Flag 2
|
||
; TIFR.TOV2 6 Timer/Counter2 Overflow Flag
|
||
; TIFR.ICF1 5 Input Capture Flag 1
|
||
; TIFR.OCF1A 4 Output Compare Flag 1A
|
||
; TIFR.OCF1B 3 Output Compare Flag 1B
|
||
; TIFR.TOV1 2 Timer/Counter1 Overflow Flag
|
||
; TIFR.OCF0 1 Output Compare Flag 0
|
||
; TIFR.TOV0 0 Timer/Counter0 Overflow Flag
|
||
; TIMSK 0x0057 Timer/Counter Interrupt Mask Register
|
||
; TIMSK.OCIE2 7 Timer/Counter2 Output Compare Interrupt Enable
|
||
; TIMSK.TOIE2 6 Timer/Counter2 Overflow Interrupt Enable
|
||
; TIMSK.TICIE1 5 Timer/Counter1 Input Capture Interrupt Enable
|
||
; TIMSK.OCIE1A 4 Timer/Counter1 Output CompareA Match Interrupt Enable
|
||
; TIMSK.OCIE1B 3 Timer/Counter1 Output CompareB Match Interrupt Enable
|
||
; TIMSK.TOIE1 2 Timer/Counter1 Overflow Interrupt Enable
|
||
; TIMSK.OCIE0 1 Timer/Counter0 Output Compare Interrupt Enable
|
||
; TIMSK.TOIE0 0 Timer/Counter0 Overflow Interrupt Enable
|
||
; EIFR 0x0058 External Interrupt Flag Register
|
||
; EIFR.INTF7 7 External Interrupt 7 Flag
|
||
; EIFR.INTF6 6 External Interrupt 6 Flag
|
||
; EIFR.INTF5 5 External Interrupt 5 Flag
|
||
; EIFR.INTF4 4 External Interrupt 4 Flag
|
||
; EIMSK 0x0059 External Interrupt Mask Register
|
||
; EIMSK.INT7 7 External Interrupt Request 7 Enable
|
||
; EIMSK.INT6 6 External Interrupt Request 6 Enable
|
||
; EIMSK.INT5 5 External Interrupt Request 5 Enable
|
||
; EIMSK.INT4 4 External Interrupt Request 4 Enable
|
||
; EIMSK.INT3 3 External Interrupt Request 3 Enable
|
||
; EIMSK.INT2 2 External Interrupt Request 2 Enable
|
||
; EIMSK.INT1 1 External Interrupt Request 1 Enable
|
||
; EIMSK.INT0 0 External Interrupt Request 0 Enable
|
||
; EICR 0x005A External Interrupt Control Register
|
||
; EICR.ISC71 7 External Interrupt 7 Sense Control Bit 1
|
||
; EICR.ISC70 6 External Interrupt 7 Sense Control Bit 0
|
||
; EICR.ISC61 5 External Interrupt 6 Sense Control Bit 1
|
||
; EICR.ISC60 4 External Interrupt 6 Sense Control Bit 0
|
||
; EICR.ISC51 3 External Interrupt 5 Sense Control Bit 1
|
||
; EICR.ISC50 2 External Interrupt 5 Sense Control Bit 0
|
||
; EICR.ISC41 1 External Interrupt 4 Sense Control Bit 1
|
||
; EICR.ISC40 0 External Interrupt 4 Sense Control Bit 0
|
||
; RAMPZ 0x005B RAM Page Z Select Register
|
||
; RAMPZ.RAMPZ0 0
|
||
; XDIV 0x005C XTAL Divide Control Register
|
||
; XDIV.XDIVEN 7 XTAL Divide Enable
|
||
; XDIV.XDIV6 6 XTAL Divide Select Bit 6
|
||
; XDIV.XDIV5 5 XTAL Divide Select Bit 5
|
||
; XDIV.XDIV4 4 XTAL Divide Select Bit 4
|
||
; XDIV.XDIV3 3 XTAL Divide Select Bit 3
|
||
; XDIV.XDIV2 2 XTAL Divide Select Bit 2
|
||
; XDIV.XDIV1 1 XTAL Divide Select Bit 1
|
||
; XDIV.XDIV0 0 XTAL Divide Select Bit 0
|
||
; SPL 0x005D Stack Pointer Low
|
||
; SPL.SP7 7
|
||
; SPL.SP6 6
|
||
; SPL.SP5 5
|
||
; SPL.SP4 4
|
||
; SPL.SP3 3
|
||
; SPL.SP2 2
|
||
; SPL.SP1 1
|
||
; SPL.SP0 0
|
||
; SPH 0x005E Stack Pointer High
|
||
; SPH.SP15 15
|
||
; SPH.SP14 14
|
||
; SPH.SP13 13
|
||
; SPH.SP12 12
|
||
; SPH.SP11 11
|
||
; SPH.SP10 10
|
||
; SPH.SP9 9
|
||
; SPH.SP8 8
|
||
; SREG 0x005F Status Register
|
||
; SREG.I 7 Global Interrupt Enable
|
||
; SREG.T 6 Bit Copy Storage
|
||
; SREG.H 5 Half-carry Flag
|
||
; SREG.S 4 Sign Bit
|
||
; SREG.V 3 Two's Complement Overflow Flag
|
||
; SREG.N 2 Negative Flag
|
||
; SREG.Z 1 Zero Flag
|
||
; SREG.C 0 Carry Flag
|
||
|
||
|
||
.ATmega128_L
|
||
SUBARCH=51
|
||
; doc2467.pdf
|
||
;
|
||
|
||
ROM=131072
|
||
RAM=4096
|
||
EEPROM=4096
|
||
|
||
; MEMORY MAP
|
||
; Memory Configuration A
|
||
area DATA FSR_1 0x0000:0x0020 32 Registers
|
||
area DATA FSR_2 0x0020:0x0060 64 I/O Registers
|
||
area DATA FSR_3 0x0060:0x00A0 160 Ext I/O Reg.
|
||
area BSS RESERVED 0x00A0:0x0100
|
||
area DATA I_SRAM 0x0100:0x1100 Internal SRAM
|
||
area DATA E_SRAM 0x1100:0x10000 External SRAM
|
||
; Memory Configuration B
|
||
; area DATA FSR_1 0x0000:0x0020 32 Registers
|
||
; area DATA FSR_2 0x0020:0x0060 64 I/O Registers
|
||
; area DATA I_SRAM 0x0060:0x1000 Internal SRAM
|
||
; area DATA E_SRAM 0x1000:0x10000 External SRAM
|
||
|
||
|
||
; Interrupt and reset vector assignments
|
||
entry __RESET 0x0000 External Pin, Power-on Reset, Brown-out Reset, Watchdog Reset, and JTAG AVR Reset
|
||
entry INT0_ 0x0002 External Interrupt Request 0
|
||
entry INT1_ 0x0004 External Interrupt Request 1
|
||
entry INT2_ 0x0006 External Interrupt Request 2
|
||
entry INT3_ 0x0008 External Interrupt Request 3
|
||
entry INT4_ 0x000A External Interrupt Request 4
|
||
entry INT5_ 0x000C External Interrupt Request 5
|
||
entry INT6_ 0x000E External Interrupt Request 6
|
||
entry INT7_ 0x0010 External Interrupt Request 7
|
||
entry TIMER2_COMP 0x0012 Timer/Counter2 Compare Match
|
||
entry TIMER2_OVF 0x0014 Timer/Counter2 Overflow
|
||
entry TIMER1_CAPT 0x0016 Timer/Counter1 Capture Event
|
||
entry TIMER1_COMPA 0x0018 Timer/Counter1 Compare Match A
|
||
entry TIMER1_COMPB 0x001A Timer/Counter1 Compare Match B
|
||
entry TIMER1_OVF 0x001C Timer/Counter1 Overflow
|
||
entry TIMER0_COMP 0x001E Timer/Counter0 Compare Match
|
||
entry TIMER0_OVF 0x0020 Timer/Counter0 Overflow
|
||
entry SPI_STC 0x0022 SPI Serial Transfer Complete
|
||
entry USART0_RX 0x0024 USART0, Rx Complete
|
||
entry USART0_UDRE 0x0026 USART0 Data Register Empty
|
||
entry USART0_TX 0x0028 USART0, Tx Complete
|
||
entry ADC_ 0x002A ADC Conversion Complete
|
||
entry EE_READY 0x002C EEPROM Ready
|
||
entry ANALOG_COMP 0x002E Analog Comparator
|
||
entry TIMER1_COMPC 0x0030 Timer/Countre1 Compare Match C
|
||
entry TIMER3_CAPT 0x0032 Timer/Counter3 Capture Event
|
||
entry TIMER3_COMPA 0x0034 Timer/Counter3 Compare Match A
|
||
entry TIMER3_COMPB 0x0036 Timer/Counter3 Compare Match B
|
||
entry TIMER3_COMPC 0x0038 Timer/Counter3 Compare Match C
|
||
entry TIMER3_OVF 0x003A Timer/Counter3 Overflow
|
||
entry USART1_RX 0x003C USART1, Rx Complete
|
||
entry USART1_UDRE 0x003E USART1 Data Register Empty
|
||
entry USART1_TX 0x0040 USART1, Tx Complete
|
||
entry TWI_ 0x0042 Two-wire Serial Interface
|
||
entry SPM_READY 0x0044 Store Program Memory Ready
|
||
|
||
|
||
; INPUT/OUTPUT PORTS
|
||
PINF 0x0000 Port F Input Pins Address
|
||
PINF.PINF7 7
|
||
PINF.PINF6 6
|
||
PINF.PINF5 5
|
||
PINF.PINF4 4
|
||
PINF.PINF3 3
|
||
PINF.PINF2 2
|
||
PINF.PINF1 1
|
||
PINF.PINF0 0
|
||
PINE 0x0001 Port E Input Pins Address
|
||
PINE.PINE7 7
|
||
PINE.PINE6 6
|
||
PINE.PINE5 5
|
||
PINE.PINE4 4
|
||
PINE.PINE3 3
|
||
PINE.PINE2 2
|
||
PINE.PINE1 1
|
||
PINE.PINE0 0
|
||
DDRE 0x0002 Port E Data Direction Register
|
||
DDRE.DDE7 7 Port E Data Direction Register bit 7
|
||
DDRE.DDE6 6 Port E Data Direction Register bit 6
|
||
DDRE.DDE5 5 Port E Data Direction Register bit 5
|
||
DDRE.DDE4 4 Port E Data Direction Register bit 4
|
||
DDRE.DDE3 3 Port E Data Direction Register bit 3
|
||
DDRE.DDE2 2 Port E Data Direction Register bit 2
|
||
DDRE.DDE1 1 Port E Data Direction Register bit 1
|
||
DDRE.DDE0 0 Port E Data Direction Register bit 0
|
||
PORTE 0x0003 Port E Data Register
|
||
PORTE.PORTE7 7 Port E Data Register bit 7
|
||
PORTE.PORTE6 6 Port E Data Register bit 6
|
||
PORTE.PORTE5 5 Port E Data Register bit 5
|
||
PORTE.PORTE4 4 Port E Data Register bit 4
|
||
PORTE.PORTE3 3 Port E Data Register bit 3
|
||
PORTE.PORTE2 2 Port E Data Register bit 2
|
||
PORTE.PORTE1 1 Port E Data Register bit 1
|
||
PORTE.PORTE0 0 Port E Data Register bit 0
|
||
ADCL 0x0004 The ADC Data Register Low (ADLAR = 0)
|
||
ADCL.ADC7 7
|
||
ADCL.ADC6 6
|
||
ADCL.ADC5 5
|
||
ADCL.ADC4 4
|
||
ADCL.ADC3 3
|
||
ADCL.ADC2 2
|
||
ADCL.ADC1 1
|
||
ADCL.ADC0 0
|
||
ADCH 0x0005 The ADC Data Register High (ADLAR = 0)
|
||
ADCH.ADC9 9
|
||
ADCH.ADC8 8
|
||
; ADCL 0x0004 The ADC Data Register Low (ADLAR = 1)
|
||
; ADCL.ADC1 7
|
||
; ADCL.ADC0 6
|
||
; ADCH 0x0005 The ADC Data Register High (ADLAR = 1)
|
||
; ADCH.ADC9 15
|
||
; ADCH.ADC8 14
|
||
; ADCH.ADC7 13
|
||
; ADCH.ADC6 12
|
||
; ADCH.ADC5 11
|
||
; ADCH.ADC4 10
|
||
; ADCH.ADC3 9
|
||
; ADCH.ADC2 8
|
||
ADCSRA 0x0006 ADC Control and Status Register A
|
||
ADCSRA.ADEN 7 ADC Enable
|
||
ADCSRA.ADSC 6 ADC Start Conversion
|
||
ADCSRA.ADFR 5 ADC Free Running Select
|
||
ADCSRA.ADIF 4 ADC Interrupt Flag
|
||
ADCSRA.ADIE 3 ADC Interrupt Enable
|
||
ADCSRA.ADPS2 2 ADC Prescaler Select Bit
|
||
ADCSRA.ADPS1 1 ADC Prescaler Select Bit
|
||
ADCSRA.ADPS0 0 ADC Prescaler Select Bit
|
||
ADMUX 0x0007 ADC Multiplexer Selection Register
|
||
ADMUX.REFS1 7 Reference Selection Bit 1
|
||
ADMUX.REFS0 6 Reference Selection Bit 0
|
||
ADMUX.ADLAR 5 ADC Left Adjust Result
|
||
ADMUX.MUX4 4 Analog Channel and Gain Selection Bit 4
|
||
ADMUX.MUX3 3 Analog Channel and Gain Selection Bit 3
|
||
ADMUX.MUX2 2 Analog Channel and Gain Selection Bit 2
|
||
ADMUX.MUX1 1 Analog Channel and Gain Selection Bit 1
|
||
ADMUX.MUX0 0 Analog Channel and Gain Selection Bit 0
|
||
ACSR 0x0008 Analog Comparator Control and Status Register
|
||
ACSR.ACD 7 Analog Comparator Disable
|
||
ACSR.ACBG 6 Analog Comparator Bandgap Select
|
||
ACSR.ACO 5 Analog Comparator Output
|
||
ACSR.ACI 4 Analog Comparator Interrupt Flag
|
||
ACSR.ACIE 3 Analog Comparator Interrupt Enable
|
||
ACSR.ACIC 2 Analog Comparator Input Capture Enable
|
||
ACSR.ACIS1 1 Analog Comparator Interrupt Mode Select 1
|
||
ACSR.ACIS0 0 Analog Comparator Interrupt Mode Select 0
|
||
UBRR0L 0x0009 USART Baud Rate Register
|
||
UBRR0L.UBRR7 7
|
||
UBRR0L.UBRR6 6
|
||
UBRR0L.UBRR5 5
|
||
UBRR0L.UBRR4 4
|
||
UBRR0L.UBRR3 3
|
||
UBRR0L.UBRR2 2
|
||
UBRR0L.UBRR1 1
|
||
UBRR0L.UBRR0 0
|
||
UCSR0B 0x000A USART Control and Status Register
|
||
UCSR0B.RXCIE 7 RX Complete Interrupt Enable
|
||
UCSR0B.TXCIE 6 TX Complete Interrupt Enable
|
||
UCSR0B.UDRIE 5 USART Data Register Empty Interrupt Enable
|
||
UCSR0B.RXEN 4 Receiver Enable
|
||
UCSR0B.TXEN 3 Transmitter Enable
|
||
UCSR0B.UCSZ2 2 Character Size
|
||
UCSR0B.RXB8 1 Receive Data Bit 8
|
||
UCSR0B.TXB8 0 Transmit Data Bit8
|
||
UCSR0A 0x000B USART Control and Status Register
|
||
UCSR0A.RXC 7 USART Receive Complete
|
||
UCSR0A.TXC 6 USART Transmit Complete
|
||
UCSR0A.UDRE 5 USART Data Register Empty
|
||
UCSR0A.FE 4 Frame Error
|
||
UCSR0A.DOR 3 Data OverRun
|
||
UCSR0A.UPE 2 Parity Error
|
||
UCSR0A.U2X 1 Double the USART Transmission Speed
|
||
UCSR0A.MPCM 0 Multi-Processor Communication Mode
|
||
UDR0 0x000C USART I/O Data Register
|
||
SPCR 0x000D SPI Control Register
|
||
SPCR.SPIE 7 SPI Interrupt Enable
|
||
SPCR.SPE 6 SPI Enable
|
||
SPCR.DORD 5 Data Order
|
||
SPCR.MSTR 4 Master/Slave Select
|
||
SPCR.CPOL 3 Clock Polarity
|
||
SPCR.CPHA 2 Clock Phase
|
||
SPCR.SPR1 1 SPI Clock Rate Select 1
|
||
SPCR.SPR0 0 SPI Clock Rate Select 0
|
||
SPSR 0x000E SPI Status Register
|
||
SPSR.SPIF 7 SPI Interrupt Flag
|
||
SPSR.WCOL 6 Write COLlision flag
|
||
SPSR.SPI2X 0 Double SPI Speed Bit
|
||
SPDR 0x000F SPI Data Register
|
||
PIND 0x0010 Port D Input Pins Address
|
||
PIND.PIND7 7
|
||
PIND.PIND6 6
|
||
PIND.PIND5 5
|
||
PIND.PIND4 4
|
||
PIND.PIND3 3
|
||
PIND.PIND2 2
|
||
PIND.PIND1 1
|
||
PIND.PIND0 0
|
||
DDRD 0x0011 Port D Data Direction Register
|
||
DDRD.DDD7 7 Port D Data Direction Register bit 7
|
||
DDRD.DDD6 6 Port D Data Direction Register bit 6
|
||
DDRD.DDD5 5 Port D Data Direction Register bit 5
|
||
DDRD.DDD4 4 Port D Data Direction Register bit 4
|
||
DDRD.DDD3 3 Port D Data Direction Register bit 3
|
||
DDRD.DDD2 2 Port D Data Direction Register bit 2
|
||
DDRD.DDD1 1 Port D Data Direction Register bit 1
|
||
DDRD.DDD0 0 Port D Data Direction Register bit 0
|
||
PORTD 0x0012 Port D Data Register
|
||
PORTD.PORTD7 7 Port D Data Register bit 7
|
||
PORTD.PORTD6 6 Port D Data Register bit 6
|
||
PORTD.PORTD5 5 Port D Data Register bit 5
|
||
PORTD.PORTD4 4 Port D Data Register bit 4
|
||
PORTD.PORTD3 3 Port D Data Register bit 3
|
||
PORTD.PORTD2 2 Port D Data Register bit 2
|
||
PORTD.PORTD1 1 Port D Data Register bit 1
|
||
PORTD.PORTD0 0 Port D Data Register bit 0
|
||
PINC 0x0013 Port C Input Pins Address
|
||
PINC.PINC7 7
|
||
PINC.PINC6 6
|
||
PINC.PINC5 5
|
||
PINC.PINC4 4
|
||
PINC.PINC3 3
|
||
PINC.PINC2 2
|
||
PINC.PINC1 1
|
||
PINC.PINC0 0
|
||
DDRC 0x0014 Port C Data Direction Register
|
||
DDRC.DDC7 7 Port C Data Direction Register bit 7
|
||
DDRC.DDC6 6 Port C Data Direction Register bit 6
|
||
DDRC.DDC5 5 Port C Data Direction Register bit 5
|
||
DDRC.DDC4 4 Port C Data Direction Register bit 4
|
||
DDRC.DDC3 3 Port C Data Direction Register bit 3
|
||
DDRC.DDC2 2 Port C Data Direction Register bit 2
|
||
DDRC.DDC1 1 Port C Data Direction Register bit 1
|
||
DDRC.DDC0 0 Port C Data Direction Register bit 0
|
||
PORTC 0x0015 Port C Data Register
|
||
PORTC.PORTC7 7 Port C Data Register bit 7
|
||
PORTC.PORTC6 6 Port C Data Register bit 6
|
||
PORTC.PORTC5 5 Port C Data Register bit 5
|
||
PORTC.PORTC4 4 Port C Data Register bit 4
|
||
PORTC.PORTC3 3 Port C Data Register bit 3
|
||
PORTC.PORTC2 2 Port C Data Register bit 2
|
||
PORTC.PORTC1 1 Port C Data Register bit 1
|
||
PORTC.PORTC0 0 Port C Data Register bit 0
|
||
PINB 0x0016 Port B Input Pins Address
|
||
PINB.PINB7 7
|
||
PINB.PINB6 6
|
||
PINB.PINB5 5
|
||
PINB.PINB4 4
|
||
PINB.PINB3 3
|
||
PINB.PINB2 2
|
||
PINB.PINB1 1
|
||
PINB.PINB0 0
|
||
DDRB 0x0017 Port B Data Direction Register
|
||
DDRB.DDB7 7 Port B Data Direction Register bit 7
|
||
DDRB.DDB6 6 Port B Data Direction Register bit 6
|
||
DDRB.DDB5 5 Port B Data Direction Register bit 5
|
||
DDRB.DDB4 4 Port B Data Direction Register bit 4
|
||
DDRB.DDB3 3 Port B Data Direction Register bit 3
|
||
DDRB.DDB2 2 Port B Data Direction Register bit 2
|
||
DDRB.DDB1 1 Port B Data Direction Register bit 1
|
||
DDRB.DDB0 0 Port B Data Direction Register bit 0
|
||
PORTB 0x0018 Port B Data Register
|
||
PORTB.PORTB7 7 Port B Data Register bit 7
|
||
PORTB.PORTB6 6 Port B Data Register bit 6
|
||
PORTB.PORTB5 5 Port B Data Register bit 5
|
||
PORTB.PORTB4 4 Port B Data Register bit 4
|
||
PORTB.PORTB3 3 Port B Data Register bit 3
|
||
PORTB.PORTB2 2 Port B Data Register bit 2
|
||
PORTB.PORTB1 1 Port B Data Register bit 1
|
||
PORTB.PORTB0 0 Port B Data Register bit 0
|
||
PINA 0x0019 Port A Input Pins Address
|
||
PINA.PINA7 7
|
||
PINA.PINA6 6
|
||
PINA.PINA5 5
|
||
PINA.PINA4 4
|
||
PINA.PINA3 3
|
||
PINA.PINA2 2
|
||
PINA.PINA1 1
|
||
PINA.PINA0 0
|
||
DDRA 0x001A Port A Data Direction Register
|
||
DDRA.DDA7 7 Port A Data Direction Register bit 7
|
||
DDRA.DDA6 6 Port A Data Direction Register bit 6
|
||
DDRA.DDA5 5 Port A Data Direction Register bit 5
|
||
DDRA.DDA4 4 Port A Data Direction Register bit 4
|
||
DDRA.DDA3 3 Port A Data Direction Register bit 3
|
||
DDRA.DDA2 2 Port A Data Direction Register bit 2
|
||
DDRA.DDA1 1 Port A Data Direction Register bit 1
|
||
DDRA.DDA0 0 Port A Data Direction Register bit 0
|
||
PORTA 0x001B Port A Data Register
|
||
PORTA.PORTA7 7 Port A Data Register bit 7
|
||
PORTA.PORTA6 6 Port A Data Register bit 6
|
||
PORTA.PORTA5 5 Port A Data Register bit 5
|
||
PORTA.PORTA4 4 Port A Data Register bit 4
|
||
PORTA.PORTA3 3 Port A Data Register bit 3
|
||
PORTA.PORTA2 2 Port A Data Register bit 2
|
||
PORTA.PORTA1 1 Port A Data Register bit 1
|
||
PORTA.PORTA0 0 Port A Data Register bit 0
|
||
EECR 0x001C EEPROM Control Register
|
||
EECR.EERIE 3 EEPROM Ready Interrupt Enable
|
||
EECR.EEMWE 2 EEPROM Master Write Enable
|
||
EECR.EEWE 1 EEPROM Write Enable
|
||
EECR.EERE 0 EEPROM Read Enable
|
||
EEDR 0x001D EEPROM Data Register
|
||
EEARL 0x001E EEPROM Address Register Low
|
||
EEARL.EEAR7 7
|
||
EEARL.EEAR6 6
|
||
EEARL.EEAR5 5
|
||
EEARL.EEAR4 4
|
||
EEARL.EEAR3 3
|
||
EEARL.EEAR2 2
|
||
EEARL.EEAR1 1
|
||
EEARL.EEAR0 0
|
||
EEARH 0x001F EEPROM Address Register High
|
||
EEARH.EEAR11 11
|
||
EEARH.EEAR10 10
|
||
EEARH.EEAR9 9
|
||
EEARH.EEAR8 8
|
||
SFIOR 0x0020 Special Function IO Register
|
||
SFIOR.TSM 7 Timer/Counter Synchronization Mode
|
||
SFIOR.ADHSM 4 ADC High Speed Mode
|
||
SFIOR.ACME 3 Analog Comparator Multiplexer Enable
|
||
SFIOR.PUD 2 Pull-up disable
|
||
SFIOR.PSR0 1 Prescaler Reset Timer/Counter0
|
||
SFIOR.PSR321 0 Prescaler Reset Timer/Counter3, Timer/Counter2, and Timer/Counter1
|
||
WDTCR 0x0021 Watchdog Timer Control Register
|
||
WDTCR.WDCE 4 Watchdog Change Enable
|
||
WDTCR.WDE 3 Watchdog Enable
|
||
WDTCR.WDP2 2 Watchdog Timer Prescaler 2
|
||
WDTCR.WDP1 1 Watchdog Timer Prescaler 1
|
||
WDTCR.WDP0 0 Watchdog Timer Prescaler 0
|
||
OCDR 0x0022 On-chip Debug Register
|
||
OCDR.IDRD_OCDR7 7
|
||
OCDR.OCDR6 6
|
||
OCDR.OCDR5 5
|
||
OCDR.OCDR4 4
|
||
OCDR.OCDR3 3
|
||
OCDR.OCDR2 2
|
||
OCDR.OCDR1 1
|
||
OCDR.OCDR0 0
|
||
OCR2 0x0023 Output Compare Register
|
||
OCR2.OCR2_7 7
|
||
OCR2.OCR2_6 6
|
||
OCR2.OCR2_5 5
|
||
OCR2.OCR2_4 4
|
||
OCR2.OCR2_3 3
|
||
OCR2.OCR2_2 2
|
||
OCR2.OCR2_1 1
|
||
OCR2.OCR2_0 0
|
||
TCNT2 0x0024 Timer/Counter Register
|
||
TCNT2.TCNT2_7 7
|
||
TCNT2.TCNT2_6 6
|
||
TCNT2.TCNT2_5 5
|
||
TCNT2.TCNT2_4 4
|
||
TCNT2.TCNT2_3 3
|
||
TCNT2.TCNT2_2 2
|
||
TCNT2.TCNT2_1 1
|
||
TCNT2.TCNT2_0 0
|
||
TCCR2 0x0025 Timer/Counter Control Register
|
||
TCCR2.FOC2 7 Force Output Compare
|
||
TCCR2.WGM20 6 Waveform Generation Mode 0
|
||
TCCR2.COM21 5 Compare Match Output Mode 1
|
||
TCCR2.COM20 4 Compare Match Output Mode 0
|
||
TCCR2.WGM21 3 Waveform Generation Mode 1
|
||
TCCR2.CS22 2 Clock Select 2
|
||
TCCR2.CS21 1 Clock Select 1
|
||
TCCR2.CS20 0 Clock Select 0
|
||
ICR1L 0x0026 Input Capture Register Low Byte
|
||
ICR1H 0x0027 Input Capture Register High Byte
|
||
OCR1BL 0x0028 Output Compare Register B Low Byte
|
||
OCR1BH 0x0029 Output Compare Register B High Byte
|
||
OCR1AL 0x002A Output Compare Register A Low Byte
|
||
OCR1AH 0x002B Output Compare Register A High Byte
|
||
TCNT1L 0x002C Counter Register Low Byte
|
||
TCNT1H 0x002D Counter Register High Byte
|
||
TCCR1B 0x002E Timer/Counter1 Control Register B
|
||
TCCR1B.ICNC1 7 Input Capture Noise Canceler
|
||
TCCR1B.ICES1 6 Input CaptureEdgeSelect
|
||
TCCR1B.WGM13 4 Waveform Generation Mode 3
|
||
TCCR1B.WGM12 3 Waveform Generation Mode 2
|
||
TCCR1B.CS12 2 Clock Select 2
|
||
TCCR1B.CS11 1 Clock Select 1
|
||
TCCR1B.CS10 0 Clock Select 0
|
||
TCCR1A 0x002F Timer/Counter1 Control Register A
|
||
TCCR1A.COM1A1 7 Compare Output Mode for Channel A 1
|
||
TCCR1A.COM1A0 6 Compare Output Mode for Channel A 0
|
||
TCCR1A.COM1B1 5 Compare Output Mode for Channel B 1
|
||
TCCR1A.COM1B0 4 Compare Output Mode for Channel B 0
|
||
TCCR1A.COM1C1 3 Compare Output Mode for Channel C 1
|
||
TCCR1A.COM1C0 2 Compare Output Mode for Channel C 0
|
||
TCCR1A.WGM11 1 Waveform Generation Mode 1
|
||
TCCR1A.WGM10 0 Waveform Generation Mode 0
|
||
ASSR 0x0030 Asynchronous Status Register
|
||
ASSR.AS0 3 Asynchronous Timer/Counter0
|
||
ASSR.TCN0UB 2 Timer/Counter0 Update Busy
|
||
ASSR.OCR0UB 1 Output Compare Register0 Update Busy
|
||
ASSR.TCR0UB 0 Timer/Counter Control Register0 Update Busy
|
||
OCR0 0x0031 Timer/Counter0 Output Compare Register
|
||
TCNT0 0x0032 Timer/Counter0
|
||
TCCR0 0x0033 Timer/Counter Control Register
|
||
TCCR0.FOC0 7 Force Output Compare
|
||
TCCR0.WGM00 6 Waveform Generation Mode 0
|
||
TCCR0.COM01 5 Compare Match Output Mode 1
|
||
TCCR0.COM00 4 Compare Match Output Mode 0
|
||
TCCR0.WGM01 3 Waveform Generation Mode 1
|
||
TCCR0.CS02 2 Clock Select 2
|
||
TCCR0.CS01 1 Clock Select 1
|
||
TCCR0.CS00 0 Clock Select 0
|
||
MCUCSR 0x0034 MCU Control and Status Register
|
||
MCUCSR.JTD 7 JTAG Interface Disable
|
||
MCUCSR.JTRF 4 JTAG Reset Flag
|
||
MCUCSR.WDRF 3 Watchdog Reset Flag
|
||
MCUCSR.BORF 2 Brown-out Reset Flag
|
||
MCUCSR.EXTRF 1 External Reset Flag
|
||
MCUCSR.PORF 0 Power-On Reset Flag
|
||
MCUCR 0x0035 MCU Control Register
|
||
MCUCR.SRE 7 External SRAM/XMEM Enable
|
||
MCUCR.SRW10 6 Wait-state Select Bit
|
||
MCUCR.SE 5 Sleep Enable
|
||
MCUCR.SM1 4 Sleep Mode Select Bit 1
|
||
MCUCR.SM0 3 Sleep Mode Select Bit 0
|
||
MCUCR.SM2 2 Sleep Mode Select Bit 2
|
||
MCUCR.IVSEL 1 Interrupt Vector Select
|
||
MCUCR.IVCE 0 Interrupt Vector Change Enable
|
||
TIFR 0x0036 Timer/Counter Interrupt Flag Register
|
||
TIFR.OCF2 7 Output Compare Flag 2
|
||
TIFR.TOV2 6 Timer/Counter2 Overflow Flag
|
||
TIFR.ICF1 5 Timer/Counter1, Input Capture Flag
|
||
TIFR.OCF1A 4 Timer/Counter1, Output Compare A Match Flag
|
||
TIFR.OCF1B 3 Timer/Counter1, Output Compare B Match Flag
|
||
TIFR.TOV1 2 Timer/Counter1 Overflow Flag
|
||
TIFR.OCF0 1 Output Compare Flag 0
|
||
TIFR.TOV0 0 Timer/Counter0 Overflow Flag
|
||
TIMSK 0x0037 Timer/Counter Interrupt Mask Register
|
||
TIMSK.OCIE2 7 Timer/Counter2 Output Compare Match Interrupt Enable
|
||
TIMSK.TOIE2 6 Timer/Counter2 Overflow Interrupt Enable
|
||
TIMSK.TICIE1 5 Timer/Counter1, Input Capture Interrupt Enable
|
||
TIMSK.OCIE1A 4 Timer/Counter1, Output Compare A Match Interrupt Enable
|
||
TIMSK.OCIE1B 3 Timer/Counter1, Output Compare B Match Interrupt Enable
|
||
TIMSK.TOIE1 2 Timer/Counter1, Overflow Interrupt Enable
|
||
TIMSK.OCIE0 1 Timer/Counter0 Output Compare Match Interrupt Enable
|
||
TIMSK.TOIE0 0 Timer/Counter0 Overflow Interrupt Enable
|
||
EIFR 0x0038 External Interrupt Flag Register
|
||
EIFR.INTF7 7 External Interrupt Flag 7
|
||
EIFR.INTF6 6 External Interrupt Flag 6
|
||
EIFR.INTF5 5 External Interrupt Flag 5
|
||
EIFR.INTF4 4 External Interrupt Flag 4
|
||
EIFR.INTF3 3 External Interrupt Flag 3
|
||
EIFR.INTF2 2 External Interrupt Flag 2
|
||
EIFR.INTF1 1 External Interrupt Flag 1
|
||
EIFR.INTF0 0 External Interrupt Flag 0
|
||
EIMSK 0x0039 External Interrupt Mask Register
|
||
EIMSK.INT7 7 External Interrupt Request 7 Enable
|
||
EIMSK.INT6 6 External Interrupt Request 6 Enable
|
||
EIMSK.INT5 5 External Interrupt Request 5 Enable
|
||
EIMSK.INT4 4 External Interrupt Request 4 Enable
|
||
EIMSK.INT3 3 External Interrupt Request 3 Enable
|
||
EIMSK.INT2 2 External Interrupt Request 2 Enable
|
||
EIMSK.INT1 1 External Interrupt Request 1 Enable
|
||
EIMSK.INT0 0 External Interrupt Request 0 Enable
|
||
EICRB 0x003A External Interrupt Control Register B
|
||
EICRB.ISC71 7 External Interrupt 7 Sense Control Bit 1
|
||
EICRB.ISC70 6 External Interrupt 7 Sense Control Bit 0
|
||
EICRB.ISC61 5 External Interrupt 6 Sense Control Bit 1
|
||
EICRB.ISC60 4 External Interrupt 6 Sense Control Bit 0
|
||
EICRB.ISC51 3 External Interrupt 5 Sense Control Bit 1
|
||
EICRB.ISC50 2 External Interrupt 5 Sense Control Bit 0
|
||
EICRB.ISC41 1 External Interrupt 4 Sense Control Bit 1
|
||
EICRB.ISC40 0 External Interrupt 4 Sense Control Bit 0
|
||
RAMPZ 0x003B RAM Page Z Select Register
|
||
RAMPZ.RAMPZ0 0 Extended RAM Page Z-pointer
|
||
XDIV 0x003C XTAL Divide Control Register
|
||
XDIV.XDIVEN 7 XTAL Divide Enable
|
||
XDIV.XDIV6 6 XTAL Divide Select Bit 6
|
||
XDIV.XDIV5 5 XTAL Divide Select Bit 5
|
||
XDIV.XDIV4 4 XTAL Divide Select Bit 4
|
||
XDIV.XDIV3 3 XTAL Divide Select Bit 3
|
||
XDIV.XDIV2 2 XTAL Divide Select Bit 2
|
||
XDIV.XDIV1 1 XTAL Divide Select Bit 1
|
||
XDIV.XDIV0 0 XTAL Divide Select Bit 0
|
||
SPL 0x003D Stack Pointer Register Low
|
||
SPL.SP7 7
|
||
SPL.SP6 6
|
||
SPL.SP5 5
|
||
SPL.SP4 4
|
||
SPL.SP3 3
|
||
SPL.SP2 2
|
||
SPL.SP1 1
|
||
SPL.SP0 0
|
||
SPH 0x003E Stack Pointer Register High
|
||
SPH.SP15 15
|
||
SPH.SP14 14
|
||
SPH.SP13 13
|
||
SPH.SP12 12
|
||
SPH.SP11 11
|
||
SPH.SP10 10
|
||
SPH.SP9 9
|
||
SPH.SP8 8
|
||
SREG 0x003F Status Register
|
||
SREG.I 7 Global Interrupt Enable
|
||
SREG.T 6 Bit Copy Storage
|
||
SREG.H 5 Half Carry Flag
|
||
SREG.S 4 Sign Bit
|
||
SREG.V 3 Two's Complement Overflow Flag
|
||
SREG.N 2 Negative Flag
|
||
SREG.Z 1 Zero Flag
|
||
SREG.C 0 CarryFlag
|
||
|
||
; PINF 0x0020 Port F Input Pins Address
|
||
; PINF.PINF7 7
|
||
; PINF.PINF6 6
|
||
; PINF.PINF5 5
|
||
; PINF.PINF4 4
|
||
; PINF.PINF3 3
|
||
; PINF.PINF2 2
|
||
; PINF.PINF1 1
|
||
; PINF.PINF0 0
|
||
; PINE 0x0021 Port E Input Pins Address
|
||
; PINE.PINE7 7
|
||
; PINE.PINE6 6
|
||
; PINE.PINE5 5
|
||
; PINE.PINE4 4
|
||
; PINE.PINE3 3
|
||
; PINE.PINE2 2
|
||
; PINE.PINE1 1
|
||
; PINE.PINE0 0
|
||
; DDRE 0x0022 Port E Data Direction Register
|
||
; DDRE.DDE7 7 Port E Data Direction Register bit 7
|
||
; DDRE.DDE6 6 Port E Data Direction Register bit 6
|
||
; DDRE.DDE5 5 Port E Data Direction Register bit 5
|
||
; DDRE.DDE4 4 Port E Data Direction Register bit 4
|
||
; DDRE.DDE3 3 Port E Data Direction Register bit 3
|
||
; DDRE.DDE2 2 Port E Data Direction Register bit 2
|
||
; DDRE.DDE1 1 Port E Data Direction Register bit 1
|
||
; DDRE.DDE0 0 Port E Data Direction Register bit 0
|
||
; PORTE 0x0023 Port E Data Register
|
||
; PORTE.PORTE7 7 Port E Data Register bit 7
|
||
; PORTE.PORTE6 6 Port E Data Register bit 6
|
||
; PORTE.PORTE5 5 Port E Data Register bit 5
|
||
; PORTE.PORTE4 4 Port E Data Register bit 4
|
||
; PORTE.PORTE3 3 Port E Data Register bit 3
|
||
; PORTE.PORTE2 2 Port E Data Register bit 2
|
||
; PORTE.PORTE1 1 Port E Data Register bit 1
|
||
; PORTE.PORTE0 0 Port E Data Register bit 0
|
||
; ADCL 0x0024 The ADC Data Register Low (ADLAR = 0)
|
||
; ADCL.ADC7 7
|
||
; ADCL.ADC6 6
|
||
; ADCL.ADC5 5
|
||
; ADCL.ADC4 4
|
||
; ADCL.ADC3 3
|
||
; ADCL.ADC2 2
|
||
; ADCL.ADC1 1
|
||
; ADCL.ADC0 0
|
||
; ADCH 0x0025 The ADC Data Register High (ADLAR = 0)
|
||
; ADCH.ADC9 9
|
||
; ADCH.ADC8 8
|
||
; ; ADCL 0x0024 The ADC Data Register Low (ADLAR = 1)
|
||
; ; ADCL.ADC1 7
|
||
; ; ADCL.ADC0 6
|
||
; ; ADCH 0x0025 The ADC Data Register High (ADLAR = 1)
|
||
; ; ADCH.ADC9 15
|
||
; ; ADCH.ADC8 14
|
||
; ; ADCH.ADC7 13
|
||
; ; ADCH.ADC6 12
|
||
; ; ADCH.ADC5 11
|
||
; ; ADCH.ADC4 10
|
||
; ; ADCH.ADC3 9
|
||
; ; ADCH.ADC2 8
|
||
; ADCSRA 0x0026 ADC Control and Status Register A
|
||
; ADCSRA.ADEN 7 ADC Enable
|
||
; ADCSRA.ADSC 6 ADC Start Conversion
|
||
; ADCSRA.ADFR 5 ADC Free Running Select
|
||
; ADCSRA.ADIF 4 ADC Interrupt Flag
|
||
; ADCSRA.ADIE 3 ADC Interrupt Enable
|
||
; ADCSRA.ADPS2 2 ADC Prescaler Select Bit
|
||
; ADCSRA.ADPS1 1 ADC Prescaler Select Bit
|
||
; ADCSRA.ADPS0 0 ADC Prescaler Select Bit
|
||
; ADMUX 0x0027 ADC Multiplexer Selection Register
|
||
; ADMUX.REFS1 7 Reference Selection Bit 1
|
||
; ADMUX.REFS0 6 Reference Selection Bit 0
|
||
; ADMUX.ADLAR 5 ADC Left Adjust Result
|
||
; ADMUX.MUX4 4 Analog Channel and Gain Selection Bit 4
|
||
; ADMUX.MUX3 3 Analog Channel and Gain Selection Bit 3
|
||
; ADMUX.MUX2 2 Analog Channel and Gain Selection Bit 2
|
||
; ADMUX.MUX1 1 Analog Channel and Gain Selection Bit 1
|
||
; ADMUX.MUX0 0 Analog Channel and Gain Selection Bit 0
|
||
; ACSR 0x0028 Analog Comparator Control and Status Register
|
||
; ACSR.ACD 7 Analog Comparator Disable
|
||
; ACSR.ACBG 6 Analog Comparator Bandgap Select
|
||
; ACSR.ACO 5 Analog Comparator Output
|
||
; ACSR.ACI 4 Analog Comparator Interrupt Flag
|
||
; ACSR.ACIE 3 Analog Comparator Interrupt Enable
|
||
; ACSR.ACIC 2 Analog Comparator Input Capture Enable
|
||
; ACSR.ACIS1 1 Analog Comparator Interrupt Mode Select 1
|
||
; ACSR.ACIS0 0 Analog Comparator Interrupt Mode Select 0
|
||
; UBRR0L 0x0029 USART Baud Rate Register
|
||
; UBRR0L.UBRR7 7
|
||
; UBRR0L.UBRR6 6
|
||
; UBRR0L.UBRR5 5
|
||
; UBRR0L.UBRR4 4
|
||
; UBRR0L.UBRR3 3
|
||
; UBRR0L.UBRR2 2
|
||
; UBRR0L.UBRR1 1
|
||
; UBRR0L.UBRR0 0
|
||
; UCSR0B 0x002A USART Control and Status Register
|
||
; UCSR0B.RXCIE 7 RX Complete Interrupt Enable
|
||
; UCSR0B.TXCIE 6 TX Complete Interrupt Enable
|
||
; UCSR0B.UDRIE 5 USART Data Register Empty Interrupt Enable
|
||
; UCSR0B.RXEN 4 Receiver Enable
|
||
; UCSR0B.TXEN 3 Transmitter Enable
|
||
; UCSR0B.UCSZ2 2 Character Size
|
||
; UCSR0B.RXB8 1 Receive Data Bit 8
|
||
; UCSR0B.TXB8 0 Transmit Data Bit8
|
||
; UCSR0A 0x002B USART Control and Status Register
|
||
; UCSR0A.RXC 7 USART Receive Complete
|
||
; UCSR0A.TXC 6 USART Transmit Complete
|
||
; UCSR0A.UDRE 5 USART Data Register Empty
|
||
; UCSR0A.FE 4 Frame Error
|
||
; UCSR0A.DOR 3 Data OverRun
|
||
; UCSR0A.UPE 2 Parity Error
|
||
; UCSR0A.U2X 1 Double the USART Transmission Speed
|
||
; UCSR0A.MPCM 0 Multi-Processor Communication Mode
|
||
; UDR0 0x002C USART I/O Data Register
|
||
; SPCR 0x002D SPI Control Register
|
||
; SPCR.SPIE 7 SPI Interrupt Enable
|
||
; SPCR.SPE 6 SPI Enable
|
||
; SPCR.DORD 5 Data Order
|
||
; SPCR.MSTR 4 Master/Slave Select
|
||
; SPCR.CPOL 3 Clock Polarity
|
||
; SPCR.CPHA 2 Clock Phase
|
||
; SPCR.SPR1 1 SPI Clock Rate Select 1
|
||
; SPCR.SPR0 0 SPI Clock Rate Select 0
|
||
; SPSR 0x002E SPI Status Register
|
||
; SPSR.SPIF 7 SPI Interrupt Flag
|
||
; SPSR.WCOL 6 Write COLlision flag
|
||
; SPSR.SPI2X 0 Double SPI Speed Bit
|
||
; SPDR 0x002F SPI Data Register
|
||
; PIND 0x0030 Port D Input Pins Address
|
||
; PIND.PIND7 7
|
||
; PIND.PIND6 6
|
||
; PIND.PIND5 5
|
||
; PIND.PIND4 4
|
||
; PIND.PIND3 3
|
||
; PIND.PIND2 2
|
||
; PIND.PIND1 1
|
||
; PIND.PIND0 0
|
||
; DDRD 0x0031 Port D Data Direction Register
|
||
; DDRD.DDD7 7 Port D Data Direction Register bit 7
|
||
; DDRD.DDD6 6 Port D Data Direction Register bit 6
|
||
; DDRD.DDD5 5 Port D Data Direction Register bit 5
|
||
; DDRD.DDD4 4 Port D Data Direction Register bit 4
|
||
; DDRD.DDD3 3 Port D Data Direction Register bit 3
|
||
; DDRD.DDD2 2 Port D Data Direction Register bit 2
|
||
; DDRD.DDD1 1 Port D Data Direction Register bit 1
|
||
; DDRD.DDD0 0 Port D Data Direction Register bit 0
|
||
; PORTD 0x0032 Port D Data Register
|
||
; PORTD.PORTD7 7 Port D Data Register bit 7
|
||
; PORTD.PORTD6 6 Port D Data Register bit 6
|
||
; PORTD.PORTD5 5 Port D Data Register bit 5
|
||
; PORTD.PORTD4 4 Port D Data Register bit 4
|
||
; PORTD.PORTD3 3 Port D Data Register bit 3
|
||
; PORTD.PORTD2 2 Port D Data Register bit 2
|
||
; PORTD.PORTD1 1 Port D Data Register bit 1
|
||
; PORTD.PORTD0 0 Port D Data Register bit 0
|
||
; PINC 0x0033 Port C Input Pins Address
|
||
; PINC.PINC7 7
|
||
; PINC.PINC6 6
|
||
; PINC.PINC5 5
|
||
; PINC.PINC4 4
|
||
; PINC.PINC3 3
|
||
; PINC.PINC2 2
|
||
; PINC.PINC1 1
|
||
; PINC.PINC0 0
|
||
; DDRC 0x0034 Port C Data Direction Register
|
||
; DDRC.DDC7 7 Port C Data Direction Register bit 7
|
||
; DDRC.DDC6 6 Port C Data Direction Register bit 6
|
||
; DDRC.DDC5 5 Port C Data Direction Register bit 5
|
||
; DDRC.DDC4 4 Port C Data Direction Register bit 4
|
||
; DDRC.DDC3 3 Port C Data Direction Register bit 3
|
||
; DDRC.DDC2 2 Port C Data Direction Register bit 2
|
||
; DDRC.DDC1 1 Port C Data Direction Register bit 1
|
||
; DDRC.DDC0 0 Port C Data Direction Register bit 0
|
||
; PORTC 0x0035 Port C Data Register
|
||
; PORTC.PORTC7 7 Port C Data Register bit 7
|
||
; PORTC.PORTC6 6 Port C Data Register bit 6
|
||
; PORTC.PORTC5 5 Port C Data Register bit 5
|
||
; PORTC.PORTC4 4 Port C Data Register bit 4
|
||
; PORTC.PORTC3 3 Port C Data Register bit 3
|
||
; PORTC.PORTC2 2 Port C Data Register bit 2
|
||
; PORTC.PORTC1 1 Port C Data Register bit 1
|
||
; PORTC.PORTC0 0 Port C Data Register bit 0
|
||
; PINB 0x0036 Port B Input Pins Address
|
||
; PINB.PINB7 7
|
||
; PINB.PINB6 6
|
||
; PINB.PINB5 5
|
||
; PINB.PINB4 4
|
||
; PINB.PINB3 3
|
||
; PINB.PINB2 2
|
||
; PINB.PINB1 1
|
||
; PINB.PINB0 0
|
||
; DDRB 0x0037 Port B Data Direction Register
|
||
; DDRB.DDB7 7 Port B Data Direction Register bit 7
|
||
; DDRB.DDB6 6 Port B Data Direction Register bit 6
|
||
; DDRB.DDB5 5 Port B Data Direction Register bit 5
|
||
; DDRB.DDB4 4 Port B Data Direction Register bit 4
|
||
; DDRB.DDB3 3 Port B Data Direction Register bit 3
|
||
; DDRB.DDB2 2 Port B Data Direction Register bit 2
|
||
; DDRB.DDB1 1 Port B Data Direction Register bit 1
|
||
; DDRB.DDB0 0 Port B Data Direction Register bit 0
|
||
; PORTB 0x0038 Port B Data Register
|
||
; PORTB.PORTB7 7 Port B Data Register bit 7
|
||
; PORTB.PORTB6 6 Port B Data Register bit 6
|
||
; PORTB.PORTB5 5 Port B Data Register bit 5
|
||
; PORTB.PORTB4 4 Port B Data Register bit 4
|
||
; PORTB.PORTB3 3 Port B Data Register bit 3
|
||
; PORTB.PORTB2 2 Port B Data Register bit 2
|
||
; PORTB.PORTB1 1 Port B Data Register bit 1
|
||
; PORTB.PORTB0 0 Port B Data Register bit 0
|
||
; PINA 0x0039 Port A Input Pins Address
|
||
; PINA.PINA7 7
|
||
; PINA.PINA6 6
|
||
; PINA.PINA5 5
|
||
; PINA.PINA4 4
|
||
; PINA.PINA3 3
|
||
; PINA.PINA2 2
|
||
; PINA.PINA1 1
|
||
; PINA.PINA0 0
|
||
; DDRA 0x003A Port A Data Direction Register
|
||
; DDRA.DDA7 7 Port A Data Direction Register bit 7
|
||
; DDRA.DDA6 6 Port A Data Direction Register bit 6
|
||
; DDRA.DDA5 5 Port A Data Direction Register bit 5
|
||
; DDRA.DDA4 4 Port A Data Direction Register bit 4
|
||
; DDRA.DDA3 3 Port A Data Direction Register bit 3
|
||
; DDRA.DDA2 2 Port A Data Direction Register bit 2
|
||
; DDRA.DDA1 1 Port A Data Direction Register bit 1
|
||
; DDRA.DDA0 0 Port A Data Direction Register bit 0
|
||
; PORTA 0x003B Port A Data Register
|
||
; PORTA.PORTA7 7 Port A Data Register bit 7
|
||
; PORTA.PORTA6 6 Port A Data Register bit 6
|
||
; PORTA.PORTA5 5 Port A Data Register bit 5
|
||
; PORTA.PORTA4 4 Port A Data Register bit 4
|
||
; PORTA.PORTA3 3 Port A Data Register bit 3
|
||
; PORTA.PORTA2 2 Port A Data Register bit 2
|
||
; PORTA.PORTA1 1 Port A Data Register bit 1
|
||
; PORTA.PORTA0 0 Port A Data Register bit 0
|
||
; EECR 0x003C EEPROM Control Register
|
||
; EECR.EERIE 3 EEPROM Ready Interrupt Enable
|
||
; EECR.EEMWE 2 EEPROM Master Write Enable
|
||
; EECR.EEWE 1 EEPROM Write Enable
|
||
; EECR.EERE 0 EEPROM Read Enable
|
||
; EEDR 0x003D EEPROM Data Register
|
||
; EEARL 0x003E EEPROM Address Register Low
|
||
; EEARL.EEAR7 7
|
||
; EEARL.EEAR6 6
|
||
; EEARL.EEAR5 5
|
||
; EEARL.EEAR4 4
|
||
; EEARL.EEAR3 3
|
||
; EEARL.EEAR2 2
|
||
; EEARL.EEAR1 1
|
||
; EEARL.EEAR0 0
|
||
; EEARH 0x003F EEPROM Address Register High
|
||
; EEARH.EEAR11 11
|
||
; EEARH.EEAR10 10
|
||
; EEARH.EEAR9 9
|
||
; EEARH.EEAR8 8
|
||
; SFIOR 0x0040 Special Function IO Register
|
||
; SFIOR.TSM 7 Timer/Counter Synchronization Mode
|
||
; SFIOR.ADHSM 4 ADC High Speed Mode
|
||
; SFIOR.ACME 3 Analog Comparator Multiplexer Enable
|
||
; SFIOR.PUD 2 Pull-up disable
|
||
; SFIOR.PSR0 1 Prescaler Reset Timer/Counter0
|
||
; SFIOR.PSR321 0 Prescaler Reset Timer/Counter3, Timer/Counter2, and Timer/Counter1
|
||
; WDTCR 0x0041 Watchdog Timer Control Register
|
||
; WDTCR.WDCE 4 Watchdog Change Enable
|
||
; WDTCR.WDE 3 Watchdog Enable
|
||
; WDTCR.WDP2 2 Watchdog Timer Prescaler 2
|
||
; WDTCR.WDP1 1 Watchdog Timer Prescaler 1
|
||
; WDTCR.WDP0 0 Watchdog Timer Prescaler 0
|
||
; OCDR 0x0042 On-chip Debug Register
|
||
; OCDR.IDRD_OCDR7 7
|
||
; OCDR.OCDR6 6
|
||
; OCDR.OCDR5 5
|
||
; OCDR.OCDR4 4
|
||
; OCDR.OCDR3 3
|
||
; OCDR.OCDR2 2
|
||
; OCDR.OCDR1 1
|
||
; OCDR.OCDR0 0
|
||
; OCR2 0x0043 Output Compare Register
|
||
; OCR2.OCR2_7 7
|
||
; OCR2.OCR2_6 6
|
||
; OCR2.OCR2_5 5
|
||
; OCR2.OCR2_4 4
|
||
; OCR2.OCR2_3 3
|
||
; OCR2.OCR2_2 2
|
||
; OCR2.OCR2_1 1
|
||
; OCR2.OCR2_0 0
|
||
; TCNT2 0x0044 Timer/Counter Register
|
||
; TCNT2.TCNT2_7 7
|
||
; TCNT2.TCNT2_6 6
|
||
; TCNT2.TCNT2_5 5
|
||
; TCNT2.TCNT2_4 4
|
||
; TCNT2.TCNT2_3 3
|
||
; TCNT2.TCNT2_2 2
|
||
; TCNT2.TCNT2_1 1
|
||
; TCNT2.TCNT2_0 0
|
||
; TCCR2 0x0045 Timer/Counter Control Register
|
||
; TCCR2.FOC2 7 Force Output Compare
|
||
; TCCR2.WGM20 6 Waveform Generation Mode 0
|
||
; TCCR2.COM21 5 Compare Match Output Mode 1
|
||
; TCCR2.COM20 4 Compare Match Output Mode 0
|
||
; TCCR2.WGM21 3 Waveform Generation Mode 1
|
||
; TCCR2.CS22 2 Clock Select 2
|
||
; TCCR2.CS21 1 Clock Select 1
|
||
; TCCR2.CS20 0 Clock Select 0
|
||
; ICR1L 0x0046 Input Capture Register Low Byte
|
||
; ICR1H 0x0047 Input Capture Register High Byte
|
||
; OCR1BL 0x0048 Output Compare Register B Low Byte
|
||
; OCR1BH 0x0049 Output Compare Register B High Byte
|
||
; OCR1AL 0x004A Output Compare Register A Low Byte
|
||
; OCR1AH 0x004B Output Compare Register A High Byte
|
||
; TCNT1L 0x004C Counter Register Low Byte
|
||
; TCNT1H 0x004D Counter Register High Byte
|
||
; TCCR1B 0x004E Timer/Counter1 Control Register B
|
||
; TCCR1B.ICNC1 7 Input Capture Noise Canceler
|
||
; TCCR1B.ICES1 6 Input CaptureEdgeSelect
|
||
; TCCR1B.WGM13 4 Waveform Generation Mode 3
|
||
; TCCR1B.WGM12 3 Waveform Generation Mode 2
|
||
; TCCR1B.CS12 2 Clock Select 2
|
||
; TCCR1B.CS11 1 Clock Select 1
|
||
; TCCR1B.CS10 0 Clock Select 0
|
||
; TCCR1A 0x004F Timer/Counter1 Control Register A
|
||
; TCCR1A.COM1A1 7 Compare Output Mode for Channel A 1
|
||
; TCCR1A.COM1A0 6 Compare Output Mode for Channel A 0
|
||
; TCCR1A.COM1B1 5 Compare Output Mode for Channel B 1
|
||
; TCCR1A.COM1B0 4 Compare Output Mode for Channel B 0
|
||
; TCCR1A.COM1C1 3 Compare Output Mode for Channel C 1
|
||
; TCCR1A.COM1C0 2 Compare Output Mode for Channel C 0
|
||
; TCCR1A.WGM11 1 Waveform Generation Mode 1
|
||
; TCCR1A.WGM10 0 Waveform Generation Mode 0
|
||
; ASSR 0x0050 Asynchronous Status Register
|
||
; ASSR.AS0 3 Asynchronous Timer/Counter0
|
||
; ASSR.TCN0UB 2 Timer/Counter0 Update Busy
|
||
; ASSR.OCR0UB 1 Output Compare Register0 Update Busy
|
||
; ASSR.TCR0UB 0 Timer/Counter Control Register0 Update Busy
|
||
; OCR0 0x0051 Timer/Counter0 Output Compare Register
|
||
; TCNT0 0x0052 Timer/Counter0
|
||
; TCCR0 0x0053 Timer/Counter Control Register
|
||
; TCCR0.FOC0 7 Force Output Compare
|
||
; TCCR0.WGM00 6 Waveform Generation Mode 0
|
||
; TCCR0.COM01 5 Compare Match Output Mode 1
|
||
; TCCR0.COM00 4 Compare Match Output Mode 0
|
||
; TCCR0.WGM01 3 Waveform Generation Mode 1
|
||
; TCCR0.CS02 2 Clock Select 2
|
||
; TCCR0.CS01 1 Clock Select 1
|
||
; TCCR0.CS00 0 Clock Select 0
|
||
; MCUCSR 0x0054 MCU Control and Status Register
|
||
; MCUCSR.JTD 7 JTAG Interface Disable
|
||
; MCUCSR.JTRF 4 JTAG Reset Flag
|
||
; MCUCSR.WDRF 3 Watchdog Reset Flag
|
||
; MCUCSR.BORF 2 Brown-out Reset Flag
|
||
; MCUCSR.EXTRF 1 External Reset Flag
|
||
; MCUCSR.PORF 0 Power-On Reset Flag
|
||
; MCUCR 0x0055 MCU Control Register
|
||
; MCUCR.SRE 7 External SRAM/XMEM Enable
|
||
; MCUCR.SRW10 6 Wait-state Select Bit
|
||
; MCUCR.SE 5 Sleep Enable
|
||
; MCUCR.SM1 4 Sleep Mode Select Bit 1
|
||
; MCUCR.SM0 3 Sleep Mode Select Bit 0
|
||
; MCUCR.SM2 2 Sleep Mode Select Bit 2
|
||
; MCUCR.IVSEL 1 Interrupt Vector Select
|
||
; MCUCR.IVCE 0 Interrupt Vector Change Enable
|
||
; TIFR 0x0056 Timer/Counter Interrupt Flag Register
|
||
; TIFR.OCF2 7 Output Compare Flag 2
|
||
; TIFR.TOV2 6 Timer/Counter2 Overflow Flag
|
||
; TIFR.ICF1 5 Timer/Counter1, Input Capture Flag
|
||
; TIFR.OCF1A 4 Timer/Counter1, Output Compare A Match Flag
|
||
; TIFR.OCF1B 3 Timer/Counter1, Output Compare B Match Flag
|
||
; TIFR.TOV1 2 Timer/Counter1 Overflow Flag
|
||
; TIFR.OCF0 1 Output Compare Flag 0
|
||
; TIFR.TOV0 0 Timer/Counter0 Overflow Flag
|
||
; TIMSK 0x0057 Timer/Counter Interrupt Mask Register
|
||
; TIMSK.OCIE2 7 Timer/Counter2 Output Compare Match Interrupt Enable
|
||
; TIMSK.TOIE2 6 Timer/Counter2 Overflow Interrupt Enable
|
||
; TIMSK.TICIE1 5 Timer/Counter1, Input Capture Interrupt Enable
|
||
; TIMSK.OCIE1A 4 Timer/Counter1, Output Compare A Match Interrupt Enable
|
||
; TIMSK.OCIE1B 3 Timer/Counter1, Output Compare B Match Interrupt Enable
|
||
; TIMSK.TOIE1 2 Timer/Counter1, Overflow Interrupt Enable
|
||
; TIMSK.OCIE0 1 Timer/Counter0 Output Compare Match Interrupt Enable
|
||
; TIMSK.TOIE0 0 Timer/Counter0 Overflow Interrupt Enable
|
||
; EIFR 0x0058 External Interrupt Flag Register
|
||
; EIFR.INTF7 7 External Interrupt Flag 7
|
||
; EIFR.INTF6 6 External Interrupt Flag 6
|
||
; EIFR.INTF5 5 External Interrupt Flag 5
|
||
; EIFR.INTF4 4 External Interrupt Flag 4
|
||
; EIFR.INTF3 3 External Interrupt Flag 3
|
||
; EIFR.INTF2 2 External Interrupt Flag 2
|
||
; EIFR.INTF1 1 External Interrupt Flag 1
|
||
; EIFR.INTF0 0 External Interrupt Flag 0
|
||
; EIMSK 0x0059 External Interrupt Mask Register
|
||
; EIMSK.INT7 7 External Interrupt Request 7 Enable
|
||
; EIMSK.INT6 6 External Interrupt Request 6 Enable
|
||
; EIMSK.INT5 5 External Interrupt Request 5 Enable
|
||
; EIMSK.INT4 4 External Interrupt Request 4 Enable
|
||
; EIMSK.INT3 3 External Interrupt Request 3 Enable
|
||
; EIMSK.INT2 2 External Interrupt Request 2 Enable
|
||
; EIMSK.INT1 1 External Interrupt Request 1 Enable
|
||
; EIMSK.INT0 0 External Interrupt Request 0 Enable
|
||
; EICRB 0x005A External Interrupt Control Register B
|
||
; EICRB.ISC71 7 External Interrupt 7 Sense Control Bit 1
|
||
; EICRB.ISC70 6 External Interrupt 7 Sense Control Bit 0
|
||
; EICRB.ISC61 5 External Interrupt 6 Sense Control Bit 1
|
||
; EICRB.ISC60 4 External Interrupt 6 Sense Control Bit 0
|
||
; EICRB.ISC51 3 External Interrupt 5 Sense Control Bit 1
|
||
; EICRB.ISC50 2 External Interrupt 5 Sense Control Bit 0
|
||
; EICRB.ISC41 1 External Interrupt 4 Sense Control Bit 1
|
||
; EICRB.ISC40 0 External Interrupt 4 Sense Control Bit 0
|
||
; RAMPZ 0x005B RAM Page Z Select Register
|
||
; RAMPZ.RAMPZ0 0 Extended RAM Page Z-pointer
|
||
; XDIV 0x005C XTAL Divide Control Register
|
||
; XDIV.XDIVEN 7 XTAL Divide Enable
|
||
; XDIV.XDIV6 6 XTAL Divide Select Bit 6
|
||
; XDIV.XDIV5 5 XTAL Divide Select Bit 5
|
||
; XDIV.XDIV4 4 XTAL Divide Select Bit 4
|
||
; XDIV.XDIV3 3 XTAL Divide Select Bit 3
|
||
; XDIV.XDIV2 2 XTAL Divide Select Bit 2
|
||
; XDIV.XDIV1 1 XTAL Divide Select Bit 1
|
||
; XDIV.XDIV0 0 XTAL Divide Select Bit 0
|
||
; SPL 0x005D Stack Pointer Register Low
|
||
; SPL.SP7 7
|
||
; SPL.SP6 6
|
||
; SPL.SP5 5
|
||
; SPL.SP4 4
|
||
; SPL.SP3 3
|
||
; SPL.SP2 2
|
||
; SPL.SP1 1
|
||
; SPL.SP0 0
|
||
; SPH 0x005E Stack Pointer Register High
|
||
; SPH.SP15 15
|
||
; SPH.SP14 14
|
||
; SPH.SP13 13
|
||
; SPH.SP12 12
|
||
; SPH.SP11 11
|
||
; SPH.SP10 10
|
||
; SPH.SP9 9
|
||
; SPH.SP8 8
|
||
; SREG 0x005F Status Register
|
||
; SREG.I 7 Global Interrupt Enable
|
||
; SREG.T 6 Bit Copy Storage
|
||
; SREG.H 5 Half Carry Flag
|
||
; SREG.S 4 Sign Bit
|
||
; SREG.V 3 Two's Complement Overflow Flag
|
||
; SREG.N 2 Negative Flag
|
||
; SREG.Z 1 Zero Flag
|
||
; SREG.C 0 CarryFlag
|
||
; RESERVED0060 0x0060 RESERVED
|
||
; DDRF 0x0061 Port F Data Direction Register
|
||
; DDRF.DDF7 7 Port F Data Direction Register bit 7
|
||
; DDRF.DDF6 6 Port F Data Direction Register bit 6
|
||
; DDRF.DDF5 5 Port F Data Direction Register bit 5
|
||
; DDRF.DDF4 4 Port F Data Direction Register bit 4
|
||
; DDRF.DDF3 3 Port F Data Direction Register bit 3
|
||
; DDRF.DDF2 2 Port F Data Direction Register bit 2
|
||
; DDRF.DDF1 1 Port F Data Direction Register bit 1
|
||
; DDRF.DDF0 0 Port F Data Direction Register bit 0
|
||
; PORTF 0x0062 Port F Data Register
|
||
; PORTF.PORTF7 7 Port F Data Register bit 7
|
||
; PORTF.PORTF6 6 Port F Data Register bit 6
|
||
; PORTF.PORTF5 5 Port F Data Register bit 5
|
||
; PORTF.PORTF4 4 Port F Data Register bit 4
|
||
; PORTF.PORTF3 3 Port F Data Register bit 3
|
||
; PORTF.PORTF2 2 Port F Data Register bit 2
|
||
; PORTF.PORTF1 1 Port F Data Register bit 1
|
||
; PORTF.PORTF0 0 Port F Data Register bit 0
|
||
; PING 0x0063 Port G Input Pins Address
|
||
; PING.PING4 4
|
||
; PING.PING3 3
|
||
; PING.PING2 2
|
||
; PING.PING1 1
|
||
; PING.PING0 0
|
||
; DDRG 0x0064 Port G Data Direction Register
|
||
; DDRG.DDG4 4 Port G Data Direction Register bit 4
|
||
; DDRG.DDG3 3 Port G Data Direction Register bit 3
|
||
; DDRG.DDG2 2 Port G Data Direction Register bit 2
|
||
; DDRG.DDG1 1 Port G Data Direction Register bit 1
|
||
; DDRG.DDG0 0 Port G Data Direction Register bit 0
|
||
; PORTG 0x0065 Port G Data Register
|
||
; PORTG.PORTG4 4 Port G Data Register bit 4
|
||
; PORTG.PORTG3 3 Port G Data Register bit 3
|
||
; PORTG.PORTG2 2 Port G Data Register bit 2
|
||
; PORTG.PORTG1 1 Port G Data Register bit 1
|
||
; PORTG.PORTG0 0 Port G Data Register bit 0
|
||
; RESERVED0066 0x0066 RESERVED
|
||
; RESERVED0067 0x0067 RESERVED
|
||
; SPMCSR 0x0068 Store Program Memory Control Register
|
||
; SPMCSR.SPMIE 7 SPM Interrupt Enable
|
||
; SPMCSR.RWWSB 6 Read-While-Write Section Busy
|
||
; SPMCSR.RWWSRE 4 Read-While-Write Section Read Enable
|
||
; SPMCSR.BLBSET 3 Boot Lock Bit Set
|
||
; SPMCSR.PGWRT 2 Page Write
|
||
; SPMCSR.PGERS 1 Page Erase
|
||
; SPMCSR.SPMEN 0 Store Program Memory Enable
|
||
; RESERVED0069 0x0069 RESERVED
|
||
; EICRA 0x006A External Interrupt Control Register A
|
||
; EICRA.ISC31 7 External Interrupt 3 Sense Control Bit 1
|
||
; EICRA.ISC30 6 External Interrupt 3 Sense Control Bit 0
|
||
; EICRA.ISC21 5 External Interrupt 2 Sense Control Bit 1
|
||
; EICRA.ISC20 4 External Interrupt 2 Sense Control Bit 0
|
||
; EICRA.ISC11 3 External Interrupt 1 Sense Control Bit 1
|
||
; EICRA.ISC10 2 External Interrupt 1 Sense Control Bit 0
|
||
; EICRA.ISC01 1 External Interrupt 0 Sense Control Bit 1
|
||
; EICRA.ISC00 0 External Interrupt 0 Sense Control Bit 0
|
||
; RESERVED006B 0x006B RESERVED
|
||
; XMCRB 0x006C External Memory Control Register B
|
||
; XMCRB.XMBK 7 External Memory Bus-keeper Enable
|
||
; XMCRB.XMM2 2 External Memory High Mask 2
|
||
; XMCRB.XMM1 1 External Memory High Mask 1
|
||
; XMCRB.XMM0 0 External Memory High Mask 0
|
||
; RESERVED006D 0x006D RESERVED
|
||
; OSCCAL 0x006F Oscillator Calibration Register
|
||
; OSCCAL.CAL7 7 Oscillator Calibration Value 7
|
||
; OSCCAL.CAL6 6 Oscillator Calibration Value 6
|
||
; OSCCAL.CAL5 5 Oscillator Calibration Value 5
|
||
; OSCCAL.CAL4 4 Oscillator Calibration Value 4
|
||
; OSCCAL.CAL3 3 Oscillator Calibration Value 3
|
||
; OSCCAL.CAL2 2 Oscillator Calibration Value 2
|
||
; OSCCAL.CAL1 1 Oscillator Calibration Value 1
|
||
; OSCCAL.CAL0 0 Oscillator Calibration Value 0
|
||
; TWBR 0x0070 TWI Bit Rate Register
|
||
; TWBR.TWBR7 7 TWI Bit Rate Register bit 7
|
||
; TWBR.TWBR6 6 TWI Bit Rate Register bit 6
|
||
; TWBR.TWBR5 5 TWI Bit Rate Register bit 5
|
||
; TWBR.TWBR4 4 TWI Bit Rate Register bit 4
|
||
; TWBR.TWBR3 3 TWI Bit Rate Register bit 3
|
||
; TWBR.TWBR2 2 TWI Bit Rate Register bit 2
|
||
; TWBR.TWBR1 1 TWI Bit Rate Register bit 1
|
||
; TWBR.TWBR0 0 TWI Bit Rate Register bit 0
|
||
; TWSR 0x0071 TWI Status Register
|
||
; TWSR.TWS7 7 TWI Status 7
|
||
; TWSR.TWS6 6 TWI Status 6
|
||
; TWSR.TWS5 5 TWI Status 5
|
||
; TWSR.TWS4 4 TWI Status 4
|
||
; TWSR.TWS3 3 TWI Status 3
|
||
; TWSR.TWS1 1 TWI Status 1
|
||
; TWSR.TWS0 0 TWI Status 0
|
||
; TWAR 0x0072 TWI (Slave) Address Register
|
||
; TWAR.TWA6 7 TWI (Slave) Address Register bit 6
|
||
; TWAR.TWA5 6 TWI (Slave) Address Register bit 5
|
||
; TWAR.TWA4 5 TWI (Slave) Address Register bit 4
|
||
; TWAR.TWA3 4 TWI (Slave) Address Register bit 3
|
||
; TWAR.TWA2 3 TWI (Slave) Address Register bit 2
|
||
; TWAR.TWA1 2 TWI (Slave) Address Register bit 1
|
||
; TWAR.TWA0 1 TWI (Slave) Address Register bit 0
|
||
; TWAR.TWGCE 0 TWI General Call Recognition Enable Bit
|
||
; TWDR 0x0073 TWI Data Register
|
||
; TWDR.TWD7 7 TWI Data Register bit 7
|
||
; TWDR.TWD6 6 TWI Data Register bit 6
|
||
; TWDR.TWD5 5 TWI Data Register bit 5
|
||
; TWDR.TWD4 4 TWI Data Register bit 4
|
||
; TWDR.TWD3 3 TWI Data Register bit 3
|
||
; TWDR.TWD2 2 TWI Data Register bit 2
|
||
; TWDR.TWD1 1 TWI Data Register bit 1
|
||
; TWDR.TWD0 0 TWI Data Register bit 0
|
||
; TWCR 0x0074 TWI Control Register
|
||
; TWCR.TWINT 7 TWI Interrupt Flag
|
||
; TWCR.TWEA 6 TWI Enable Acknowledge Bit
|
||
; TWCR.TWSTA 5 TWI START Condition Bit
|
||
; TWCR.TWSTO 4 TWI STOP Condition Bit
|
||
; TWCR.TWWC 3 TWI Write Collision Flag
|
||
; TWCR.TWEN 2 TWI Enable Bit
|
||
; TWCR.TWIE 0 TWI Interrupt Enable
|
||
; RESERVED0075 0x0075 RESERVED
|
||
; RESERVED0076 0x0076 RESERVED
|
||
; RESERVED0077 0x0077 RESERVED
|
||
; OCR1CL 0x0078 Output Compare Register C Low Byte
|
||
; OCR1CH 0x0079 Output Compare Register C High Byte
|
||
; TCCR1C 0x007A Timer/Counter1 Control Register C
|
||
; TCCR1C.FOC1A 7 Force Output Compare for Channel A
|
||
; TCCR1C.FOC1B 6 Force Output Compare for Channel B
|
||
; TCCR1C.FOC1C 5 Force Output Compare for Channel C
|
||
; RESERVED007B 0x007B RESERVED
|
||
; ETIFR 0x007C Extended Timer/Counter Interrupt Flag Register
|
||
; ETIFR.ICF3 5 Timer/Counter3, Input Capture Flag
|
||
; ETIFR.OCF3A 4 Timer/Counter3, Output Compare A Match Flag
|
||
; ETIFR.OCF3B 3 Timer/Counter3, Output Compare B Match Flag
|
||
; ETIFR.TOV3 2 Timer/Counter3, Overflow Flag
|
||
; ETIFR.OCF3C 1 Timer/Counter3, Output Compare C Match Flag
|
||
; ETIFR.OCF1C 0 Timer/Counter1, Output Compare C Match Flag
|
||
; ETIMSK 0x007D Extended Timer/Counter Interrupt Mask Register
|
||
; ETIMSK.TICIE3 5 Timer/Counter3, Input Capture Interrupt Enable
|
||
; ETIMSK.OCIE3A 4 Timer/Counter3, Output Compare A Match Interrupt Enable
|
||
; ETIMSK.OCIE3B 3 Timer/Counter3, Output Compare B Match Interrupt Enable
|
||
; ETIMSK.TOIE3 2 Timer/Counter3, Overflow Interrupt Enable
|
||
; ETIMSK.OCIE3C 1 Timer/Counter3, Output Compare C Match Interrupt Enable
|
||
; ETIMSK.OCIE1C 0 Timer/Counter1, Output Compare C Match Interrupt Enable
|
||
; RESERVED007E 0x007E RESERVED
|
||
; RESERVED007F 0x007F RESERVED
|
||
; ICR3L 0x0080 Input Capture Register Low Byte
|
||
; ICR3H 0x0081 Input Capture Register High Byte
|
||
; OCR3CL 0x0082 Output Compare Register C Low Byte
|
||
; OCR3CH 0x0083 Output Compare Register C High Byte
|
||
; OCR3BL 0x0084 Output Compare Register B Low Byte
|
||
; OCR3BH 0x0085 Output Compare Register B High Byte
|
||
; OCR3AL 0x0086 Output Compare Register A Low Byte
|
||
; OCR3AH 0x0087 Output Compare Register A High Byte
|
||
; TCNT3L 0x0088 Counter Register Low Byte
|
||
; TCNT3H 0x0089 Counter Register High Byte
|
||
; TCCR3B 0x008A Timer/Counter3 Control Register B
|
||
; TCCR3B.ICNC3 7 Input Capture Noise Canceler
|
||
; TCCR3B.ICES3 6 Input CaptureEdgeSelect
|
||
; TCCR3B.WGM33 4 Waveform Generation Mode 3
|
||
; TCCR3B.WGM32 3 Waveform Generation Mode 2
|
||
; TCCR3B.CS32 2 Clock Select 2
|
||
; TCCR3B.CS31 1 Clock Select 1
|
||
; TCCR3B.CS30 0 Clock Select 0
|
||
; TCCR3A 0x008B Timer/Counter3 Control Register A
|
||
; TCCR3A.COM3A1 7 Compare Output Mode for Channel A 1
|
||
; TCCR3A.COM3A0 6 Compare Output Mode for Channel A 0
|
||
; TCCR3A.COM3B1 5 Compare Output Mode for Channel B 1
|
||
; TCCR3A.COM3B0 4 Compare Output Mode for Channel B 0
|
||
; TCCR3A.COM3C1 3 Compare Output Mode for Channel C 1
|
||
; TCCR3A.COM3C0 2 Compare Output Mode for Channel C 0
|
||
; TCCR3A.WGM31 1 Waveform Generation Mode 1
|
||
; TCCR3A.WGM30 0 Waveform Generation Mode 0
|
||
; TCCR3C 0x008C Timer/Counter3 Control Register C
|
||
; TCCR3C.FOC3A 7 Force Output Compare for Channel A
|
||
; TCCR3C.FOC3B 6 Force Output Compare for Channel B
|
||
; TCCR3C.FOC3C 5 Force Output Compare for Channel C
|
||
; RESERVED008D 0x008D RESERVED
|
||
; RESERVED008E 0x008E RESERVED
|
||
; RESERVED008F 0x008F RESERVED
|
||
; UBRR0H 0x0090 USART0 Baud Rate Register High
|
||
; RESERVED0091 0x0091 RESERVED
|
||
; RESERVED0092 0x0092 RESERVED
|
||
; RESERVED0093 0x0093 RESERVED
|
||
; RESERVED0094 0x0094 RESERVED
|
||
; UCSR0C 0x0095 USART Control and Status Register C
|
||
; UCSR0C.UMSEL 6 USART Mode Select
|
||
; UCSR0C.UPM1 5 Parity Mode 1
|
||
; UCSR0C.UPM0 4 Parity Mode 0
|
||
; UCSR0C.USBS 3 Stop Bit Select
|
||
; UCSR0C.UCSZ1 2 Character Size 1
|
||
; UCSR0C.UCSZ0 1 Character Size 0
|
||
; UCSR0C.UCPOL 0 Clock Polarity
|
||
; RESERVED0096 0x0096 RESERVED
|
||
; RESERVED0097 0x0097 RESERVED
|
||
; UBRR1H 0x0098 USART1 Baud Rate Register High
|
||
; UBRR1L 0x0099 USART1 Baud Rate Register Low
|
||
; UCSR1B 0x009A USART Control and Status Register B
|
||
; UCSR1B.RXCIE 7 RX Complete Interrupt Enable
|
||
; UCSR1B.TXCIE 6 TX Complete Interrupt Enable
|
||
; UCSR1B.UDRIE 5 USART Data Register Empty Interrupt Enable
|
||
; UCSR1B.RXEN 4 Receiver Enable
|
||
; UCSR1B.TXEN 3 Transmitter Enable
|
||
; UCSR1B.UCSZ2 2 Character Size
|
||
; UCSR1B.RXB8 1 Receive Data Bit 8
|
||
; UCSR1B.TXB8 0 Transmit Data Bit8
|
||
; UCSR1A 0x009B USART Control and Status Register A
|
||
; UCSR1A.RXC 7 USART Receive Complete
|
||
; UCSR1A.TXC 6 USART Transmit Complete
|
||
; UCSR1A.UDRE 5 USART Data Register Empty
|
||
; UCSR1A.FE 4 Frame Error
|
||
; UCSR1A.DOR 3 Data OverRun
|
||
; UCSR1A.UPE 2 Parity Error
|
||
; UCSR1A.U2X 1 Double the USART Transmission Speed
|
||
; UCSR1A.MPCM 0 Multi-Processor Communication Mode
|
||
; UDR1 0x009C USART1 I/O Data Register
|
||
; UCSR1C 0x009D USART Control and Status Register C
|
||
; UCSR1C.UMSEL 6 USART Mode Select
|
||
; UCSR1C.UPM1 5 Parity Mode 1
|
||
; UCSR1C.UPM0 4 Parity Mode 0
|
||
; UCSR1C.USBS 3 Stop Bit Select
|
||
; UCSR1C.UCSZ1 2 Character Size 1
|
||
; UCSR1C.UCSZ0 1 Character Size 0
|
||
; UCSR1C.UCPOL 0 Clock Polarity
|
||
; RESERVED009E 0x009E RESERVED
|
||
; RESERVED009F 0x009F RESERVED
|
||
|
||
|
||
.ATmega161_L
|
||
SUBARCH=5
|
||
; doc1228.pdf
|
||
;
|
||
|
||
RAM=1024
|
||
ROM=16384
|
||
EEPROM=512
|
||
|
||
|
||
; MEMORY MAP
|
||
area DATA FSR 0x0000:0x0060
|
||
area DATA I_SRAM 0x0060:0x0460 Internal SRAM
|
||
area DATA E_SRAM 0x0460:0x10000 External SRAM
|
||
|
||
|
||
; Interrupt and reset vector assignments
|
||
entry __RESET 0x0000 Hardware Pin, Power-on Reset and Watchdog Reset
|
||
entry INT0_ 0x0002 External Interrupt Request 0
|
||
entry INT1_ 0x0004 External Interrupt Request 1
|
||
entry INT2_ 0x0006 External Interrupt Request 2
|
||
entry TIMER2_COMP 0x0008 Timer/Counter2 Compare Match
|
||
entry TIMER2_OVF 0x000A Timer/Counter2 Overflow
|
||
entry TIMER1_CAPT 0x000C Timer/Counter1 Capture Event
|
||
entry TIMER1_COMPA 0x000E Timer/Counter1 Compare Match A
|
||
entry TIMER1_COMPB 0x0010 Timer/Counter1 Compare Match B
|
||
entry TIMER1_OVF 0x0012 Timer/Counter1 Overflow
|
||
entry TIMER0_COMP 0x0014 Timer/Counter0 Compare Match
|
||
entry TIMER0_OVF 0x0016 Timer/Counter0 Overflow
|
||
entry SPI_STC 0x0018 Serial Transfer Complete
|
||
entry UART0_RX 0x001A UART0, Rx Complete
|
||
entry UART1_RX 0x001C UART1, Rx Complete
|
||
entry UART0_UDRE 0x001E UART0 Data Register Empty
|
||
entry UART1_UDRE 0x0020 UART1 Data Register Empty
|
||
entry UART0_TX 0x0022 UART0, Tx Complete
|
||
entry UART1_TX 0x0024 UART1, Tx Complete
|
||
entry EE_RDY 0x0026 EEPROM Ready
|
||
entry ANA_COMP 0x0028 Analog Comparator
|
||
|
||
|
||
; INPUT/OUTPUT PORTS
|
||
UBRR1 0x0000 UART1 Baud Rate Register Low Byte
|
||
UCSR1B 0x0001 UART1 Control and Status Register
|
||
UCSR1B.RXCIE1 7 RX Complete Interrupt Enable
|
||
UCSR1B.TXCIE1 6 TX Complete Interrupt Enable
|
||
UCSR1B.UDRIE1 5 UART Data Register Empty Interrupt Enable
|
||
UCSR1B.RXEN1 4 Receiver Enable
|
||
UCSR1B.TXEN1 3 Transmitter Enable
|
||
UCSR1B.CHR91 2 9-bit Characters
|
||
UCSR1B.RXB81 1 Receive Data Bit 8
|
||
UCSR1B.TXB81 0 Transmit Data Bit 8
|
||
UCSR1A 0x0002 UART1 Control and Status Register
|
||
UCSR1A.RXC1 7 UART Receive Complete
|
||
UCSR1A.TXC1 6 UART Transmit Complete
|
||
UCSR1A.UDRE1 5 UART Data Register Empty
|
||
UCSR1A.FE1 4 Framing Error
|
||
UCSR1A.OR1 3 OverRun
|
||
UCSR1A.U2X1 1 Double the UART Transmission Speed
|
||
UCSR1A.MPCM1 0 Multi-processor Communication Mode
|
||
UDR1 0x0003 UART1 I/O Data Register
|
||
RESERVED0004 0x0004 RESERVED
|
||
PINE 0x0005 Port E Input Pins Address
|
||
PINE.PINE2 2
|
||
PINE.PINE1 1
|
||
PINE.PINE0 0
|
||
DDRE 0x0006 Port E Data Direction Register
|
||
DDRE.DDE2 2 Port E Data Direction Register bit 2
|
||
DDRE.DDE1 1 Port E Data Direction Register bit 1
|
||
DDRE.DDE0 0 Port E Data Direction Register bit 0
|
||
PORTE 0x0007 Port E Data Register
|
||
PORTE.PORTE2 2 Port E Data Register bit 2
|
||
PORTE.PORTE1 1 Port E Data Register bit 1
|
||
PORTE.PORTE0 0 Port E Data Register bit 0
|
||
ACSR 0x0008 Analog Comparator Control and Status Register
|
||
ACSR.ACD 7 Analog Comparator Disable
|
||
ACSR.AINBG 6 Analog Comparator Bandgap Select
|
||
ACSR.ACO 5 Analog Comparator Output
|
||
ACSR.ACI 4 Analog Comparator Interrupt Flag
|
||
ACSR.ACIE 3 Analog Comparator Interrupt Enable
|
||
ACSR.ACIC 2 Analog Comparator Input Capture Enable
|
||
ACSR.ACIS1 1 Analog Comparator Interrupt Mode Select 1
|
||
ACSR.ACIS0 0 Analog Comparator Interrupt Mode Select 0
|
||
UBRR0 0x0009 UART0 Baud Rate Register Low Byte
|
||
UCSR0B 0x000A UART0 Control and StatusRegister
|
||
UCSR0B.RXCIE0 7 RX Complete Interrupt Enable
|
||
UCSR0B.TXCIE0 6 TX Complete Interrupt Enable
|
||
UCSR0B.UDRIE0 5 UART Data Register Empty Interrupt Enable
|
||
UCSR0B.RXEN0 4 Receiver Enable
|
||
UCSR0B.TXEN0 3 Transmitter Enable
|
||
UCSR0B.CHR90 2 9-bit Characters
|
||
UCSR0B.RXB80 1 Receive Data Bit 8
|
||
UCSR0B.TXB80 0 Transmit Data Bit 8
|
||
UCSR0A 0x000B UART0 Control and Status Register
|
||
UCSR0A.RXC0 7 UART Receive Complete
|
||
UCSR0A.TXC0 6 UART Transmit Complete
|
||
UCSR0A.UDRE0 5 UART Data Register Empty
|
||
UCSR0A.FE0 4 Framing Error
|
||
UCSR0A.OR0 3 OverRun
|
||
UCSR0A.U2X0 1 Double the UART Transmission Speed
|
||
UCSR0A.MPCM0 0 Multi-processor Communication Mode
|
||
UDR0 0x000C UART0 I/O Data Register
|
||
SPCR 0x000D SPI Control Register
|
||
SPCR.SPIE 7 SPI Interrupt Enable
|
||
SPCR.SPE 6 SPI Enable
|
||
SPCR.DORD 5 Data Order
|
||
SPCR.MSTR 4 Master/Slave Select
|
||
SPCR.CPOL 3 Clock Polarity
|
||
SPCR.CPHA 2 Clock Phase
|
||
SPCR.SPR1 1 SPI Clock Rate Select 1
|
||
SPCR.SPR0 0 SPI Clock Rate Select 0
|
||
SPSR 0x000E SPI Status Register
|
||
SPSR.SPIF 7 SPI Interrupt Flag
|
||
SPSR.WCOL 6 Write Collision Flag
|
||
SPSR.SPI2X 0 Double SPI Speed Bit
|
||
SPDR 0x000F SPI Data Register
|
||
PIND 0x0010 Port D Input Pins Address
|
||
PIND.PIND7 7
|
||
PIND.PIND6 6
|
||
PIND.PIND5 5
|
||
PIND.PIND4 4
|
||
PIND.PIND3 3
|
||
PIND.PIND2 2
|
||
PIND.PIND1 1
|
||
PIND.PIND0 0
|
||
DDRD 0x0011 Port D Data Direction Register
|
||
DDRD.DDD7 7 Port D Data Direction Register bit 7
|
||
DDRD.DDD6 6 Port D Data Direction Register bit 6
|
||
DDRD.DDD5 5 Port D Data Direction Register bit 5
|
||
DDRD.DDD4 4 Port D Data Direction Register bit 4
|
||
DDRD.DDD3 3 Port D Data Direction Register bit 3
|
||
DDRD.DDD2 2 Port D Data Direction Register bit 2
|
||
DDRD.DDD1 1 Port D Data Direction Register bit 1
|
||
DDRD.DDD0 0 Port D Data Direction Register bit 0
|
||
PORTD 0x0012 Port D Data Register
|
||
PORTD.PORTD7 7 Port D Data Register bit 7
|
||
PORTD.PORTD6 6 Port D Data Register bit 6
|
||
PORTD.PORTD5 5 Port D Data Register bit 5
|
||
PORTD.PORTD4 4 Port D Data Register bit 4
|
||
PORTD.PORTD3 3 Port D Data Register bit 3
|
||
PORTD.PORTD2 2 Port D Data Register bit 2
|
||
PORTD.PORTD1 1 Port D Data Register bit 1
|
||
PORTD.PORTD0 0 Port D Data Register bit 0
|
||
PINC 0x0013 Port C Input Pins Address
|
||
PINC.PINC7 7
|
||
PINC.PINC6 6
|
||
PINC.PINC5 5
|
||
PINC.PINC4 4
|
||
PINC.PINC3 3
|
||
PINC.PINC2 2
|
||
PINC.PINC1 1
|
||
PINC.PINC0 0
|
||
DDRC 0x0014 Port C Data Direction Register
|
||
DDRC.DDC7 7 Port C Data Direction Register bit 7
|
||
DDRC.DDC6 6 Port C Data Direction Register bit 6
|
||
DDRC.DDC5 5 Port C Data Direction Register bit 5
|
||
DDRC.DDC4 4 Port C Data Direction Register bit 4
|
||
DDRC.DDC3 3 Port C Data Direction Register bit 3
|
||
DDRC.DDC2 2 Port C Data Direction Register bit 2
|
||
DDRC.DDC1 1 Port C Data Direction Register bit 1
|
||
DDRC.DDC0 0 Port C Data Direction Register bit 0
|
||
PORTC 0x0015 Port C Data Register
|
||
PORTC.PORTC7 7 Port C Data Register bit 7
|
||
PORTC.PORTC6 6 Port C Data Register bit 6
|
||
PORTC.PORTC5 5 Port C Data Register bit 5
|
||
PORTC.PORTC4 4 Port C Data Register bit 4
|
||
PORTC.PORTC3 3 Port C Data Register bit 3
|
||
PORTC.PORTC2 2 Port C Data Register bit 2
|
||
PORTC.PORTC1 1 Port C Data Register bit 1
|
||
PORTC.PORTC0 0 Port C Data Register bit 0
|
||
PINB 0x0016 Port B Input Pins Address
|
||
PINB.PINB7 7
|
||
PINB.PINB6 6
|
||
PINB.PINB5 5
|
||
PINB.PINB4 4
|
||
PINB.PINB3 3
|
||
PINB.PINB2 2
|
||
PINB.PINB1 1
|
||
PINB.PINB0 0
|
||
DDRB 0x0017 Port B Data Direction Register
|
||
DDRB.DDB7 7 Port B Data Direction Register bit 7
|
||
DDRB.DDB6 6 Port B Data Direction Register bit 6
|
||
DDRB.DDB5 5 Port B Data Direction Register bit 5
|
||
DDRB.DDB4 4 Port B Data Direction Register bit 4
|
||
DDRB.DDB3 3 Port B Data Direction Register bit 3
|
||
DDRB.DDB2 2 Port B Data Direction Register bit 2
|
||
DDRB.DDB1 1 Port B Data Direction Register bit 1
|
||
DDRB.DDB0 0 Port B Data Direction Register bit 0
|
||
PORTB 0x0018 Port B Data Register
|
||
PORTB.PORTB7 7 Port B Data Register bit 7
|
||
PORTB.PORTB6 6 Port B Data Register bit 6
|
||
PORTB.PORTB5 5 Port B Data Register bit 5
|
||
PORTB.PORTB4 4 Port B Data Register bit 4
|
||
PORTB.PORTB3 3 Port B Data Register bit 3
|
||
PORTB.PORTB2 2 Port B Data Register bit 2
|
||
PORTB.PORTB1 1 Port B Data Register bit 1
|
||
PORTB.PORTB0 0 Port B Data Register bit 0
|
||
PINA 0x0019 Port A Input Pins Address
|
||
PINA.PINA7 7
|
||
PINA.PINA6 6
|
||
PINA.PINA5 5
|
||
PINA.PINA4 4
|
||
PINA.PINA3 3
|
||
PINA.PINA2 2
|
||
PINA.PINA1 1
|
||
PINA.PINA0 0
|
||
DDRA 0x001A Port A Data Direction Register
|
||
DDRA.DDA7 7 Port A Data Direction Register bit 7
|
||
DDRA.DDA6 6 Port A Data Direction Register bit 6
|
||
DDRA.DDA5 5 Port A Data Direction Register bit 5
|
||
DDRA.DDA4 4 Port A Data Direction Register bit 4
|
||
DDRA.DDA3 3 Port A Data Direction Register bit 3
|
||
DDRA.DDA2 2 Port A Data Direction Register bit 2
|
||
DDRA.DDA1 1 Port A Data Direction Register bit 1
|
||
DDRA.DDA0 0 Port A Data Direction Register bit 0
|
||
PORTA 0x001B Port A Data Register
|
||
PORTA.PORTA7 7 Port A Data Register bit 7
|
||
PORTA.PORTA6 6 Port A Data Register bit 6
|
||
PORTA.PORTA5 5 Port A Data Register bit 5
|
||
PORTA.PORTA4 4 Port A Data Register bit 4
|
||
PORTA.PORTA3 3 Port A Data Register bit 3
|
||
PORTA.PORTA2 2 Port A Data Register bit 2
|
||
PORTA.PORTA1 1 Port A Data Register bit 1
|
||
PORTA.PORTA0 0 Port A Data Register bit 0
|
||
EECR 0x001C EEPROM Control Register
|
||
EECR.EERIE 3 EEPROM Ready Interrupt Enable
|
||
EECR.EEMWE 2 EEPROM Master Write Enable
|
||
EECR.EEWE 1 EEPROM Write Enable
|
||
EECR.EERE 0 EEPROM Read Enable
|
||
EEDR 0x001D EEPROM Data Register
|
||
EEARL 0x001E EEPROM Address Register Low Byte
|
||
EEARL.EEAR7 7 EEPROM Addres 7
|
||
EEARL.EEAR6 6 EEPROM Addres 6
|
||
EEARL.EEAR5 5 EEPROM Addres 5
|
||
EEARL.EEAR4 4 EEPROM Addres 4
|
||
EEARL.EEAR3 3 EEPROM Addres 3
|
||
EEARL.EEAR2 2 EEPROM Addres 2
|
||
EEARL.EEAR1 1 EEPROM Addres 1
|
||
EEARL.EEAR0 0 EEPROM Addres 0
|
||
EEARH 0x001F EEPROM Address Register High Byte
|
||
UBRRHI 0x0020 UART0 and UART1 High Byte Baud Rate Register
|
||
WDTCR 0x0021 Watchdog Timer Control Register
|
||
WDTCR.WDTOE 4 Watchdog Turn-off Enable
|
||
WDTCR.WDE 3 Watchdog Enable
|
||
WDTCR.WDP2 2 Watchdog Timer Prescaler 2
|
||
WDTCR.WDP1 1 Watchdog Timer Prescaler 1
|
||
WDTCR.WDP0 0 Watchdog Timer Prescaler 0
|
||
OCR2 0x0022 Timer/Counter2 Output Compare Register
|
||
TCNT2 0x0023 Timer/Counter2 Counter Register
|
||
ICR1L 0x0024 Input Capture Register Low Byte
|
||
ICR1H 0x0025 Input Capture Register High Byte
|
||
ASSR 0x0026 Asynchronous Status Register
|
||
ASSR.AS2 3 Asynchronous Timer/Counter2 Mode
|
||
ASSR.TCN2UB 2 Timer/Counter2 Update Busy
|
||
ASSR.OCR2UB 1 Output Compare Register2 Update Busy
|
||
ASSR.TCR2UB 0 Timer/Counter Control Register2 Update Busy
|
||
TCCR2 0x0027 Timer/Counter2 Control Register
|
||
TCCR2.FOC2 7 Force Output Compare
|
||
TCCR2.PWM2 6 Pulse Width Modulator Enable
|
||
TCCR2.COM21 5 Compare Output Mode, Bit 1
|
||
TCCR2.COM20 4 Compare Output Mode, Bit 0
|
||
TCCR2.CTC2 3 Clear Timer/Counter on Compare Match
|
||
TCCR2.CS22 2 Clock Select Bit 2
|
||
TCCR2.CS21 1 Clock Select Bit 1
|
||
TCCR2.CS20 0 Clock Select Bit 0
|
||
OCR1BL 0x0028 Output Compare Register B Low Byte
|
||
OCR1BH 0x0029 Output Compare Register B High Byte
|
||
OCR1AL 0x002A Output Compare Register A Low Byte
|
||
OCR1AH 0x002B Output Compare Register A High Byte
|
||
TCNT1L 0x002C Counter Register Low Byte
|
||
TCNT1H 0x002D Counter Register High Byte
|
||
TCCR1B 0x002E Timer/Counter1 Control Register
|
||
TCCR1B.ICNC1 7 Input Capture1 Noise Canceler (4 CKs)
|
||
TCCR1B.ICES1 6 Input Capture1 Edge Select
|
||
TCCR1B.CTC1 3 Clear Timer/Counter1 on Compare Match
|
||
TCCR1B.CS12 2 Clock Select1, Bit 2
|
||
TCCR1B.CS11 1 Clock Select1, Bit 1
|
||
TCCR1B.CS10 0 Clock Select1, Bit 0
|
||
TCCR1A 0x002F Timer/Counter1 Control Register A
|
||
TCCR1A.COM1A1 7 Compare Output Mode1A, Bit 1
|
||
TCCR1A.COM1A0 6 Compare Output Mode1A, Bit 0
|
||
TCCR1A.COM1B1 5 Compare Output Mode1B, Bit 1
|
||
TCCR1A.COM1B0 4 Compare Output Mode1B, Bit 0
|
||
TCCR1A.FOC1A 3 Force Output Compare1A
|
||
TCCR1A.FOC1B 2 Force Output Compare1B
|
||
TCCR1A.PWM11 1 Pulse Width Modulator Select Bit 1
|
||
TCCR1A.PWM10 0 Pulse Width Modulator Select Bit 0
|
||
SFIOR 0x0030 Special Function IO Register
|
||
SFIOR.PSR2 1 Prescaler Reset Timer/Counter2
|
||
SFIOR.PSR10 0 Prescaler Reset Timer/Counter1 and Timer/Counter0
|
||
OCR0 0x0031 Timer/Counter0 Output Compare Register
|
||
TCNT0 0x0032 Timer/Counter0 Counter Register
|
||
TCCR0 0x0033 Timer/Counter0 Control Register
|
||
TCCR0.FOC0 7 Force Output Compare
|
||
TCCR0.PWM0 6 Pulse Width Modulator Enable
|
||
TCCR0.COM01 5 Compare Output Mode, Bit 1
|
||
TCCR0.COM00 4 Compare Output Mode, Bit 0
|
||
TCCR0.CTC0 3 Clear Timer/Counter on Compare Match
|
||
TCCR0.CS02 2 Clock Select Bit 2
|
||
TCCR0.CS01 1 Clock Select Bit 1
|
||
TCCR0.CS00 0 Clock Select Bit 0
|
||
MCUSR 0x0034 MCU Status Register
|
||
MCUSR.WDRF 3 Watchdog Reset Flag
|
||
MCUSR.BORF 2 Brown-out Reset Flag
|
||
MCUSR.EXTRF 1 External Reset Flag
|
||
MCUSR.PORF 0 Power-on Reset Flag
|
||
MCUCR 0x0035 MCU Control Register
|
||
MCUCR.SRE 7 External SRAM Enable
|
||
MCUCR.SRW10 6 External SRAM Wait State
|
||
MCUCR.SE 5 Sleep Enable
|
||
MCUCR.SM1 4 Sleep Mode Select Bit 1
|
||
MCUCR.ISC11 3 Interrupt Sense Control 1 Bit 1
|
||
MCUCR.ISC10 2 Interrupt Sense Control 1 Bit 0
|
||
MCUCR.ISC01 1 Interrupt Sense Control 0 Bit 1
|
||
MCUCR.ISC00 0 Interrupt Sense Control 0 Bit 0
|
||
EMCUCR 0x0036 Extended MCU Control Register
|
||
EMCUCR.SM0 7 Sleep Mode Bit 0
|
||
EMCUCR.SRL2 6 External SRAM Limit 2
|
||
EMCUCR.SRL1 5 External SRAM Limit 1
|
||
EMCUCR.SRL0 4 External SRAM Limit 0
|
||
EMCUCR.SRW01 3 External SRAM Wait State Select Bit 01
|
||
EMCUCR.SRW00 2 External SRAM Wait State Select Bit 00
|
||
EMCUCR.SRW11 1 External SRAM Wait State Select Bit 11
|
||
EMCUCR.ISC2 0 Interrupt Sense Control 2
|
||
SPMCR 0x0037 Store Program Memory Control Register
|
||
SPMCR.BLBSET 3 Boot Lock Bit Set
|
||
SPMCR.PGWRT 2 Page Write
|
||
SPMCR.PGERS 1 Page Erase
|
||
SPMCR.SPMEN 0 Store Program Memory Enable
|
||
TIFR 0x0038 Timer/Counter Interrupt Flag Register
|
||
TIFR.TOV1 7 Timer/Counter1 Overflow Flag
|
||
TIFR.OCF1A 6 Output Compare Flag 1A
|
||
TIFR.OCIFB 5 Output Compare Flag 1B
|
||
TIFR.TOV2 4 Timer/Counter2 Overflow Flag
|
||
TIFR.ICF1 3 Input Capture Flag 1
|
||
TIFR.OCF2 2 Output Compare Flag 2
|
||
TIFR.TOV0 1 Timer/Counter0 Overflow Flag
|
||
TIFR.OCF0 0 Output Compare Flag 0
|
||
TIMSK 0x0039 Timer/Counter Interrupt Mask Register
|
||
TIMSK.TOIE1 7 Timer/Counter1 Overflow Interrupt Enable
|
||
TIMSK.OCIE1A 6 Timer/Counter1 Output CompareA Match Interrupt Enable
|
||
TIMSK.OCIE1B 5 Timer/Counter1 Output CompareB Match Interrupt Enable
|
||
TIMSK.TOIE2 4 Timer/Counter2 Overflow Interrupt Enable
|
||
TIMSK.TICIE1 3 Timer/Counter1 Input Capture Interrupt Enable
|
||
TIMSK.OCIE2 2 Timer/Counter2 Output Compare Match Interrupt Enable
|
||
TIMSK.TOIE0 1 Timer/Counter0 Overflow Interrupt Enable
|
||
TIMSK.OCIE0 0 Timer/Counter0 Output Compare Match Interrupt Enable
|
||
GIFR 0x003A General Interrupt Flag
|
||
GIFR.INTF1 7 External Interrupt Flag1
|
||
GIFR.INTF0 6 External Interrupt Flag0
|
||
GIFR.INTF2 5 External Interrupt Flag2
|
||
GIMSK 0x003B General Interrupt Mask Register
|
||
GIMSK.INT1 7 External Interrupt Request 1 Enable
|
||
GIMSK.INT0 6 External Interrupt Request 0 Enable
|
||
GIMSK.INT2 5 External Interrupt Request 2 Enable
|
||
RESERVED003C 0x003C RESERVED
|
||
SPL 0x003D Stack Pointer Low
|
||
SPL.SP7 7
|
||
SPL.SP6 6
|
||
SPL.SP5 5
|
||
SPL.SP4 4
|
||
SPL.SP3 3
|
||
SPL.SP2 2
|
||
SPL.SP1 1
|
||
SPL.SP0 0
|
||
SPH 0x003E Stack Pointer High
|
||
SPH.SP15 15
|
||
SPH.SP14 14
|
||
SPH.SP13 13
|
||
SPH.SP12 12
|
||
SPH.SP11 11
|
||
SPH.SP10 10
|
||
SPH.SP9 9
|
||
SPH.SP8 8
|
||
SREG 0x003F Status Register
|
||
SREG.I 7 Global Interrupt Enable
|
||
SREG.T 6 Bit Copy Storage
|
||
SREG.H 5 Half Carry Flag
|
||
SREG.S 4 Sign Bit
|
||
SREG.V 3 Two's Complement Overflow Flag
|
||
SREG.N 2 Negative Flag
|
||
SREG.Z 1 Zero Flag
|
||
SREG.C 0 CarryFlag
|
||
|
||
; UBRR1 0x0020 UART1 Baud Rate Register Low Byte
|
||
; UCSR1B 0x0021 UART1 Control and Status Register
|
||
; UCSR1B.RXCIE1 7 RX Complete Interrupt Enable
|
||
; UCSR1B.TXCIE1 6 TX Complete Interrupt Enable
|
||
; UCSR1B.UDRIE1 5 UART Data Register Empty Interrupt Enable
|
||
; UCSR1B.RXEN1 4 Receiver Enable
|
||
; UCSR1B.TXEN1 3 Transmitter Enable
|
||
; UCSR1B.CHR91 2 9-bit Characters
|
||
; UCSR1B.RXB81 1 Receive Data Bit 8
|
||
; UCSR1B.TXB81 0 Transmit Data Bit 8
|
||
; UCSR1A 0x0022 UART1 Control and Status Register
|
||
; UCSR1A.RXC1 7 UART Receive Complete
|
||
; UCSR1A.TXC1 6 UART Transmit Complete
|
||
; UCSR1A.UDRE1 5 UART Data Register Empty
|
||
; UCSR1A.FE1 4 Framing Error
|
||
; UCSR1A.OR1 3 OverRun
|
||
; UCSR1A.U2X1 1 Double the UART Transmission Speed
|
||
; UCSR1A.MPCM1 0 Multi-processor Communication Mode
|
||
; UDR1 0x0023 UART1 I/O Data Register
|
||
; RESERVED0024 0x0024 RESERVED
|
||
; PINE 0x0025 Port E Input Pins Address
|
||
; PINE.PINE2 2
|
||
; PINE.PINE1 1
|
||
; PINE.PINE0 0
|
||
; DDRE 0x0026 Port E Data Direction Register
|
||
; DDRE.DDE2 2 Port E Data Direction Register bit 2
|
||
; DDRE.DDE1 1 Port E Data Direction Register bit 1
|
||
; DDRE.DDE0 0 Port E Data Direction Register bit 0
|
||
; PORTE 0x0027 Port E Data Register
|
||
; PORTE.PORTE2 2 Port E Data Register bit 2
|
||
; PORTE.PORTE1 1 Port E Data Register bit 1
|
||
; PORTE.PORTE0 0 Port E Data Register bit 0
|
||
; ACSR 0x0028 Analog Comparator Control and Status Register
|
||
; ACSR.ACD 7 Analog Comparator Disable
|
||
; ACSR.AINBG 6 Analog Comparator Bandgap Select
|
||
; ACSR.ACO 5 Analog Comparator Output
|
||
; ACSR.ACI 4 Analog Comparator Interrupt Flag
|
||
; ACSR.ACIE 3 Analog Comparator Interrupt Enable
|
||
; ACSR.ACIC 2 Analog Comparator Input Capture Enable
|
||
; ACSR.ACIS1 1 Analog Comparator Interrupt Mode Select 1
|
||
; ACSR.ACIS0 0 Analog Comparator Interrupt Mode Select 0
|
||
; UBRR0 0x0029 UART0 Baud Rate Register Low Byte
|
||
; UCSR0B 0x002A UART0 Control and StatusRegister
|
||
; UCSR0B.RXCIE0 7 RX Complete Interrupt Enable
|
||
; UCSR0B.TXCIE0 6 TX Complete Interrupt Enable
|
||
; UCSR0B.UDRIE0 5 UART Data Register Empty Interrupt Enable
|
||
; UCSR0B.RXEN0 4 Receiver Enable
|
||
; UCSR0B.TXEN0 3 Transmitter Enable
|
||
; UCSR0B.CHR90 2 9-bit Characters
|
||
; UCSR0B.RXB80 1 Receive Data Bit 8
|
||
; UCSR0B.TXB80 0 Transmit Data Bit 8
|
||
; UCSR0A 0x002B UART0 Control and Status Register
|
||
; UCSR0A.RXC0 7 UART Receive Complete
|
||
; UCSR0A.TXC0 6 UART Transmit Complete
|
||
; UCSR0A.UDRE0 5 UART Data Register Empty
|
||
; UCSR0A.FE0 4 Framing Error
|
||
; UCSR0A.OR0 3 OverRun
|
||
; UCSR0A.U2X0 1 Double the UART Transmission Speed
|
||
; UCSR0A.MPCM0 0 Multi-processor Communication Mode
|
||
; UDR0 0x002C UART0 I/O Data Register
|
||
; SPCR 0x002D SPI Control Register
|
||
; SPCR.SPIE 7 SPI Interrupt Enable
|
||
; SPCR.SPE 6 SPI Enable
|
||
; SPCR.DORD 5 Data Order
|
||
; SPCR.MSTR 4 Master/Slave Select
|
||
; SPCR.CPOL 3 Clock Polarity
|
||
; SPCR.CPHA 2 Clock Phase
|
||
; SPCR.SPR1 1 SPI Clock Rate Select 1
|
||
; SPCR.SPR0 0 SPI Clock Rate Select 0
|
||
; SPSR 0x002E SPI Status Register
|
||
; SPSR.SPIF 7 SPI Interrupt Flag
|
||
; SPSR.WCOL 6 Write Collision Flag
|
||
; SPSR.SPI2X 0 Double SPI Speed Bit
|
||
; SPDR 0x002F SPI Data Register
|
||
; PIND 0x0030 Port D Input Pins Address
|
||
; PIND.PIND7 7
|
||
; PIND.PIND6 6
|
||
; PIND.PIND5 5
|
||
; PIND.PIND4 4
|
||
; PIND.PIND3 3
|
||
; PIND.PIND2 2
|
||
; PIND.PIND1 1
|
||
; PIND.PIND0 0
|
||
; DDRD 0x0031 Port D Data Direction Register
|
||
; DDRD.DDD7 7 Port D Data Direction Register bit 7
|
||
; DDRD.DDD6 6 Port D Data Direction Register bit 6
|
||
; DDRD.DDD5 5 Port D Data Direction Register bit 5
|
||
; DDRD.DDD4 4 Port D Data Direction Register bit 4
|
||
; DDRD.DDD3 3 Port D Data Direction Register bit 3
|
||
; DDRD.DDD2 2 Port D Data Direction Register bit 2
|
||
; DDRD.DDD1 1 Port D Data Direction Register bit 1
|
||
; DDRD.DDD0 0 Port D Data Direction Register bit 0
|
||
; PORTD 0x0032 Port D Data Register
|
||
; PORTD.PORTD7 7 Port D Data Register bit 7
|
||
; PORTD.PORTD6 6 Port D Data Register bit 6
|
||
; PORTD.PORTD5 5 Port D Data Register bit 5
|
||
; PORTD.PORTD4 4 Port D Data Register bit 4
|
||
; PORTD.PORTD3 3 Port D Data Register bit 3
|
||
; PORTD.PORTD2 2 Port D Data Register bit 2
|
||
; PORTD.PORTD1 1 Port D Data Register bit 1
|
||
; PORTD.PORTD0 0 Port D Data Register bit 0
|
||
; PINC 0x0033 Port C Input Pins Address
|
||
; PINC.PINC7 7
|
||
; PINC.PINC6 6
|
||
; PINC.PINC5 5
|
||
; PINC.PINC4 4
|
||
; PINC.PINC3 3
|
||
; PINC.PINC2 2
|
||
; PINC.PINC1 1
|
||
; PINC.PINC0 0
|
||
; DDRC 0x0034 Port C Data Direction Register
|
||
; DDRC.DDC7 7 Port C Data Direction Register bit 7
|
||
; DDRC.DDC6 6 Port C Data Direction Register bit 6
|
||
; DDRC.DDC5 5 Port C Data Direction Register bit 5
|
||
; DDRC.DDC4 4 Port C Data Direction Register bit 4
|
||
; DDRC.DDC3 3 Port C Data Direction Register bit 3
|
||
; DDRC.DDC2 2 Port C Data Direction Register bit 2
|
||
; DDRC.DDC1 1 Port C Data Direction Register bit 1
|
||
; DDRC.DDC0 0 Port C Data Direction Register bit 0
|
||
; PORTC 0x0035 Port C Data Register
|
||
; PORTC.PORTC7 7 Port C Data Register bit 7
|
||
; PORTC.PORTC6 6 Port C Data Register bit 6
|
||
; PORTC.PORTC5 5 Port C Data Register bit 5
|
||
; PORTC.PORTC4 4 Port C Data Register bit 4
|
||
; PORTC.PORTC3 3 Port C Data Register bit 3
|
||
; PORTC.PORTC2 2 Port C Data Register bit 2
|
||
; PORTC.PORTC1 1 Port C Data Register bit 1
|
||
; PORTC.PORTC0 0 Port C Data Register bit 0
|
||
; PINB 0x0036 Port B Input Pins Address
|
||
; PINB.PINB7 7
|
||
; PINB.PINB6 6
|
||
; PINB.PINB5 5
|
||
; PINB.PINB4 4
|
||
; PINB.PINB3 3
|
||
; PINB.PINB2 2
|
||
; PINB.PINB1 1
|
||
; PINB.PINB0 0
|
||
; DDRB 0x0037 Port B Data Direction Register
|
||
; DDRB.DDB7 7 Port B Data Direction Register bit 7
|
||
; DDRB.DDB6 6 Port B Data Direction Register bit 6
|
||
; DDRB.DDB5 5 Port B Data Direction Register bit 5
|
||
; DDRB.DDB4 4 Port B Data Direction Register bit 4
|
||
; DDRB.DDB3 3 Port B Data Direction Register bit 3
|
||
; DDRB.DDB2 2 Port B Data Direction Register bit 2
|
||
; DDRB.DDB1 1 Port B Data Direction Register bit 1
|
||
; DDRB.DDB0 0 Port B Data Direction Register bit 0
|
||
; PORTB 0x0038 Port B Data Register
|
||
; PORTB.PORTB7 7 Port B Data Register bit 7
|
||
; PORTB.PORTB6 6 Port B Data Register bit 6
|
||
; PORTB.PORTB5 5 Port B Data Register bit 5
|
||
; PORTB.PORTB4 4 Port B Data Register bit 4
|
||
; PORTB.PORTB3 3 Port B Data Register bit 3
|
||
; PORTB.PORTB2 2 Port B Data Register bit 2
|
||
; PORTB.PORTB1 1 Port B Data Register bit 1
|
||
; PORTB.PORTB0 0 Port B Data Register bit 0
|
||
; PINA 0x0039 Port A Input Pins Address
|
||
; PINA.PINA7 7
|
||
; PINA.PINA6 6
|
||
; PINA.PINA5 5
|
||
; PINA.PINA4 4
|
||
; PINA.PINA3 3
|
||
; PINA.PINA2 2
|
||
; PINA.PINA1 1
|
||
; PINA.PINA0 0
|
||
; DDRA 0x003A Port A Data Direction Register
|
||
; DDRA.DDA7 7 Port A Data Direction Register bit 7
|
||
; DDRA.DDA6 6 Port A Data Direction Register bit 6
|
||
; DDRA.DDA5 5 Port A Data Direction Register bit 5
|
||
; DDRA.DDA4 4 Port A Data Direction Register bit 4
|
||
; DDRA.DDA3 3 Port A Data Direction Register bit 3
|
||
; DDRA.DDA2 2 Port A Data Direction Register bit 2
|
||
; DDRA.DDA1 1 Port A Data Direction Register bit 1
|
||
; DDRA.DDA0 0 Port A Data Direction Register bit 0
|
||
; PORTA 0x003B Port A Data Register
|
||
; PORTA.PORTA7 7 Port A Data Register bit 7
|
||
; PORTA.PORTA6 6 Port A Data Register bit 6
|
||
; PORTA.PORTA5 5 Port A Data Register bit 5
|
||
; PORTA.PORTA4 4 Port A Data Register bit 4
|
||
; PORTA.PORTA3 3 Port A Data Register bit 3
|
||
; PORTA.PORTA2 2 Port A Data Register bit 2
|
||
; PORTA.PORTA1 1 Port A Data Register bit 1
|
||
; PORTA.PORTA0 0 Port A Data Register bit 0
|
||
; EECR 0x003C EEPROM Control Register
|
||
; EECR.EERIE 3 EEPROM Ready Interrupt Enable
|
||
; EECR.EEMWE 2 EEPROM Master Write Enable
|
||
; EECR.EEWE 1 EEPROM Write Enable
|
||
; EECR.EERE 0 EEPROM Read Enable
|
||
; EEDR 0x003D EEPROM Data Register
|
||
; EEARL 0x003E EEPROM Address Register Low Byte
|
||
; EEARL.EEAR7 7 EEPROM Addres 7
|
||
; EEARL.EEAR6 6 EEPROM Addres 6
|
||
; EEARL.EEAR5 5 EEPROM Addres 5
|
||
; EEARL.EEAR4 4 EEPROM Addres 4
|
||
; EEARL.EEAR3 3 EEPROM Addres 3
|
||
; EEARL.EEAR2 2 EEPROM Addres 2
|
||
; EEARL.EEAR1 1 EEPROM Addres 1
|
||
; EEARL.EEAR0 0 EEPROM Addres 0
|
||
; EEARH 0x003F EEPROM Address Register High Byte
|
||
; UBRRHI 0x0040 UART0 and UART1 High Byte Baud Rate Register
|
||
; WDTCR 0x0041 Watchdog Timer Control Register
|
||
; WDTCR.WDTOE 4 Watchdog Turn-off Enable
|
||
; WDTCR.WDE 3 Watchdog Enable
|
||
; WDTCR.WDP2 2 Watchdog Timer Prescaler 2
|
||
; WDTCR.WDP1 1 Watchdog Timer Prescaler 1
|
||
; WDTCR.WDP0 0 Watchdog Timer Prescaler 0
|
||
; OCR2 0x0042 Timer/Counter2 Output Compare Register
|
||
; TCNT2 0x0043 Timer/Counter2 Counter Register
|
||
; ICR1L 0x0044 Input Capture Register Low Byte
|
||
; ICR1H 0x0045 Input Capture Register High Byte
|
||
; ASSR 0x0046 Asynchronous Status Register
|
||
; ASSR.AS2 3 Asynchronous Timer/Counter2 Mode
|
||
; ASSR.TCN2UB 2 Timer/Counter2 Update Busy
|
||
; ASSR.OCR2UB 1 Output Compare Register2 Update Busy
|
||
; ASSR.TCR2UB 0 Timer/Counter Control Register2 Update Busy
|
||
; TCCR2 0x0047 Timer/Counter2 Control Register
|
||
; TCCR2.FOC2 7 Force Output Compare
|
||
; TCCR2.PWM2 6 Pulse Width Modulator Enable
|
||
; TCCR2.COM21 5 Compare Output Mode, Bit 1
|
||
; TCCR2.COM20 4 Compare Output Mode, Bit 0
|
||
; TCCR2.CTC2 3 Clear Timer/Counter on Compare Match
|
||
; TCCR2.CS22 2 Clock Select Bit 2
|
||
; TCCR2.CS21 1 Clock Select Bit 1
|
||
; TCCR2.CS20 0 Clock Select Bit 0
|
||
; OCR1BL 0x0048 Output Compare Register B Low Byte
|
||
; OCR1BH 0x0049 Output Compare Register B High Byte
|
||
; OCR1AL 0x004A Output Compare Register A Low Byte
|
||
; OCR1AH 0x004B Output Compare Register A High Byte
|
||
; TCNT1L 0x004C Counter Register Low Byte
|
||
; TCNT1H 0x004D Counter Register High Byte
|
||
; TCCR1B 0x004E Timer/Counter1 Control Register
|
||
; TCCR1B.ICNC1 7 Input Capture1 Noise Canceler (4 CKs)
|
||
; TCCR1B.ICES1 6 Input Capture1 Edge Select
|
||
; TCCR1B.CTC1 3 Clear Timer/Counter1 on Compare Match
|
||
; TCCR1B.CS12 2 Clock Select1, Bit 2
|
||
; TCCR1B.CS11 1 Clock Select1, Bit 1
|
||
; TCCR1B.CS10 0 Clock Select1, Bit 0
|
||
; TCCR1A 0x004F Timer/Counter1 Control Register A
|
||
; TCCR1A.COM1A1 7 Compare Output Mode1A, Bit 1
|
||
; TCCR1A.COM1A0 6 Compare Output Mode1A, Bit 0
|
||
; TCCR1A.COM1B1 5 Compare Output Mode1B, Bit 1
|
||
; TCCR1A.COM1B0 4 Compare Output Mode1B, Bit 0
|
||
; TCCR1A.FOC1A 3 Force Output Compare1A
|
||
; TCCR1A.FOC1B 2 Force Output Compare1B
|
||
; TCCR1A.PWM11 1 Pulse Width Modulator Select Bit 1
|
||
; TCCR1A.PWM10 0 Pulse Width Modulator Select Bit 0
|
||
; SFIOR 0x0050 Special Function IO Register
|
||
; SFIOR.PSR2 1 Prescaler Reset Timer/Counter2
|
||
; SFIOR.PSR10 0 Prescaler Reset Timer/Counter1 and Timer/Counter0
|
||
; OCR0 0x0051 Timer/Counter0 Output Compare Register
|
||
; TCNT0 0x0052 Timer/Counter0 Counter Register
|
||
; TCCR0 0x0053 Timer/Counter0 Control Register
|
||
; TCCR0.FOC0 7 Force Output Compare
|
||
; TCCR0.PWM0 6 Pulse Width Modulator Enable
|
||
; TCCR0.COM01 5 Compare Output Mode, Bit 1
|
||
; TCCR0.COM00 4 Compare Output Mode, Bit 0
|
||
; TCCR0.CTC0 3 Clear Timer/Counter on Compare Match
|
||
; TCCR0.CS02 2 Clock Select Bit 2
|
||
; TCCR0.CS01 1 Clock Select Bit 1
|
||
; TCCR0.CS00 0 Clock Select Bit 0
|
||
; MCUSR 0x0054 MCU Status Register
|
||
; MCUSR.WDRF 3 Watchdog Reset Flag
|
||
; MCUSR.BORF 2 Brown-out Reset Flag
|
||
; MCUSR.EXTRF 1 External Reset Flag
|
||
; MCUSR.PORF 0 Power-on Reset Flag
|
||
; MCUCR 0x0055 MCU Control Register
|
||
; MCUCR.SRE 7 External SRAM Enable
|
||
; MCUCR.SRW10 6 External SRAM Wait State
|
||
; MCUCR.SE 5 Sleep Enable
|
||
; MCUCR.SM1 4 Sleep Mode Select Bit 1
|
||
; MCUCR.ISC11 3 Interrupt Sense Control 1 Bit 1
|
||
; MCUCR.ISC10 2 Interrupt Sense Control 1 Bit 0
|
||
; MCUCR.ISC01 1 Interrupt Sense Control 0 Bit 1
|
||
; MCUCR.ISC00 0 Interrupt Sense Control 0 Bit 0
|
||
; EMCUCR 0x0056 Extended MCU Control Register
|
||
; EMCUCR.SM0 7 Sleep Mode Bit 0
|
||
; EMCUCR.SRL2 6 External SRAM Limit 2
|
||
; EMCUCR.SRL1 5 External SRAM Limit 1
|
||
; EMCUCR.SRL0 4 External SRAM Limit 0
|
||
; EMCUCR.SRW01 3 External SRAM Wait State Select Bit 01
|
||
; EMCUCR.SRW00 2 External SRAM Wait State Select Bit 00
|
||
; EMCUCR.SRW11 1 External SRAM Wait State Select Bit 11
|
||
; EMCUCR.ISC2 0 Interrupt Sense Control 2
|
||
; SPMCR 0x0057 Store Program Memory Control Register
|
||
; SPMCR.BLBSET 3 Boot Lock Bit Set
|
||
; SPMCR.PGWRT 2 Page Write
|
||
; SPMCR.PGERS 1 Page Erase
|
||
; SPMCR.SPMEN 0 Store Program Memory Enable
|
||
; TIFR 0x0058 Timer/Counter Interrupt Flag Register
|
||
; TIFR.TOV1 7 Timer/Counter1 Overflow Flag
|
||
; TIFR.OCF1A 6 Output Compare Flag 1A
|
||
; TIFR.OCIFB 5 Output Compare Flag 1B
|
||
; TIFR.TOV2 4 Timer/Counter2 Overflow Flag
|
||
; TIFR.ICF1 3 Input Capture Flag 1
|
||
; TIFR.OCF2 2 Output Compare Flag 2
|
||
; TIFR.TOV0 1 Timer/Counter0 Overflow Flag
|
||
; TIFR.OCF0 0 Output Compare Flag 0
|
||
; TIMSK 0x0059 Timer/Counter Interrupt Mask Register
|
||
; TIMSK.TOIE1 7 Timer/Counter1 Overflow Interrupt Enable
|
||
; TIMSK.OCIE1A 6 Timer/Counter1 Output CompareA Match Interrupt Enable
|
||
; TIMSK.OCIE1B 5 Timer/Counter1 Output CompareB Match Interrupt Enable
|
||
; TIMSK.TOIE2 4 Timer/Counter2 Overflow Interrupt Enable
|
||
; TIMSK.TICIE1 3 Timer/Counter1 Input Capture Interrupt Enable
|
||
; TIMSK.OCIE2 2 Timer/Counter2 Output Compare Match Interrupt Enable
|
||
; TIMSK.TOIE0 1 Timer/Counter0 Overflow Interrupt Enable
|
||
; TIMSK.OCIE0 0 Timer/Counter0 Output Compare Match Interrupt Enable
|
||
; GIFR 0x005A General Interrupt Flag
|
||
; GIFR.INTF1 7 External Interrupt Flag1
|
||
; GIFR.INTF0 6 External Interrupt Flag0
|
||
; GIFR.INTF2 5 External Interrupt Flag2
|
||
; GIMSK 0x005B General Interrupt Mask Register
|
||
; GIMSK.INT1 7 External Interrupt Request 1 Enable
|
||
; GIMSK.INT0 6 External Interrupt Request 0 Enable
|
||
; GIMSK.INT2 5 External Interrupt Request 2 Enable
|
||
; RESERVED003C 0x005C RESERVED
|
||
; SPL 0x005D Stack Pointer Low
|
||
; SPL.SP7 7
|
||
; SPL.SP6 6
|
||
; SPL.SP5 5
|
||
; SPL.SP4 4
|
||
; SPL.SP3 3
|
||
; SPL.SP2 2
|
||
; SPL.SP1 1
|
||
; SPL.SP0 0
|
||
; SPH 0x005E Stack Pointer High
|
||
; SPH.SP15 15
|
||
; SPH.SP14 14
|
||
; SPH.SP13 13
|
||
; SPH.SP12 12
|
||
; SPH.SP11 11
|
||
; SPH.SP10 10
|
||
; SPH.SP9 9
|
||
; SPH.SP8 8
|
||
; SREG 0x005F Status Register
|
||
; SREG.I 7 Global Interrupt Enable
|
||
; SREG.T 6 Bit Copy Storage
|
||
; SREG.H 5 Half Carry Flag
|
||
; SREG.S 4 Sign Bit
|
||
; SREG.V 3 Two's Complement Overflow Flag
|
||
; SREG.N 2 Negative Flag
|
||
; SREG.Z 1 Zero Flag
|
||
; SREG.C 0 CarryFlag
|
||
|
||
|
||
.ATmega162_L_V
|
||
SUBARCH=5
|
||
; doc2513.pdf
|
||
;
|
||
|
||
RAM=1024
|
||
ROM=16384
|
||
EEPROM=512
|
||
|
||
; MEMORY MAP
|
||
; Memory configuration A
|
||
area DATA FSR1 0x0000:0x0060
|
||
area DATA FSR2 0x0060:0x008C Ext I/O Reg.
|
||
area BSS RESERVED 0x008C:0x0100
|
||
area DATA I_SRAM 0x0100:0x0500 Internal SRAM
|
||
area DATA E_SRAM 0x0500:0x10000 External SRAM
|
||
; Memory configuration B
|
||
; area DATA FSR 0x0000:0x0060
|
||
; area DATA I_SRAM 0x0060:0x0460 Internal SRAM
|
||
; area DATA E_SRAM 0x0460:0x10000 External SRAM
|
||
|
||
|
||
; Interrupt and reset vector assignments
|
||
; if M161C is unprogrammed
|
||
entry __RESET 0x0000 External Pin, Power-on Reset, Brown-out Reset, Watchdog Reset, and JTAG AVR Reset
|
||
entry INT0_ 0x0002 External Interrupt Request 0
|
||
entry INT1_ 0x0004 External Interrupt Request 1
|
||
entry INT2_ 0x0006 External Interrupt Request 2
|
||
entry PCINT0_ 0x0008 Pin Change Interrupt Request 0
|
||
entry PCINT1_ 0x000A Pin Change Interrupt Request 1
|
||
entry TIMER3_CAPT 0x000C Timer/Counter3 Capture Event
|
||
entry TIMER3_COMPA 0x000E Timer/Counter3 Compare Match A
|
||
entry TIMER3_COMPB 0x0010 Timer/Counter3 Compare Match B
|
||
entry TIMER3_OVF 0x0012 Timer/Counter3 Overflow
|
||
entry TIMER2_COMP 0x0014 Timer/Counter2 Compare Match
|
||
entry TIMER2_OVF 0x0016 Timer/Counter2 Overflow
|
||
entry TIMER1_CAPT 0x0018 Timer/Counter1 Capture Event
|
||
entry TIMER1_COMPA 0x001A Timer/Counter1 Compare Match A
|
||
entry TIMER1_COMPB 0x001C Timer/Counter1 Compare Match B
|
||
entry TIMER1_OVF 0x001E Timer/Counter1 Overflow
|
||
entry TIMER0_COMP 0x0020 Timer/Counter0 Compare Match
|
||
entry TIMER0_OVF 0x0022 Timer/Counter0 Overflow
|
||
entry SPI_STC 0x0024 Serial Transfer Complete
|
||
entry USART0_RXC 0x0026 USART0, Rx Complete
|
||
entry USART1_RXC 0x0028 USART1, Rx Complete
|
||
entry USART0_UDRE 0x002A USART0 Data Register Empty
|
||
entry USART1_UDRE 0x002C USART1 Data Register Empty
|
||
entry USART0_TXC 0x002E USART0, Tx Complete
|
||
entry USART1_TXC 0x0030 USART1, Tx Complete
|
||
entry EE_RDY 0x0032 EEPROM Ready
|
||
entry ANA_COMP 0x0034 Analog Comparator
|
||
entry SPM_RDY 0x0036 Store Program Memory Ready
|
||
|
||
; if M161C is programmed
|
||
; entry __RESET 0x0000 External Pin, Power-on Reset, Brown-out Reset, Watchdog Reset, and JTAG AVR Reset
|
||
; entry INT0_ 0x0002 External Interrupt Request 0
|
||
; entry INT1_ 0x0004 External Interrupt Request 1
|
||
; entry INT2_ 0x0006 External Interrupt Request 2
|
||
; entry TIMER2_COMP 0x0008 Timer/Counter2 Compare Match
|
||
; entry TIMER2_OVF 0x000A Timer/Counter2 Overflow
|
||
; entry TIMER1_CAPT 0x000C Timer/Counter1 Capture Event
|
||
; entry TIMER1_COMPA 0x000E Timer/Counter1 Compare Match A
|
||
; entry TIMER1_COMPB 0x0010 Timer/Counter1 Compare Match B
|
||
; entry TIMER1_OVF 0x0012 Timer/Counter1 Overflow
|
||
; entry TIMER0_COMP 0x0014 Timer/Counter0 Compare Match
|
||
; entry TIMER0_OVF 0x0016 Timer/Counter0 Overflow
|
||
; entry SPI_STC 0x0018 Serial Transfer Complete
|
||
; entry USART0_RXC 0x001A USART0, Rx Complete
|
||
; entry USART1_RXC 0x001C USART1, Rx Complete
|
||
; entry USART0_UDRE 0x001E USART0 Data Register Empty
|
||
; entry USART1_UDRE 0x0020 USART1 Data Register Empty
|
||
; entry USART0_TXC 0x0022 USART0, Tx Complete
|
||
; entry USART1_TXC 0x0024 USART1, Tx Complete
|
||
; entry EE_RDY 0x0026 EEPROM Ready
|
||
; entry ANA_COMP 0x0028 Analog Comparator
|
||
; entry SPM_RDY 0x002A Store Program Memory Ready
|
||
|
||
|
||
; INPUT/OUTPUT PORTS
|
||
UBRR1L 0x0000 USART1 Baud Rate Register Low Byte
|
||
UCSR1B 0x0001 USART Control and Status Register B
|
||
UCSR1B.RXCIE 7 RX Complete Interrupt Enable
|
||
UCSR1B.TXCIE 6 TX Complete Interrupt Enable
|
||
UCSR1B.UDRIE 5 USART Data Register Empty Interrupt Enable
|
||
UCSR1B.RXEN 4 Receiver Enable
|
||
UCSR1B.TXEN 3 Transmitter Enable
|
||
UCSR1B.UCSZ2 2 Character Size
|
||
UCSR1B.RXB8 1 Receive Data Bit 8
|
||
UCSR1B.TXB8 0 Transmit Data Bit8
|
||
UCSR1A 0x0002 USART Control and Status Register A
|
||
UCSR1A.RXC 7 USART Receive Complete
|
||
UCSR1A.TXC 6 USART Transmit Complete
|
||
UCSR1A.UDRE 5 USART Data Register Empty
|
||
UCSR1A.FE 4 Frame Error
|
||
UCSR1A.DOR 3 Data OverRun
|
||
UCSR1A.PE 2 Parity Error
|
||
UCSR1A.U2X 1 Double the USART Transmission Speed
|
||
UCSR1A.MPCM 0 Multi-processor Communication Mode
|
||
UDR1 0x0003 USART I/O Data Register
|
||
OCDR 0x0004 On-chip Debug Register
|
||
; OSCCAL 0x0004 Oscillator Calibration Register
|
||
; OSCCAL.CAL7 7 Oscillator Calibration Value 7
|
||
; OSCCAL.CAL6 6 Oscillator Calibration Value 6
|
||
; OSCCAL.CAL5 5 Oscillator Calibration Value 5
|
||
; OSCCAL.CAL4 4 Oscillator Calibration Value 4
|
||
; OSCCAL.CAL3 3 Oscillator Calibration Value 3
|
||
; OSCCAL.CAL2 2 Oscillator Calibration Value 2
|
||
; OSCCAL.CAL1 1 Oscillator Calibration Value 1
|
||
; OSCCAL.CAL0 0 Oscillator Calibration Value 0
|
||
PINE 0x0005 Port E Input Pins Address
|
||
PINE.PINE2 2
|
||
PINE.PINE1 1
|
||
PINE.PINE0 0
|
||
DDRE 0x0006 Port E Data Direction Register
|
||
DDRE.DDE2 2 Port E Data Direction Register bit 2
|
||
DDRE.DDE1 1 Port E Data Direction Register bit 1
|
||
DDRE.DDE0 0 Port E Data Direction Register bit 0
|
||
PORTE 0x0007 Port E Data Register
|
||
PORTE.PORTE2 2 Port E Data Register bit 2
|
||
PORTE.PORTE1 1 Port E Data Register bit 1
|
||
PORTE.PORTE0 0 Port E Data Register bit 0
|
||
ACSR 0x0008 Analog Comparator Control and Status Register
|
||
ACSR.ACD 7 Analog Comparator Disable
|
||
ACSR.ACBG 6 Analog Comparator Bandgap Select
|
||
ACSR.ACO 5 Analog Comparator Output
|
||
ACSR.ACI 4 Analog Comparator Interrupt Flag
|
||
ACSR.ACIE 3 Analog Comparator Interrupt Enable
|
||
ACSR.ACIC 2 Analog Comparator Input Capture Enable
|
||
ACSR.ACIS1 1 Analog Comparator Interrupt Mode Select 1
|
||
ACSR.ACIS0 0 Analog Comparator Interrupt Mode Select 0
|
||
UBRR0L 0x0009 USART0 Baud Rate Register Low Byte
|
||
UCSR0B 0x000A USART Control and Status Register B
|
||
UCSR0B.RXCIE 7 RX Complete Interrupt Enable
|
||
UCSR0B.TXCIE 6 TX Complete Interrupt Enable
|
||
UCSR0B.UDRIE 5 USART Data Register Empty Interrupt Enable
|
||
UCSR0B.RXEN 4 Receiver Enable
|
||
UCSR0B.TXEN 3 Transmitter Enable
|
||
UCSR0B.UCSZ2 2 Character Size
|
||
UCSR0B.RXB8 1 Receive Data Bit 8
|
||
UCSR0B.TXB8 0 Transmit Data Bit8
|
||
UCSR0A 0x000B USART Control and Status Register A
|
||
UCSR0A.RXC 7 USART Receive Complete
|
||
UCSR0A.TXC 6 USART Transmit Complete
|
||
UCSR0A.UDRE 5 USART Data Register Empty
|
||
UCSR0A.FE 4 Frame Error
|
||
UCSR0A.DOR 3 Data OverRun
|
||
UCSR0A.PE 2 Parity Error
|
||
UCSR0A.U2X 1 Double the USART Transmission Speed
|
||
UCSR0A.MPCM 0 Multi-processor Communication Mode
|
||
UDR0 0x000C USART I/O Data Register
|
||
SPCR 0x000D SPI Control Register-
|
||
SPCR.SPIE 7 SPI Interrupt Enable
|
||
SPCR.SPE 6 SPI Enable
|
||
SPCR.DORD 5 Data Order
|
||
SPCR.MSTR 4 Master/Slave Select
|
||
SPCR.CPOL 3 Clock Polarity
|
||
SPCR.CPHA 2 Clock Phase
|
||
SPCR.SPR1 1 SPI Clock Rate Select 1
|
||
SPCR.SPR0 0 SPI Clock Rate Select 0
|
||
SPSR 0x000E SPI Status Register
|
||
SPSR.SPIF 7 SPI Interrupt Flag
|
||
SPSR.WCOL 6 Write COLlision Flag
|
||
SPSR.SPI2X 0 Double SPI Speed Bit
|
||
SPDR 0x000F SPI Data Register
|
||
PIND 0x0010 Port D Input Pins Address
|
||
PIND.PIND7 7
|
||
PIND.PIND6 6
|
||
PIND.PIND5 5
|
||
PIND.PIND4 4
|
||
PIND.PIND3 3
|
||
PIND.PIND2 2
|
||
PIND.PIND1 1
|
||
PIND.PIND0 0
|
||
DDRD 0x0011 Port D Data Direction Register
|
||
DDRD.DDD7 7 Port D Data Direction Register bit 7
|
||
DDRD.DDD6 6 Port D Data Direction Register bit 6
|
||
DDRD.DDD5 5 Port D Data Direction Register bit 5
|
||
DDRD.DDD4 4 Port D Data Direction Register bit 4
|
||
DDRD.DDD3 3 Port D Data Direction Register bit 3
|
||
DDRD.DDD2 2 Port D Data Direction Register bit 2
|
||
DDRD.DDD1 1 Port D Data Direction Register bit 1
|
||
DDRD.DDD0 0 Port D Data Direction Register bit 0
|
||
PORTD 0x0012 Port D Data Register
|
||
PORTD.PORTD7 7 Port D Data Register bit 7
|
||
PORTD.PORTD6 6 Port D Data Register bit 6
|
||
PORTD.PORTD5 5 Port D Data Register bit 5
|
||
PORTD.PORTD4 4 Port D Data Register bit 4
|
||
PORTD.PORTD3 3 Port D Data Register bit 3
|
||
PORTD.PORTD2 2 Port D Data Register bit 2
|
||
PORTD.PORTD1 1 Port D Data Register bit 1
|
||
PORTD.PORTD0 0 Port D Data Register bit 0
|
||
PINC 0x0013 Port C Input Pins Address
|
||
PINC.PINC7 7
|
||
PINC.PINC6 6
|
||
PINC.PINC5 5
|
||
PINC.PINC4 4
|
||
PINC.PINC3 3
|
||
PINC.PINC2 2
|
||
PINC.PINC1 1
|
||
PINC.PINC0 0
|
||
DDRC 0x0014 Port C Data Direction Register
|
||
DDRC.DDC7 7 Port C Data Direction Register bit 7
|
||
DDRC.DDC6 6 Port C Data Direction Register bit 6
|
||
DDRC.DDC5 5 Port C Data Direction Register bit 5
|
||
DDRC.DDC4 4 Port C Data Direction Register bit 4
|
||
DDRC.DDC3 3 Port C Data Direction Register bit 3
|
||
DDRC.DDC2 2 Port C Data Direction Register bit 2
|
||
DDRC.DDC1 1 Port C Data Direction Register bit 1
|
||
DDRC.DDC0 0 Port C Data Direction Register bit 0
|
||
PORTC 0x0015 Port C Data Register
|
||
PORTC.PORTC7 7 Port C Data Register bit 7
|
||
PORTC.PORTC6 6 Port C Data Register bit 6
|
||
PORTC.PORTC5 5 Port C Data Register bit 5
|
||
PORTC.PORTC4 4 Port C Data Register bit 4
|
||
PORTC.PORTC3 3 Port C Data Register bit 3
|
||
PORTC.PORTC2 2 Port C Data Register bit 2
|
||
PORTC.PORTC1 1 Port C Data Register bit 1
|
||
PORTC.PORTC0 0 Port C Data Register bit 0
|
||
PINB 0x0016 Port B Input Pins Address
|
||
PINB.PINB7 7
|
||
PINB.PINB6 6
|
||
PINB.PINB5 5
|
||
PINB.PINB4 4
|
||
PINB.PINB3 3
|
||
PINB.PINB2 2
|
||
PINB.PINB1 1
|
||
PINB.PINB0 0
|
||
DDRB 0x0017 Port B Data Direction Register
|
||
DDRB.DDB7 7 Port B Data Direction Register bit 7
|
||
DDRB.DDB6 6 Port B Data Direction Register bit 6
|
||
DDRB.DDB5 5 Port B Data Direction Register bit 5
|
||
DDRB.DDB4 4 Port B Data Direction Register bit 4
|
||
DDRB.DDB3 3 Port B Data Direction Register bit 3
|
||
DDRB.DDB2 2 Port B Data Direction Register bit 2
|
||
DDRB.DDB1 1 Port B Data Direction Register bit 1
|
||
DDRB.DDB0 0 Port B Data Direction Register bit 0
|
||
PORTB 0x0018 Port B Data Register
|
||
PORTB.PORTB7 7 Port B Data Register bit 7
|
||
PORTB.PORTB6 6 Port B Data Register bit 6
|
||
PORTB.PORTB5 5 Port B Data Register bit 5
|
||
PORTB.PORTB4 4 Port B Data Register bit 4
|
||
PORTB.PORTB3 3 Port B Data Register bit 3
|
||
PORTB.PORTB2 2 Port B Data Register bit 2
|
||
PORTB.PORTB1 1 Port B Data Register bit 1
|
||
PORTB.PORTB0 0 Port B Data Register bit 0
|
||
PINA 0x0019 Port A Input Pins Address
|
||
PINA.PINA7 7
|
||
PINA.PINA6 6
|
||
PINA.PINA5 5
|
||
PINA.PINA4 4
|
||
PINA.PINA3 3
|
||
PINA.PINA2 2
|
||
PINA.PINA1 1
|
||
PINA.PINA0 0
|
||
DDRA 0x001A Port A Data Direction Register
|
||
DDRA.DDA7 7 Port A Data Direction Register bit 7
|
||
DDRA.DDA6 6 Port A Data Direction Register bit 6
|
||
DDRA.DDA5 5 Port A Data Direction Register bit 5
|
||
DDRA.DDA4 4 Port A Data Direction Register bit 4
|
||
DDRA.DDA3 3 Port A Data Direction Register bit 3
|
||
DDRA.DDA2 2 Port A Data Direction Register bit 2
|
||
DDRA.DDA1 1 Port A Data Direction Register bit 1
|
||
DDRA.DDA0 0 Port A Data Direction Register bit 0
|
||
PORTA 0x001B Port A Data Register
|
||
PORTA.PORTA7 7 Port A Data Register bit 7
|
||
PORTA.PORTA6 6 Port A Data Register bit 6
|
||
PORTA.PORTA5 5 Port A Data Register bit 5
|
||
PORTA.PORTA4 4 Port A Data Register bit 4
|
||
PORTA.PORTA3 3 Port A Data Register bit 3
|
||
PORTA.PORTA2 2 Port A Data Register bit 2
|
||
PORTA.PORTA1 1 Port A Data Register bit 1
|
||
PORTA.PORTA0 0 Port A Data Register bit 0
|
||
EECR 0x001C The EEPROM Control Register
|
||
EECR.EERIE 3 EEPROM Ready Interrupt Enable
|
||
EECR.EEMWE 2 EEPROM Master Write Enable
|
||
EECR.EEWE 1 EEPROM Write Enable
|
||
EECR.EERE 0 EEPROM Read Enable
|
||
EEDR 0x001D EEPROM Data Register
|
||
EEARL 0x001E EEPROM Address Register Low Byte
|
||
EEARH 0x001F The EEPROM Address Register High
|
||
EEARH.EEAR8 8 EEPROM Address 8
|
||
UCSR0C 0x0020 USART Control and Status Register C (page 180)
|
||
UCSR0C.URSEL 7 Register Select
|
||
UCSR0C.UMSEL 6 USART Mode Select
|
||
UCSR0C.UPM1 5 Parity Mode 1
|
||
UCSR0C.UPM0 4 Parity Mode 0
|
||
UCSR0C.USBS 3 Stop Bit Select
|
||
UCSR0C.UCSZ1 2 Character Size 1
|
||
UCSR0C.UCSZ0 1 Character Size 0
|
||
UCSR0C.UCPOL 0 Clock Polarity
|
||
; UBRR0H 0x0020 USART Baud Rate Register High
|
||
; UBRR0H.URSEL 15 Register Select
|
||
; UBRR0H.UBRR11 11 USART Baud Rate Register bit 11
|
||
; UBRR0H.UBRR10 10 USART Baud Rate Register bit 10
|
||
; UBRR0H.UBRR9 9 USART Baud Rate Register bit 9
|
||
; UBRR0H.UBRR8 8 USART Baud Rate Register bit 8
|
||
WDTCR 0x0021 Watchdog Timer Control Register
|
||
WDTCR.WDCE 4 Watchdog Change Enable
|
||
WDTCR.WDE 3 Watchdog Enable
|
||
WDTCR.WDP2 2 Watchdog Timer Prescaler 2
|
||
WDTCR.WDP1 1 Watchdog Timer Prescaler 1
|
||
WDTCR.WDP0 0 Watchdog Timer Prescaler 0
|
||
OCR2 0x0022 Output Compare Register
|
||
TCNT2 0x0023 Timer/Counter2
|
||
ICR1L 0x0024 Input Capture Register Low Byte
|
||
ICR1H 0x0025 Input Capture Register High Byte
|
||
ASSR 0x0026 Asynchronous Status Register
|
||
ASSR.AS2 3 Asynchronous Timer/Counter2
|
||
ASSR.TCN2UB 2 Timer/Counter2 Update Busy
|
||
ASSR.OCR2UB 1 Output Compare Register2 Update Busy
|
||
ASSR.TCR2UB 0 Timer/Counter Control Register2 Update Busy
|
||
TCCR2 0x0027 Timer/Counter Control Register
|
||
TCCR2.FOC2 7 Force Output Compare
|
||
TCCR2.WGM20 6 Waveform Generation Mode 0
|
||
TCCR2.COM21 5 Compare Match Output Mode 1
|
||
TCCR2.COM20 4 Compare Match Output Mode 0
|
||
TCCR2.WGM21 3 Waveform Generation Mode 1
|
||
TCCR2.CS22 2 Clock Select 2
|
||
TCCR2.CS21 1 Clock Select 1
|
||
TCCR2.CS20 0 Clock Select 0
|
||
OCR1BL 0x0028 Output Compare Register B Low Byte
|
||
OCR1BH 0x0029 Output Compare Register B High Byte
|
||
OCR1AL 0x002A Output Compare Register A Low Byte
|
||
OCR1AH 0x002B Output Compare Register A High Byte
|
||
TCNT1L 0x002C Counter Register Low Byte
|
||
TCNT1H 0x002D Counter Register High Byte
|
||
TCCR1B 0x002E Timer/Counter1 Control Register B
|
||
TCCR1B.ICNC1 7 Input Capture Noise Canceler
|
||
TCCR1B.ICES1 6 Input CaptureEdgeSelect
|
||
TCCR1B.WGM13 4 Waveform Generation Mode 3
|
||
TCCR1B.WGM12 3 Waveform Generation Mode 2
|
||
TCCR1B.CS12 2 Clock Select 2
|
||
TCCR1B.CS11 1 Clock Select 1
|
||
TCCR1B.CS10 0 Clock Select 0
|
||
TCCR1A 0x002F Timer/Counter1 Control Register A
|
||
TCCR1A.COM1A1 7 Compare Output Mode for channel A 1
|
||
TCCR1A.COM1A0 6 Compare Output Mode for channel A 0
|
||
TCCR1A.COM1B1 5 Compare Output Mode for channel B 1
|
||
TCCR1A.COM1B0 4 Compare Output Mode for channel B 0
|
||
TCCR1A.FOC1A 3 Force Output Compare for channel A
|
||
TCCR1A.FOC1B 2 Force Output Compare for channel B
|
||
TCCR1A.WGM11 1 Waveform Generation Mode 1
|
||
TCCR1A.WGM10 0 Waveform Generation Mode 0
|
||
SFIOR 0x0030 Special Function IO Register
|
||
SFIOR.TSM 7 Timer/Counter Synchronization Mode
|
||
SFIOR.XMBK 6 External Memory Bus Keeper Enable
|
||
SFIOR.XMM2 5 External Memory High Mask 2
|
||
SFIOR.XMM1 4 External Memory High Mask 1
|
||
SFIOR.XMM0 3 External Memory High Mask 0
|
||
SFIOR.PUD 2 Pull-up Disable
|
||
SFIOR.PSR2 1 Prescaler Reset Timer/Counter2
|
||
SFIOR.PSR310 0 Prescaler Reset Timer/Counter3, Timer/Counter1, and Timer/Counter0
|
||
OCR0 0x0031 Timer/Counter0 Output Compare Register
|
||
TCNT0 0x0032 Timer/Counter0
|
||
TCCR0 0x0033 Timer/Counter Control Register
|
||
TCCR0.FOC0 7 Force Output Compare
|
||
TCCR0.WGM00 6 Waveform Generation Mode 0
|
||
TCCR0.COM01 5 Compare Match Output Mode 1
|
||
TCCR0.COM00 4 Compare Match Output Mode 0
|
||
TCCR0.WGM01 3 Waveform Generation Mode 1
|
||
TCCR0.CS02 2 Clock Select 2
|
||
TCCR0.CS01 1 Clock Select 1
|
||
TCCR0.CS00 0 Clock Select 0
|
||
MCUCSR 0x0034 MCU Control and Status Register
|
||
MCUCSR.JTD 7 JTAG Interface Disable
|
||
MCUCSR.SM2 5 Sleep Mode Select Bit 2
|
||
MCUCSR.JTRF 4 JTAG Reset Flag
|
||
MCUCSR.WDRF 3 Watchdog Reset Flag
|
||
MCUCSR.BORF 2 Brown-out Reset Flag
|
||
MCUCSR.EXTRF 1 External Reset Flag
|
||
MCUCSR.PORF 0 Power-on Reset Flag
|
||
MCUCR 0x0035 MCU Control Register
|
||
MCUCR.SRE 7 External SRAM/XMEM Enable
|
||
MCUCR.SRW10 6 Wait State Select Bit
|
||
MCUCR.SE 5 Sleep Enable
|
||
MCUCR.SM1 4 Sleep Mode Select Bit 1
|
||
MCUCR.ISC11 3 Interrupt Sense Control 1 Bit 1
|
||
MCUCR.ISC10 2 Interrupt Sense Control 1 Bit 0
|
||
MCUCR.ISC01 1 Interrupt Sense Control 0 Bit 1
|
||
MCUCR.ISC00 0 Interrupt Sense Control 0 Bit 0
|
||
EMCUCR 0x0036 Extended MCU Control Register
|
||
EMCUCR.SM0 7 Sleep Mode Select Bit 0
|
||
EMCUCR.SRL2 6 Wait State Sector Limit 2
|
||
EMCUCR.SRL1 5 Wait State Sector Limit 1
|
||
EMCUCR.SRL0 4 Wait State Sector Limit 0
|
||
EMCUCR.SRW01 3 Wait-state Select Bits for Lower Sector 1
|
||
EMCUCR.SRW00 2 Wait-state Select Bits for Lower Sector 0
|
||
EMCUCR.SRW11 1 Wait-state Select Bits for Upper Sector
|
||
EMCUCR.ISC2 0 Interrupt Sense Control 2
|
||
SPMCR 0x0037 Store Program Memory Control Register
|
||
SPMCR.SPMIE 7 SPM Interrupt Enable
|
||
SPMCR.RWWSB 6 Read-While-Write Section Busy
|
||
SPMCR.RWWSRE 4 Read-While-Write Section Read Enable
|
||
SPMCR.BLBSET 3 Boot Lock Bit Set
|
||
SPMCR.PGWRT 2 Page Write
|
||
SPMCR.PGERS 1 Page Erase
|
||
SPMCR.SPMEN 0 Store Program Memory Enable
|
||
TIFR 0x0038 Timer/Counter Interrupt Flag Register
|
||
TIFR.TOV1 7 Timer/Counter1, Overflow Flag
|
||
TIFR.OCF1A 6 Timer/Counter1, Output Compare A Match Flag
|
||
TIFR.OCF1B 5 Timer/Counter1, Output Compare B Match Flag
|
||
TIFR.OCF2 4 Output Compare Flag 2
|
||
TIFR.ICF1 3 Timer/Counter1, Input Capture Flag
|
||
TIFR.TOV2 2 Timer/Counter2 Overflow Flag
|
||
TIFR.TOV0 1 Timer/Counter0 Overflow Flag
|
||
TIFR.OCF0 0 Output Compare Flag 0
|
||
TIMSK 0x0039 Timer/Counter Interrupt Mask Register
|
||
TIMSK.TOIE1 7 Timer/Counter1, Overflow Interrupt Enable
|
||
TIMSK.OCIE1A 6 Timer/Counter1, Output Compare A Match Interrupt Enable
|
||
TIMSK.OCIE1B 5 Timer/Counter1, Output Compare B Match Interrupt Enable
|
||
TIMSK.OCIE2 4 Timer/Counter2 Output Compare Match Interrupt Enable
|
||
TIMSK.TICIE1 3 Timer/Counter1, Input Capture Interrupt Enable
|
||
TIMSK.TOIE2 2 Timer/Counter2 Overflow Interrupt Enable
|
||
TIMSK.TOIE0 1 Timer/Counter0 Overflow Interrupt Enable
|
||
TIMSK.OCIE0 0 Timer/Counter0 Overflow Flag
|
||
GIFR 0x003A General Interrupt Flag Register
|
||
GIFR.INTF1 7 External Interrupt Flag 1
|
||
GIFR.INTF0 6 External Interrupt Flag 0
|
||
GIFR.INTF2 5 External Interrupt Flag 2
|
||
GIFR.PCIF1 4 Pin Change Interrupt Flag 1
|
||
GIFR.PCIF0 3 Pin Change Interrupt Flag 0
|
||
GICR 0x003B General Interrupt Control Register
|
||
GICR.INT1 7 External Interrupt Request 1 Enable
|
||
GICR.INT0 6 External Interrupt Request 0 Enable
|
||
GICR.INT2 5 External Interrupt Request 2 Enable
|
||
GICR.PCIE1 4 Pin Change Interrupt Enable 1
|
||
GICR.PCIE0 3 Pin Change Interrupt Enable 0
|
||
GICR.IVSEL 1 Interrupt Vector Select
|
||
GICR.IVCE 0 Interrupt Vector Change Enable
|
||
UCSR1C 0x003C USART Control and Status Register C (page 180)
|
||
UCSR1C.URSEL 7 Register Select
|
||
UCSR1C.UMSEL 6 USART Mode Select
|
||
UCSR1C.UPM1 5 Parity Mode 1
|
||
UCSR1C.UPM0 4 Parity Mode 0
|
||
UCSR1C.USBS 3 Stop Bit Select
|
||
UCSR1C.UCSZ1 2 Character Size 1
|
||
UCSR1C.UCSZ0 1 Character Size 0
|
||
UCSR1C.UCPOL 0 Clock Polarity
|
||
; UBRR1H 0x003C USART Baud Rate Register High
|
||
; UBRR1H.URSEL 15 Register Select
|
||
; UBRR1H.UBRR11 11 USART Baud Rate Register 11
|
||
; UBRR1H.UBRR10 10 USART Baud Rate Register 10
|
||
; UBRR1H.UBRR9 9 USART Baud Rate Register 9
|
||
; UBRR1H.UBRR8 8 USART Baud Rate Register 8
|
||
SPL 0x003D Stack Pointer Low
|
||
SPL.SP7 7
|
||
SPL.SP6 6
|
||
SPL.SP5 5
|
||
SPL.SP4 4
|
||
SPL.SP3 3
|
||
SPL.SP2 2
|
||
SPL.SP1 1
|
||
SPL.SP0 0
|
||
SPH 0x003E Stack Pointer High
|
||
SPH.SP15 15
|
||
SPH.SP14 14
|
||
SPH.SP13 13
|
||
SPH.SP12 12
|
||
SPH.SP11 11
|
||
SPH.SP10 10
|
||
SPH.SP9 9
|
||
SPH.SP8 8
|
||
SREG 0x003F Status Register
|
||
SREG.I 7 Global Interrupt Enable
|
||
SREG.T 6 Bit Copy Storage
|
||
SREG.H 5 Half Carry Flag
|
||
SREG.S 4 Sign Bit
|
||
SREG.V 3 Two's Complement Overflow Flag
|
||
SREG.N 2 Negative Flag
|
||
SREG.Z 1 Zero Flag
|
||
SREG.C 0 CarryFlag
|
||
|
||
; UBRR1L 0x0020 USART1 Baud Rate Register Low Byte
|
||
; UCSR1B 0x0021 USART Control and Status Register B
|
||
; UCSR1B.RXCIE 7 RX Complete Interrupt Enable
|
||
; UCSR1B.TXCIE 6 TX Complete Interrupt Enable
|
||
; UCSR1B.UDRIE 5 USART Data Register Empty Interrupt Enable
|
||
; UCSR1B.RXEN 4 Receiver Enable
|
||
; UCSR1B.TXEN 3 Transmitter Enable
|
||
; UCSR1B.UCSZ2 2 Character Size
|
||
; UCSR1B.RXB8 1 Receive Data Bit 8
|
||
; UCSR1B.TXB8 0 Transmit Data Bit8
|
||
; UCSR1A 0x0022 USART Control and Status Register A
|
||
; UCSR1A.RXC 7 USART Receive Complete
|
||
; UCSR1A.TXC 6 USART Transmit Complete
|
||
; UCSR1A.UDRE 5 USART Data Register Empty
|
||
; UCSR1A.FE 4 Frame Error
|
||
; UCSR1A.DOR 3 Data OverRun
|
||
; UCSR1A.PE 2 Parity Error
|
||
; UCSR1A.U2X 1 Double the USART Transmission Speed
|
||
; UCSR1A.MPCM 0 Multi-processor Communication Mode
|
||
; UDR1 0x0023 USART I/O Data Register
|
||
; OCDR 0x0024 On-chip Debug Register
|
||
; ; OSCCAL 0x0024 Oscillator Calibration Register
|
||
; ; OSCCAL.CAL7 7 Oscillator Calibration Value 7
|
||
; ; OSCCAL.CAL6 6 Oscillator Calibration Value 6
|
||
; ; OSCCAL.CAL5 5 Oscillator Calibration Value 5
|
||
; ; OSCCAL.CAL4 4 Oscillator Calibration Value 4
|
||
; ; OSCCAL.CAL3 3 Oscillator Calibration Value 3
|
||
; ; OSCCAL.CAL2 2 Oscillator Calibration Value 2
|
||
; ; OSCCAL.CAL1 1 Oscillator Calibration Value 1
|
||
; ; OSCCAL.CAL0 0 Oscillator Calibration Value 0
|
||
; PINE 0x0025 Port E Input Pins Address
|
||
; PINE.PINE2 2
|
||
; PINE.PINE1 1
|
||
; PINE.PINE0 0
|
||
; DDRE 0x0026 Port E Data Direction Register
|
||
; DDRE.DDE2 2 Port E Data Direction Register bit 2
|
||
; DDRE.DDE1 1 Port E Data Direction Register bit 1
|
||
; DDRE.DDE0 0 Port E Data Direction Register bit 0
|
||
; PORTE 0x0027 Port E Data Register
|
||
; PORTE.PORTE2 2 Port E Data Register bit 2
|
||
; PORTE.PORTE1 1 Port E Data Register bit 1
|
||
; PORTE.PORTE0 0 Port E Data Register bit 0
|
||
; ACSR 0x0028 Analog Comparator Control and Status Register
|
||
; ACSR.ACD 7 Analog Comparator Disable
|
||
; ACSR.ACBG 6 Analog Comparator Bandgap Select
|
||
; ACSR.ACO 5 Analog Comparator Output
|
||
; ACSR.ACI 4 Analog Comparator Interrupt Flag
|
||
; ACSR.ACIE 3 Analog Comparator Interrupt Enable
|
||
; ACSR.ACIC 2 Analog Comparator Input Capture Enable
|
||
; ACSR.ACIS1 1 Analog Comparator Interrupt Mode Select 1
|
||
; ACSR.ACIS0 0 Analog Comparator Interrupt Mode Select 0
|
||
; UBRR0L 0x0029 USART0 Baud Rate Register Low Byte
|
||
; UCSR0B 0x002A USART Control and Status Register B
|
||
; UCSR0B.RXCIE 7 RX Complete Interrupt Enable
|
||
; UCSR0B.TXCIE 6 TX Complete Interrupt Enable
|
||
; UCSR0B.UDRIE 5 USART Data Register Empty Interrupt Enable
|
||
; UCSR0B.RXEN 4 Receiver Enable
|
||
; UCSR0B.TXEN 3 Transmitter Enable
|
||
; UCSR0B.UCSZ2 2 Character Size
|
||
; UCSR0B.RXB8 1 Receive Data Bit 8
|
||
; UCSR0B.TXB8 0 Transmit Data Bit8
|
||
; UCSR0A 0x002B USART Control and Status Register A
|
||
; UCSR0A.RXC 7 USART Receive Complete
|
||
; UCSR0A.TXC 6 USART Transmit Complete
|
||
; UCSR0A.UDRE 5 USART Data Register Empty
|
||
; UCSR0A.FE 4 Frame Error
|
||
; UCSR0A.DOR 3 Data OverRun
|
||
; UCSR0A.PE 2 Parity Error
|
||
; UCSR0A.U2X 1 Double the USART Transmission Speed
|
||
; UCSR0A.MPCM 0 Multi-processor Communication Mode
|
||
; UDR0 0x002C USART I/O Data Register
|
||
; SPCR 0x002D SPI Control Register-
|
||
; SPCR.SPIE 7 SPI Interrupt Enable
|
||
; SPCR.SPE 6 SPI Enable
|
||
; SPCR.DORD 5 Data Order
|
||
; SPCR.MSTR 4 Master/Slave Select
|
||
; SPCR.CPOL 3 Clock Polarity
|
||
; SPCR.CPHA 2 Clock Phase
|
||
; SPCR.SPR1 1 SPI Clock Rate Select 1
|
||
; SPCR.SPR0 0 SPI Clock Rate Select 0
|
||
; SPSR 0x002E SPI Status Register
|
||
; SPSR.SPIF 7 SPI Interrupt Flag
|
||
; SPSR.WCOL 6 Write COLlision Flag
|
||
; SPSR.SPI2X 0 Double SPI Speed Bit
|
||
; SPDR 0x002F SPI Data Register
|
||
; PIND 0x0030 Port D Input Pins Address
|
||
; PIND.PIND7 7
|
||
; PIND.PIND6 6
|
||
; PIND.PIND5 5
|
||
; PIND.PIND4 4
|
||
; PIND.PIND3 3
|
||
; PIND.PIND2 2
|
||
; PIND.PIND1 1
|
||
; PIND.PIND0 0
|
||
; DDRD 0x0031 Port D Data Direction Register
|
||
; DDRD.DDD7 7 Port D Data Direction Register bit 7
|
||
; DDRD.DDD6 6 Port D Data Direction Register bit 6
|
||
; DDRD.DDD5 5 Port D Data Direction Register bit 5
|
||
; DDRD.DDD4 4 Port D Data Direction Register bit 4
|
||
; DDRD.DDD3 3 Port D Data Direction Register bit 3
|
||
; DDRD.DDD2 2 Port D Data Direction Register bit 2
|
||
; DDRD.DDD1 1 Port D Data Direction Register bit 1
|
||
; DDRD.DDD0 0 Port D Data Direction Register bit 0
|
||
; PORTD 0x0032 Port D Data Register
|
||
; PORTD.PORTD7 7 Port D Data Register bit 7
|
||
; PORTD.PORTD6 6 Port D Data Register bit 6
|
||
; PORTD.PORTD5 5 Port D Data Register bit 5
|
||
; PORTD.PORTD4 4 Port D Data Register bit 4
|
||
; PORTD.PORTD3 3 Port D Data Register bit 3
|
||
; PORTD.PORTD2 2 Port D Data Register bit 2
|
||
; PORTD.PORTD1 1 Port D Data Register bit 1
|
||
; PORTD.PORTD0 0 Port D Data Register bit 0
|
||
; PINC 0x0033 Port C Input Pins Address
|
||
; PINC.PINC7 7
|
||
; PINC.PINC6 6
|
||
; PINC.PINC5 5
|
||
; PINC.PINC4 4
|
||
; PINC.PINC3 3
|
||
; PINC.PINC2 2
|
||
; PINC.PINC1 1
|
||
; PINC.PINC0 0
|
||
; DDRC 0x0034 Port C Data Direction Register
|
||
; DDRC.DDC7 7 Port C Data Direction Register bit 7
|
||
; DDRC.DDC6 6 Port C Data Direction Register bit 6
|
||
; DDRC.DDC5 5 Port C Data Direction Register bit 5
|
||
; DDRC.DDC4 4 Port C Data Direction Register bit 4
|
||
; DDRC.DDC3 3 Port C Data Direction Register bit 3
|
||
; DDRC.DDC2 2 Port C Data Direction Register bit 2
|
||
; DDRC.DDC1 1 Port C Data Direction Register bit 1
|
||
; DDRC.DDC0 0 Port C Data Direction Register bit 0
|
||
; PORTC 0x0035 Port C Data Register
|
||
; PORTC.PORTC7 7 Port C Data Register bit 7
|
||
; PORTC.PORTC6 6 Port C Data Register bit 6
|
||
; PORTC.PORTC5 5 Port C Data Register bit 5
|
||
; PORTC.PORTC4 4 Port C Data Register bit 4
|
||
; PORTC.PORTC3 3 Port C Data Register bit 3
|
||
; PORTC.PORTC2 2 Port C Data Register bit 2
|
||
; PORTC.PORTC1 1 Port C Data Register bit 1
|
||
; PORTC.PORTC0 0 Port C Data Register bit 0
|
||
; PINB 0x0036 Port B Input Pins Address
|
||
; PINB.PINB7 7
|
||
; PINB.PINB6 6
|
||
; PINB.PINB5 5
|
||
; PINB.PINB4 4
|
||
; PINB.PINB3 3
|
||
; PINB.PINB2 2
|
||
; PINB.PINB1 1
|
||
; PINB.PINB0 0
|
||
; DDRB 0x0037 Port B Data Direction Register
|
||
; DDRB.DDB7 7 Port B Data Direction Register bit 7
|
||
; DDRB.DDB6 6 Port B Data Direction Register bit 6
|
||
; DDRB.DDB5 5 Port B Data Direction Register bit 5
|
||
; DDRB.DDB4 4 Port B Data Direction Register bit 4
|
||
; DDRB.DDB3 3 Port B Data Direction Register bit 3
|
||
; DDRB.DDB2 2 Port B Data Direction Register bit 2
|
||
; DDRB.DDB1 1 Port B Data Direction Register bit 1
|
||
; DDRB.DDB0 0 Port B Data Direction Register bit 0
|
||
; PORTB 0x0038 Port B Data Register
|
||
; PORTB.PORTB7 7 Port B Data Register bit 7
|
||
; PORTB.PORTB6 6 Port B Data Register bit 6
|
||
; PORTB.PORTB5 5 Port B Data Register bit 5
|
||
; PORTB.PORTB4 4 Port B Data Register bit 4
|
||
; PORTB.PORTB3 3 Port B Data Register bit 3
|
||
; PORTB.PORTB2 2 Port B Data Register bit 2
|
||
; PORTB.PORTB1 1 Port B Data Register bit 1
|
||
; PORTB.PORTB0 0 Port B Data Register bit 0
|
||
; PINA 0x0039 Port A Input Pins Address
|
||
; PINA.PINA7 7
|
||
; PINA.PINA6 6
|
||
; PINA.PINA5 5
|
||
; PINA.PINA4 4
|
||
; PINA.PINA3 3
|
||
; PINA.PINA2 2
|
||
; PINA.PINA1 1
|
||
; PINA.PINA0 0
|
||
; DDRA 0x003A Port A Data Direction Register
|
||
; DDRA.DDA7 7 Port A Data Direction Register bit 7
|
||
; DDRA.DDA6 6 Port A Data Direction Register bit 6
|
||
; DDRA.DDA5 5 Port A Data Direction Register bit 5
|
||
; DDRA.DDA4 4 Port A Data Direction Register bit 4
|
||
; DDRA.DDA3 3 Port A Data Direction Register bit 3
|
||
; DDRA.DDA2 2 Port A Data Direction Register bit 2
|
||
; DDRA.DDA1 1 Port A Data Direction Register bit 1
|
||
; DDRA.DDA0 0 Port A Data Direction Register bit 0
|
||
; PORTA 0x003B Port A Data Register
|
||
; PORTA.PORTA7 7 Port A Data Register bit 7
|
||
; PORTA.PORTA6 6 Port A Data Register bit 6
|
||
; PORTA.PORTA5 5 Port A Data Register bit 5
|
||
; PORTA.PORTA4 4 Port A Data Register bit 4
|
||
; PORTA.PORTA3 3 Port A Data Register bit 3
|
||
; PORTA.PORTA2 2 Port A Data Register bit 2
|
||
; PORTA.PORTA1 1 Port A Data Register bit 1
|
||
; PORTA.PORTA0 0 Port A Data Register bit 0
|
||
; EECR 0x003C The EEPROM Control Register
|
||
; EECR.EERIE 3 EEPROM Ready Interrupt Enable
|
||
; EECR.EEMWE 2 EEPROM Master Write Enable
|
||
; EECR.EEWE 1 EEPROM Write Enable
|
||
; EECR.EERE 0 EEPROM Read Enable
|
||
; EEDR 0x003D EEPROM Data Register
|
||
; EEARL 0x003E EEPROM Address Register Low Byte
|
||
; EEARH 0x003F The EEPROM Address Register High
|
||
; EEARH.EEAR8 8 EEPROM Address 8
|
||
; UCSR0C 0x0040 USART Control and Status Register C (page 180)
|
||
; UCSR0C.URSEL 7 Register Select
|
||
; UCSR0C.UMSEL 6 USART Mode Select
|
||
; UCSR0C.UPM1 5 Parity Mode 1
|
||
; UCSR0C.UPM0 4 Parity Mode 0
|
||
; UCSR0C.USBS 3 Stop Bit Select
|
||
; UCSR0C.UCSZ1 2 Character Size 1
|
||
; UCSR0C.UCSZ0 1 Character Size 0
|
||
; UCSR0C.UCPOL 0 Clock Polarity
|
||
; ; UBRR0H 0x0040 USART Baud Rate Register High
|
||
; ; UBRR0H.URSEL 15 Register Select
|
||
; ; UBRR0H.UBRR11 11 USART Baud Rate Register bit 11
|
||
; ; UBRR0H.UBRR10 10 USART Baud Rate Register bit 10
|
||
; ; UBRR0H.UBRR9 9 USART Baud Rate Register bit 9
|
||
; ; UBRR0H.UBRR8 8 USART Baud Rate Register bit 8
|
||
; WDTCR 0x0041 Watchdog Timer Control Register
|
||
; WDTCR.WDCE 4 Watchdog Change Enable
|
||
; WDTCR.WDE 3 Watchdog Enable
|
||
; WDTCR.WDP2 2 Watchdog Timer Prescaler 2
|
||
; WDTCR.WDP1 1 Watchdog Timer Prescaler 1
|
||
; WDTCR.WDP0 0 Watchdog Timer Prescaler 0
|
||
; OCR2 0x0042 Output Compare Register
|
||
; TCNT2 0x0043 Timer/Counter2
|
||
; ICR1L 0x0044 Input Capture Register Low Byte
|
||
; ICR1H 0x0045 Input Capture Register High Byte
|
||
; ASSR 0x0046 Asynchronous Status Register
|
||
; ASSR.AS2 3 Asynchronous Timer/Counter2
|
||
; ASSR.TCN2UB 2 Timer/Counter2 Update Busy
|
||
; ASSR.OCR2UB 1 Output Compare Register2 Update Busy
|
||
; ASSR.TCR2UB 0 Timer/Counter Control Register2 Update Busy
|
||
; TCCR2 0x0047 Timer/Counter Control Register
|
||
; TCCR2.FOC2 7 Force Output Compare
|
||
; TCCR2.WGM20 6 Waveform Generation Mode 0
|
||
; TCCR2.COM21 5 Compare Match Output Mode 1
|
||
; TCCR2.COM20 4 Compare Match Output Mode 0
|
||
; TCCR2.WGM21 3 Waveform Generation Mode 1
|
||
; TCCR2.CS22 2 Clock Select 2
|
||
; TCCR2.CS21 1 Clock Select 1
|
||
; TCCR2.CS20 0 Clock Select 0
|
||
; OCR1BL 0x0048 Output Compare Register B Low Byte
|
||
; OCR1BH 0x0049 Output Compare Register B High Byte
|
||
; OCR1AL 0x004A Output Compare Register A Low Byte
|
||
; OCR1AH 0x004B Output Compare Register A High Byte
|
||
; TCNT1L 0x004C Counter Register Low Byte
|
||
; TCNT1H 0x004D Counter Register High Byte
|
||
; TCCR1B 0x004E Timer/Counter1 Control Register B
|
||
; TCCR1B.ICNC1 7 Input Capture Noise Canceler
|
||
; TCCR1B.ICES1 6 Input CaptureEdgeSelect
|
||
; TCCR1B.WGM13 4 Waveform Generation Mode 3
|
||
; TCCR1B.WGM12 3 Waveform Generation Mode 2
|
||
; TCCR1B.CS12 2 Clock Select 2
|
||
; TCCR1B.CS11 1 Clock Select 1
|
||
; TCCR1B.CS10 0 Clock Select 0
|
||
; TCCR1A 0x004F Timer/Counter1 Control Register A
|
||
; TCCR1A.COM1A1 7 Compare Output Mode for channel A 1
|
||
; TCCR1A.COM1A0 6 Compare Output Mode for channel A 0
|
||
; TCCR1A.COM1B1 5 Compare Output Mode for channel B 1
|
||
; TCCR1A.COM1B0 4 Compare Output Mode for channel B 0
|
||
; TCCR1A.FOC1A 3 Force Output Compare for channel A
|
||
; TCCR1A.FOC1B 2 Force Output Compare for channel B
|
||
; TCCR1A.WGM11 1 Waveform Generation Mode 1
|
||
; TCCR1A.WGM10 0 Waveform Generation Mode 0
|
||
; SFIOR 0x0050 Special Function IO Register
|
||
; SFIOR.TSM 7 Timer/Counter Synchronization Mode
|
||
; SFIOR.XMBK 6 External Memory Bus Keeper Enable
|
||
; SFIOR.XMM2 5 External Memory High Mask 2
|
||
; SFIOR.XMM1 4 External Memory High Mask 1
|
||
; SFIOR.XMM0 3 External Memory High Mask 0
|
||
; SFIOR.PUD 2 Pull-up Disable
|
||
; SFIOR.PSR2 1 Prescaler Reset Timer/Counter2
|
||
; SFIOR.PSR310 0 Prescaler Reset Timer/Counter3, Timer/Counter1, and Timer/Counter0
|
||
; OCR0 0x0051 Timer/Counter0 Output Compare Register
|
||
; TCNT0 0x0052 Timer/Counter0
|
||
; TCCR0 0x0053 Timer/Counter Control Register
|
||
; TCCR0.FOC0 7 Force Output Compare
|
||
; TCCR0.WGM00 6 Waveform Generation Mode 0
|
||
; TCCR0.COM01 5 Compare Match Output Mode 1
|
||
; TCCR0.COM00 4 Compare Match Output Mode 0
|
||
; TCCR0.WGM01 3 Waveform Generation Mode 1
|
||
; TCCR0.CS02 2 Clock Select 2
|
||
; TCCR0.CS01 1 Clock Select 1
|
||
; TCCR0.CS00 0 Clock Select 0
|
||
; MCUCSR 0x0054 MCU Control and Status Register
|
||
; MCUCSR.JTD 7 JTAG Interface Disable
|
||
; MCUCSR.SM2 5 Sleep Mode Select Bit 2
|
||
; MCUCSR.JTRF 4 JTAG Reset Flag
|
||
; MCUCSR.WDRF 3 Watchdog Reset Flag
|
||
; MCUCSR.BORF 2 Brown-out Reset Flag
|
||
; MCUCSR.EXTRF 1 External Reset Flag
|
||
; MCUCSR.PORF 0 Power-on Reset Flag
|
||
; MCUCR 0x0055 MCU Control Register
|
||
; MCUCR.SRE 7 External SRAM/XMEM Enable
|
||
; MCUCR.SRW10 6 Wait State Select Bit
|
||
; MCUCR.SE 5 Sleep Enable
|
||
; MCUCR.SM1 4 Sleep Mode Select Bit 1
|
||
; MCUCR.ISC11 3 Interrupt Sense Control 1 Bit 1
|
||
; MCUCR.ISC10 2 Interrupt Sense Control 1 Bit 0
|
||
; MCUCR.ISC01 1 Interrupt Sense Control 0 Bit 1
|
||
; MCUCR.ISC00 0 Interrupt Sense Control 0 Bit 0
|
||
; EMCUCR 0x0056 Extended MCU Control Register
|
||
; EMCUCR.SM0 7 Sleep Mode Select Bit 0
|
||
; EMCUCR.SRL2 6 Wait State Sector Limit 2
|
||
; EMCUCR.SRL1 5 Wait State Sector Limit 1
|
||
; EMCUCR.SRL0 4 Wait State Sector Limit 0
|
||
; EMCUCR.SRW01 3 Wait-state Select Bits for Lower Sector 1
|
||
; EMCUCR.SRW00 2 Wait-state Select Bits for Lower Sector 0
|
||
; EMCUCR.SRW11 1 Wait-state Select Bits for Upper Sector
|
||
; EMCUCR.ISC2 0 Interrupt Sense Control 2
|
||
; SPMCR 0x0057 Store Program Memory Control Register
|
||
; SPMCR.SPMIE 7 SPM Interrupt Enable
|
||
; SPMCR.RWWSB 6 Read-While-Write Section Busy
|
||
; SPMCR.RWWSRE 4 Read-While-Write Section Read Enable
|
||
; SPMCR.BLBSET 3 Boot Lock Bit Set
|
||
; SPMCR.PGWRT 2 Page Write
|
||
; SPMCR.PGERS 1 Page Erase
|
||
; SPMCR.SPMEN 0 Store Program Memory Enable
|
||
; TIFR 0x0058 Timer/Counter Interrupt Flag Register
|
||
; TIFR.TOV1 7 Timer/Counter1, Overflow Flag
|
||
; TIFR.OCF1A 6 Timer/Counter1, Output Compare A Match Flag
|
||
; TIFR.OCF1B 5 Timer/Counter1, Output Compare B Match Flag
|
||
; TIFR.OCF2 4 Output Compare Flag 2
|
||
; TIFR.ICF1 3 Timer/Counter1, Input Capture Flag
|
||
; TIFR.TOV2 2 Timer/Counter2 Overflow Flag
|
||
; TIFR.TOV0 1 Timer/Counter0 Overflow Flag
|
||
; TIFR.OCF0 0 Output Compare Flag 0
|
||
; TIMSK 0x0059 Timer/Counter Interrupt Mask Register
|
||
; TIMSK.TOIE1 7 Timer/Counter1, Overflow Interrupt Enable
|
||
; TIMSK.OCIE1A 6 Timer/Counter1, Output Compare A Match Interrupt Enable
|
||
; TIMSK.OCIE1B 5 Timer/Counter1, Output Compare B Match Interrupt Enable
|
||
; TIMSK.OCIE2 4 Timer/Counter2 Output Compare Match Interrupt Enable
|
||
; TIMSK.TICIE1 3 Timer/Counter1, Input Capture Interrupt Enable
|
||
; TIMSK.TOIE2 2 Timer/Counter2 Overflow Interrupt Enable
|
||
; TIMSK.TOIE0 1 Timer/Counter0 Overflow Interrupt Enable
|
||
; TIMSK.OCIE0 0 Timer/Counter0 Overflow Flag
|
||
; GIFR 0x005A General Interrupt Flag Register
|
||
; GIFR.INTF1 7 External Interrupt Flag 1
|
||
; GIFR.INTF0 6 External Interrupt Flag 0
|
||
; GIFR.INTF2 5 External Interrupt Flag 2
|
||
; GIFR.PCIF1 4 Pin Change Interrupt Flag 1
|
||
; GIFR.PCIF0 3 Pin Change Interrupt Flag 0
|
||
; GICR 0x005B General Interrupt Control Register
|
||
; GICR.INT1 7 External Interrupt Request 1 Enable
|
||
; GICR.INT0 6 External Interrupt Request 0 Enable
|
||
; GICR.INT2 5 External Interrupt Request 2 Enable
|
||
; GICR.PCIE1 4 Pin Change Interrupt Enable 1
|
||
; GICR.PCIE0 3 Pin Change Interrupt Enable 0
|
||
; GICR.IVSEL 1 Interrupt Vector Select
|
||
; GICR.IVCE 0 Interrupt Vector Change Enable
|
||
; UCSR1C 0x005C USART Control and Status Register C (page 180)
|
||
; UCSR1C.URSEL 7 Register Select
|
||
; UCSR1C.UMSEL 6 USART Mode Select
|
||
; UCSR1C.UPM1 5 Parity Mode 1
|
||
; UCSR1C.UPM0 4 Parity Mode 0
|
||
; UCSR1C.USBS 3 Stop Bit Select
|
||
; UCSR1C.UCSZ1 2 Character Size 1
|
||
; UCSR1C.UCSZ0 1 Character Size 0
|
||
; UCSR1C.UCPOL 0 Clock Polarity
|
||
; ; UBRR1H 0x005C USART Baud Rate Register High
|
||
; ; UBRR1H.URSEL 15 Register Select
|
||
; ; UBRR1H.UBRR11 11 USART Baud Rate Register 11
|
||
; ; UBRR1H.UBRR10 10 USART Baud Rate Register 10
|
||
; ; UBRR1H.UBRR9 9 USART Baud Rate Register 9
|
||
; ; UBRR1H.UBRR8 8 USART Baud Rate Register 8
|
||
; SPL 0x005D Stack Pointer Low
|
||
; SPL.SP7 7
|
||
; SPL.SP6 6
|
||
; SPL.SP5 5
|
||
; SPL.SP4 4
|
||
; SPL.SP3 3
|
||
; SPL.SP2 2
|
||
; SPL.SP1 1
|
||
; SPL.SP0 0
|
||
; SPH 0x005E Stack Pointer High
|
||
; SPH.SP15 15
|
||
; SPH.SP14 14
|
||
; SPH.SP13 13
|
||
; SPH.SP12 12
|
||
; SPH.SP11 11
|
||
; SPH.SP10 10
|
||
; SPH.SP9 9
|
||
; SPH.SP8 8
|
||
; SREG 0x005F Status Register
|
||
; SREG.I 7 Global Interrupt Enable
|
||
; SREG.T 6 Bit Copy Storage
|
||
; SREG.H 5 Half Carry Flag
|
||
; SREG.S 4 Sign Bit
|
||
; SREG.V 3 Two's Complement Overflow Flag
|
||
; SREG.N 2 Negative Flag
|
||
; SREG.Z 1 Zero Flag
|
||
; SREG.C 0 CarryFlag
|
||
; RESERVED0060 0x0060 RESERVED
|
||
; CLKPR 0x0061 Clock Prescale Register
|
||
; CLKPR.CPCE 7 Clock Prescaler Change Enable
|
||
; CLKPR.CLKPS3 3 Clock Prescaler Select Bit 3
|
||
; CLKPR.CLKPS2 2 Clock Prescaler Select Bit 2
|
||
; CLKPR.CLKPS1 1 Clock Prescaler Select Bit 1
|
||
; CLKPR.CLKPS0 0 Clock Prescaler Select Bit 0
|
||
; RESERVED0062 0x0062 RESERVED
|
||
; RESERVED0063 0x0063 RESERVED
|
||
; RESERVED0064 0x0064 RESERVED
|
||
; RESERVED0065 0x0065 RESERVED
|
||
; RESERVED0066 0x0066 RESERVED
|
||
; RESERVED0067 0x0067 RESERVED
|
||
; RESERVED0068 0x0068 RESERVED
|
||
; RESERVED0069 0x0069 RESERVED
|
||
; RESERVED006A 0x006A RESERVED
|
||
; PCMSK0 0x006B Pin Change Mask Register 0
|
||
; PCMSK0.PCINT7 7 Pin Change Enable Mask 7
|
||
; PCMSK0.PCINT6 6 Pin Change Enable Mask 6
|
||
; PCMSK0.PCINT5 5 Pin Change Enable Mask 5
|
||
; PCMSK0.PCINT4 4 Pin Change Enable Mask 4
|
||
; PCMSK0.PCINT3 3 Pin Change Enable Mask 3
|
||
; PCMSK0.PCINT2 2 Pin Change Enable Mask 2
|
||
; PCMSK0.PCINT1 1 Pin Change Enable Mask 1
|
||
; PCMSK0.PCINT0 0 Pin Change Enable Mask 0
|
||
; PCMSK1 0x006C Pin Change Mask Register 1
|
||
; PCMSK1.PCINT15 15 Pin Change Enable Mask 15
|
||
; PCMSK1.PCINT14 14 Pin Change Enable Mask 14
|
||
; PCMSK1.PCINT13 13 Pin Change Enable Mask 13
|
||
; PCMSK1.PCINT12 12 Pin Change Enable Mask 12
|
||
; PCMSK1.PCINT11 11 Pin Change Enable Mask 11
|
||
; PCMSK1.PCINT10 10 Pin Change Enable Mask 10
|
||
; PCMSK1.PCINT9 9 Pin Change Enable Mask 9
|
||
; PCMSK1.PCINT8 8 Pin Change Enable Mask 8
|
||
; RESERVED006D 0x006D RESERVED
|
||
; RESERVED006E 0x006E RESERVED
|
||
; RESERVED006F 0x006F RESERVED
|
||
; RESERVED0070 0x0070 RESERVED
|
||
; RESERVED0071 0x0071 RESERVED
|
||
; RESERVED0072 0x0072 RESERVED
|
||
; RESERVED0073 0x0073 RESERVED
|
||
; RESERVED0074 0x0074 RESERVED
|
||
; RESERVED0075 0x0075 RESERVED
|
||
; RESERVED0076 0x0076 RESERVED
|
||
; RESERVED0077 0x0077 RESERVED
|
||
; RESERVED0078 0x0078 RESERVED
|
||
; RESERVED0079 0x0079 RESERVED
|
||
; RESERVED007A 0x007A RESERVED
|
||
; RESERVED007B 0x007B RESERVED
|
||
; ETIFR 0x007C Extended Timer/Counter Interrupt Flag Register
|
||
; ETIFR.ICF3 5 Timer/Counter3, Input Capture Flag
|
||
; ETIFR.OCF3A 4 Timer/Counter3, Output Compare A Match Flag
|
||
; ETIFR.OC3FB 3 Timer/Counter3, Output Compare B Match Flag
|
||
; ETIFR.TOV3 2 Timer/Counter3, Overflow Flag
|
||
; ETIMSK 0x007D Extended Timer/Counter Interrupt Mask Register
|
||
; ETIMSK.TICIE3 5 Timer/Counter3, Input Capture Interrupt Enable
|
||
; ETIMSK.OCIE3A 4 Timer/Counter3, Output Compare A Match Interrupt Enable
|
||
; ETIMSK.OCIE3B 3 Timer/Counter3, Output Compare B Match Interrupt Enable
|
||
; ETIMSK.TOIE3 2 Timer/Counter3, Overflow Interrupt Enable
|
||
; RESERVED007E 0x007E RESERVED
|
||
; RESERVED007F 0x007F RESERVED
|
||
; ICR3L 0x0080 Input Capture Register Low Byte
|
||
; ICR3H 0x0081 Input Capture Register High Byte
|
||
; RESERVED0082 0x0082 RESERVED
|
||
; RESERVED0083 0x0083 RESERVED
|
||
; OCR3BL 0x0084 Output Compare Register B Low Byte
|
||
; OCR3BH 0x0085 Output Compare Register B High Byte
|
||
; OCR3AL 0x0086 Output Compare Register A Low Byte
|
||
; OCR3AH 0x0087 Output Compare Register A High Byte
|
||
; TCNT3L 0x0088 Counter Register Low Byte
|
||
; TCNT3H 0x0089 Counter Register High Byte
|
||
; TCCR3B 0x008A Timer/Counter3 Control Register A
|
||
; TCCR3B.COM3A1 7 Compare Output Mode for channel A 1
|
||
; TCCR3B.COM3A0 6 Compare Output Mode for channel A 0
|
||
; TCCR3B.COM3B1 5 Compare Output Mode for channel B 1
|
||
; TCCR3B.COM3B0 4 Compare Output Mode for channel B 0
|
||
; TCCR3B.FOC3A 3 Force Output Compare for channel A
|
||
; TCCR3B.FOC3B 2 Force Output Compare for channel B
|
||
; TCCR3B.WGM31 1 Waveform Generation Mode 1
|
||
; TCCR3B.WGM30 0 Waveform Generation Mode 0
|
||
; TCCR3A 0x008B Timer/Counter3 Control Register B
|
||
; TCCR3A.ICNC3 7 Input Capture Noise Canceler
|
||
; TCCR3A.ICES3 6 Input CaptureEdgeSelect
|
||
; TCCR3A.WGM33 4 Waveform Generation Mode 3
|
||
; TCCR3A.WGM32 3 Waveform Generation Mode 2
|
||
; TCCR3A.CS32 2 Clock Select 2
|
||
; TCCR3A.CS31 1 Clock Select 1
|
||
; TCCR3A.CS30 0 Clock Select 0
|
||
|
||
|
||
.ATmega163_L
|
||
SUBARCH=5
|
||
; doc1142.pdf
|
||
;
|
||
|
||
RAM=1024
|
||
ROM=16384
|
||
EEPROM=512
|
||
|
||
; MEMORY MAP
|
||
|
||
|
||
; Interrupt and reset vector assignments
|
||
entry __RESET 0x0000 External Pin, Power-on Reset, Brown-out Reset and Watchdog Reset
|
||
entry INT0_ 0x0002 External Interrupt Request 0
|
||
entry INT1_ 0x0004 External Interrupt Request 1
|
||
entry TIMER2_COMP 0x0006 Timer/Counter2 Compare Match
|
||
entry TIMER2_OVF 0x0008 Timer/Counter2 Overflow
|
||
entry TIMER1_CAPT 0x000A Timer/Counter1 Capture Event
|
||
entry TIMER1_COMPA 0x000C Timer/Counter1 Compare Match A
|
||
entry TIMER1_COMPB 0x000E Timer/Counter1 Compare Match B
|
||
entry TIMER1_OVF 0x0010 Timer/Counter1 Overflow
|
||
entry TIMER0_OVF 0x0012 Timer/Counter0 Overflow
|
||
entry SPI_STC 0x0014 Serial Transfer Complete
|
||
entry UART_RXC 0x0016 UART, Rx Complete
|
||
entry UART_UDRE 0x0018 UART Data Register Empty
|
||
entry UART_TXC 0x001A UART, Tx Complete
|
||
entry ADC_ 0x001C ADC Conversion Complete
|
||
entry EE_RDY 0x001E EEPROM Ready
|
||
entry ANA_COMP 0x0020 Analog Comparator
|
||
entry TWI_ 0x0022 2-wire Serial Interface
|
||
|
||
|
||
; INPUT/OUTPUT PORTS
|
||
TWBR 0x0000 The 2-wire Serial Interface Bit Rate Register
|
||
TWBR.TWBR7 7 2-wire Serial Interface Bit Rate Register bit 7
|
||
TWBR.TWBR6 6 2-wire Serial Interface Bit Rate Register bit 6
|
||
TWBR.TWBR5 5 2-wire Serial Interface Bit Rate Register bit 5
|
||
TWBR.TWBR4 4 2-wire Serial Interface Bit Rate Register bit 4
|
||
TWBR.TWBR3 3 2-wire Serial Interface Bit Rate Register bit 3
|
||
TWBR.TWBR2 2 2-wire Serial Interface Bit Rate Register bit 2
|
||
TWBR.TWBR1 1 2-wire Serial Interface Bit Rate Register bit 1
|
||
TWBR.TWBR0 0 2-wire Serial Interface Bit Rate Register bit 0
|
||
TWSR 0x0001 The 2-wire Serial Interface Status Register
|
||
TWSR.TWS7 7 2-wire Serial Interface Status bit 7
|
||
TWSR.TWS6 6 2-wire Serial Interface Status bit 6
|
||
TWSR.TWS5 5 2-wire Serial Interface Status bit 5
|
||
TWSR.TWS4 4 2-wire Serial Interface Status bit 4
|
||
TWSR.TWS3 3 2-wire Serial Interface Status bit 3
|
||
TWAR 0x0002 The 2-wire Serial Interface (Slave) Address Register
|
||
TWAR.TWA6 7 2-wire Serial Interface (Slave) Address Register bit 6
|
||
TWAR.TWA5 6 2-wire Serial Interface (Slave) Address Register bit 5
|
||
TWAR.TWA4 5 2-wire Serial Interface (Slave) Address Register bit 4
|
||
TWAR.TWA3 4 2-wire Serial Interface (Slave) Address Register bit 3
|
||
TWAR.TWA2 3 2-wire Serial Interface (Slave) Address Register bit 2
|
||
TWAR.TWA1 2 2-wire Serial Interface (Slave) Address Register bit 1
|
||
TWAR.TWA0 1 2-wire Serial Interface (Slave) Address Register bit 0
|
||
TWAR.TWGCE 0 2-wire Serial Interface General Call Recognition Enable Bit
|
||
TWDR 0x0003 The 2-wire Serial Interface Data Register
|
||
TWDR.TWD7 7 2-wire Serial Interface Data Register bit 7
|
||
TWDR.TWD6 6 2-wire Serial Interface Data Register bit 6
|
||
TWDR.TWD5 5 2-wire Serial Interface Data Register bit 5
|
||
TWDR.TWD4 4 2-wire Serial Interface Data Register bit 4
|
||
TWDR.TWD3 3 2-wire Serial Interface Data Register bit 3
|
||
TWDR.TWD2 2 2-wire Serial Interface Data Register bit 2
|
||
TWDR.TWD1 1 2-wire Serial Interface Data Register bit 1
|
||
TWDR.TWD0 0 2-wire Serial Interface Data Register bit 0
|
||
ADCL 0x0004 The ADC Data Register Low (ADLAR = 0)
|
||
ADCL.ADC7 7 ADC Conversion result 7
|
||
ADCL.ADC6 6 ADC Conversion result 6
|
||
ADCL.ADC5 5 ADC Conversion result 5
|
||
ADCL.ADC4 4 ADC Conversion result 4
|
||
ADCL.ADC3 3 ADC Conversion result 3
|
||
ADCL.ADC2 2 ADC Conversion result 2
|
||
ADCL.ADC1 1 ADC Conversion result 1
|
||
ADCL.ADC0 0 ADC Conversion result 0
|
||
ADCH 0x0005 The ADC Data Register High (ADLAR = 0)
|
||
ADCH.SIGN 15
|
||
ADCH.ADC9 9 ADC Conversion result 9
|
||
ADCH.ADC8 8 ADC Conversion result 8
|
||
; ADCL 0x0004 The ADC Data Register Low (ADLAR = 1)
|
||
; ADCL.ADC1 7 ADC Conversion result 1
|
||
; ADCL.ADC0 6 ADC Conversion result 0
|
||
; ADCH 0x0005 The ADC Data Register High (ADLAR = 1)
|
||
; ADCH.ADC9 15 ADC Conversion result 9
|
||
; ADCH.ADC8 14 ADC Conversion result 8
|
||
; ADCH.ADC7 13 ADC Conversion result 7
|
||
; ADCH.ADC6 12 ADC Conversion result 6
|
||
; ADCH.ADC5 11 ADC Conversion result 5
|
||
; ADCH.ADC4 10 ADC Conversion result 4
|
||
; ADCH.ADC3 9 ADC Conversion result 3
|
||
; ADCH.ADC2 8 ADC Conversion result 2
|
||
ADCSR 0x0006 The ADC Control and Status Register
|
||
ADCSR.ADEN 7 ADC Enable
|
||
ADCSR.ADSC 6 ADC Start Conversion
|
||
ADCSR.ADFR 5 ADC Free Running Select
|
||
ADCSR.ADIF 4 ADC Interrupt Flag
|
||
ADCSR.ADIE 3 ADC Interrupt Enable
|
||
ADCSR.ADPS2 2 ADC Prescaler Select Bit 2
|
||
ADCSR.ADPS1 1 ADC Prescaler Select Bit 1
|
||
ADCSR.ADPS0 0 ADC Prescaler Select Bit 0
|
||
ADMUX 0x0007 The ADC Multiplexer Selection Register
|
||
ADMUX.REFS1 7 Reference Selection Bit 1
|
||
ADMUX.REFS0 6 Reference Selection Bit 0
|
||
ADMUX.ADLAR 5 ADC Left Adjust Result
|
||
ADMUX.MUX4 4 Analog Channel and Gain Selection Bit 4
|
||
ADMUX.MUX3 3 Analog Channel and Gain Selection Bit 3
|
||
ADMUX.MUX2 2 Analog Channel and Gain Selection Bit 2
|
||
ADMUX.MUX1 1 Analog Channel and Gain Selection Bit 1
|
||
ADMUX.MUX0 0 Analog Channel and Gain Selection Bit 0
|
||
ACSR 0x0008 Analog Comparator Control And Status Register
|
||
ACSR.ACD 7 Analog Comparator Disable
|
||
ACSR.ACBG 6 Analog Comparator Bandgap Select
|
||
ACSR.ACO 5 Analog Comparator Output
|
||
ACSR.ACI 4 Analog Comparator Interrupt Flag
|
||
ACSR.ACIE 3 Analog Comparator Interrupt Enable
|
||
ACSR.ACIC 2 Analog Comparator Input Capture Enable
|
||
ACSR.ACIS1 1 Analog Comparator Interrupt Mode Select 1
|
||
ACSR.ACIS0 0 Analog Comparator Interrupt Mode Select 0
|
||
UBRR 0x0009 UART Baud Rate Register
|
||
UCSRB 0x000A UART Control and Status Register B
|
||
UCSRB.RXCIE 7 RX Complete Interrupt Enable
|
||
UCSRB.TXCIE 6 TX Complete Interrupt Enable
|
||
UCSRB.UDRIE 5 UART Data Register Empty Interrupt Enable
|
||
UCSRB.RXEN 4 Receiver Enable
|
||
UCSRB.TXEN 3 Transmitter Enable
|
||
UCSRB.CHR9 2 9 Bit Characters
|
||
UCSRB.RXB8 1 Receive Data Bit 8
|
||
UCSRB.TXB8 0 Transmit Data Bit 8
|
||
UCSRA 0x000B UART Control and Status Register A
|
||
UCSRA.RXC 7 UART Receive Complete
|
||
UCSRA.TXC 6 UART Transmit Complete
|
||
UCSRA.UDRE 5 UART Data Register Empty
|
||
UCSRA.FE 4 Framing Error
|
||
UCSRA.OR 3 OverRun
|
||
UCSRA.U2X 1 Double the UART Transmission Speed
|
||
UCSRA.MPCM 0 Multi-processor Communication Mode
|
||
UDR 0x000C UART I/O Data Register
|
||
SPCR 0x000D SPI Control Register
|
||
SPCR.SPIE 7 SPI Interrupt Enable
|
||
SPCR.SPE 6 SPI Enable
|
||
SPCR.DORD 5 Data Order
|
||
SPCR.MSTR 4 Master/Slave Select
|
||
SPCR.CPOL 3 Clock Polarity
|
||
SPCR.CPHA 2 Clock Phase
|
||
SPCR.SPR1 1 SPI Clock Rate Select 1
|
||
SPCR.SPR0 0 SPI Clock Rate Select 0
|
||
SPSR 0x000E The SPI Status Register
|
||
SPSR.SPIF 7 SPI Interrupt Flag
|
||
SPSR.WCOL 6 Write COLlision Flag
|
||
SPSR.SPI2X 0 Double SPI Speed Bit
|
||
SPDR 0x000F SPI Data Register
|
||
PIND 0x0010 Port D Input Pins Address
|
||
PIND.PIND7 7
|
||
PIND.PIND6 6
|
||
PIND.PIND5 5
|
||
PIND.PIND4 4
|
||
PIND.PIND3 3
|
||
PIND.PIND2 2
|
||
PIND.PIND1 1
|
||
PIND.PIND0 0
|
||
DDRD 0x0011 Port D Data Direction Register
|
||
DDRD.DDD7 7 Port D Data Direction Register bit 7
|
||
DDRD.DDD6 6 Port D Data Direction Register bit 6
|
||
DDRD.DDD5 5 Port D Data Direction Register bit 5
|
||
DDRD.DDD4 4 Port D Data Direction Register bit 4
|
||
DDRD.DDD3 3 Port D Data Direction Register bit 3
|
||
DDRD.DDD2 2 Port D Data Direction Register bit 2
|
||
DDRD.DDD1 1 Port D Data Direction Register bit 1
|
||
DDRD.DDD0 0 Port D Data Direction Register bit 0
|
||
PORTD 0x0012 Port D Data Register
|
||
PORTD.PORTD7 7 Port D Data Register bit 7
|
||
PORTD.PORTD6 6 Port D Data Register bit 6
|
||
PORTD.PORTD5 5 Port D Data Register bit 5
|
||
PORTD.PORTD4 4 Port D Data Register bit 4
|
||
PORTD.PORTD3 3 Port D Data Register bit 3
|
||
PORTD.PORTD2 2 Port D Data Register bit 2
|
||
PORTD.PORTD1 1 Port D Data Register bit 1
|
||
PORTD.PORTD0 0 Port D Data Register bit 0
|
||
PINC 0x0013 Port C Input Pins Address
|
||
PINC.PINC7 7
|
||
PINC.PINC6 6
|
||
PINC.PINC5 5
|
||
PINC.PINC4 4
|
||
PINC.PINC3 3
|
||
PINC.PINC2 2
|
||
PINC.PINC1 1
|
||
PINC.PINC0 0
|
||
DDRC 0x0014 Port C Data Direction Register
|
||
DDRC.DDC7 7 Port C Data Direction Register bit 7
|
||
DDRC.DDC6 6 Port C Data Direction Register bit 6
|
||
DDRC.DDC5 5 Port C Data Direction Register bit 5
|
||
DDRC.DDC4 4 Port C Data Direction Register bit 4
|
||
DDRC.DDC3 3 Port C Data Direction Register bit 3
|
||
DDRC.DDC2 2 Port C Data Direction Register bit 2
|
||
DDRC.DDC1 1 Port C Data Direction Register bit 1
|
||
DDRC.DDC0 0 Port C Data Direction Register bit 0
|
||
PORTC 0x0015 Port C Data Register
|
||
PORTC.PORTC7 7 Port C Data Register bit 7
|
||
PORTC.PORTC6 6 Port C Data Register bit 6
|
||
PORTC.PORTC5 5 Port C Data Register bit 5
|
||
PORTC.PORTC4 4 Port C Data Register bit 4
|
||
PORTC.PORTC3 3 Port C Data Register bit 3
|
||
PORTC.PORTC2 2 Port C Data Register bit 2
|
||
PORTC.PORTC1 1 Port C Data Register bit 1
|
||
PORTC.PORTC0 0 Port C Data Register bit 0
|
||
PINB 0x0016 Port B Input Pins Address
|
||
PINB.PINB7 7
|
||
PINB.PINB6 6
|
||
PINB.PINB5 5
|
||
PINB.PINB4 4
|
||
PINB.PINB3 3
|
||
PINB.PINB2 2
|
||
PINB.PINB1 1
|
||
PINB.PINB0 0
|
||
DDRB 0x0017 Port B Data Direction Register
|
||
DDRB.DDB7 7 Port B Data Direction Register bit 7
|
||
DDRB.DDB6 6 Port B Data Direction Register bit 6
|
||
DDRB.DDB5 5 Port B Data Direction Register bit 5
|
||
DDRB.DDB4 4 Port B Data Direction Register bit 4
|
||
DDRB.DDB3 3 Port B Data Direction Register bit 3
|
||
DDRB.DDB2 2 Port B Data Direction Register bit 2
|
||
DDRB.DDB1 1 Port B Data Direction Register bit 1
|
||
DDRB.DDB0 0 Port B Data Direction Register bit 0
|
||
PORTB 0x0018 Port B Data Register
|
||
PORTB.PORTB7 7 Port B Data Register bit 7
|
||
PORTB.PORTB6 6 Port B Data Register bit 6
|
||
PORTB.PORTB5 5 Port B Data Register bit 5
|
||
PORTB.PORTB4 4 Port B Data Register bit 4
|
||
PORTB.PORTB3 3 Port B Data Register bit 3
|
||
PORTB.PORTB2 2 Port B Data Register bit 2
|
||
PORTB.PORTB1 1 Port B Data Register bit 1
|
||
PORTB.PORTB0 0 Port B Data Register bit 0
|
||
PINA 0x0019 Port A Input Pins Address
|
||
PINA.PINA7 7
|
||
PINA.PINA6 6
|
||
PINA.PINA5 5
|
||
PINA.PINA4 4
|
||
PINA.PINA3 3
|
||
PINA.PINA2 2
|
||
PINA.PINA1 1
|
||
PINA.PINA0 0
|
||
DDRA 0x001A Port A Data Direction Register
|
||
DDRA.DDA7 7 Port A Data Direction Register bit 7
|
||
DDRA.DDA6 6 Port A Data Direction Register bit 6
|
||
DDRA.DDA5 5 Port A Data Direction Register bit 5
|
||
DDRA.DDA4 4 Port A Data Direction Register bit 4
|
||
DDRA.DDA3 3 Port A Data Direction Register bit 3
|
||
DDRA.DDA2 2 Port A Data Direction Register bit 2
|
||
DDRA.DDA1 1 Port A Data Direction Register bit 1
|
||
DDRA.DDA0 0 Port A Data Direction Register bit 0
|
||
PORTA 0x001B Port A Data Register
|
||
PORTA.PORTA7 7 Port A Data Register bit 7
|
||
PORTA.PORTA6 6 Port A Data Register bit 6
|
||
PORTA.PORTA5 5 Port A Data Register bit 5
|
||
PORTA.PORTA4 4 Port A Data Register bit 4
|
||
PORTA.PORTA3 3 Port A Data Register bit 3
|
||
PORTA.PORTA2 2 Port A Data Register bit 2
|
||
PORTA.PORTA1 1 Port A Data Register bit 1
|
||
PORTA.PORTA0 0 Port A Data Register bit 0
|
||
EECR 0x001C The EEPROM Control Register
|
||
EECR.EERIE 3 EEPROM Ready Interrupt Enable
|
||
EECR.EEMWE 2 EEPROM Master Write Enable
|
||
EECR.EEWE 1 EEPROM Write Enable
|
||
EECR.EERE 0 EEPROM Read Enable
|
||
EEDR 0x001D EEPROM Data Register
|
||
EEARL 0x001E EEPROM Address Register Low
|
||
EEARL.EEAR7 7 EEPROM Address 7
|
||
EEARL.EEAR6 6 EEPROM Address 6
|
||
EEARL.EEAR5 5 EEPROM Address 5
|
||
EEARL.EEAR4 4 EEPROM Address 4
|
||
EEARL.EEAR3 3 EEPROM Address 3
|
||
EEARL.EEAR2 2 EEPROM Address 2
|
||
EEARL.EEAR1 1 EEPROM Address 1
|
||
EEARL.EEAR0 0 EEPROM Address 0
|
||
EEARH 0x001F EEPROM Address Register High
|
||
EEARH.EEAR8 8 EEPROM Address 8
|
||
UBRRHI 0x0020 UART Baud Rate Register
|
||
WDTCR 0x0021 Watchdog Timer Control Register
|
||
WDTCR.WDTOE 4 Watchdog Turn-off Enable
|
||
WDTCR.WDE 3 Watchdog Enable
|
||
WDTCR.WDP2 2 Watchdog Timer Prescaler 2
|
||
WDTCR.WDP1 1 Watchdog Timer Prescaler 1
|
||
WDTCR.WDP0 0 Watchdog Timer Prescaler 0
|
||
ASSR 0x0022 Asynchronous Status Register
|
||
ASSR.AS2 3 Asynchronous Timer/Counter2
|
||
ASSR.TCN2UB 2 Timer/Counter2 Update Busy
|
||
ASSR.OCR2UB 1 Output Compare Register2 Update Busy
|
||
ASSR.TCR2UB 0 Timer/Counter Control Register2 Update Busy
|
||
OCR2 0x0023 Timer/Counter2 Output Compare Register
|
||
TCNT2 0x0024 Timer/Counter2
|
||
TCCR2 0x0025 Timer/Counter2 Control Register
|
||
TCCR2.FOC2 7 Force Output Compare
|
||
TCCR2.PWM2 6 Pulse Width Modulator Enable
|
||
TCCR2.COM21 5 Compare Output Mode, bit 1
|
||
TCCR2.COM20 4 Compare Output Mode, bit 0
|
||
TCCR2.CTC2 3 Clear Timer/Counter on Compare Match
|
||
TCCR2.CS22 2 Clock Select Bit 2
|
||
TCCR2.CS21 1 Clock Select Bit 1
|
||
TCCR2.CS20 0 Clock Select Bit 0
|
||
ICR1L 0x0026 Input Capture Register Low Byte
|
||
ICR1H 0x0027 Input Capture Register High Byte
|
||
OCR1BL 0x0028 Output Compare Register B Low Byte
|
||
OCR1BH 0x0029 Output Compare Register B High Byte
|
||
OCR1AL 0x002A Output Compare Register A Low Byte
|
||
OCR1AH 0x002B Output Compare Register A High Byte
|
||
TCNT1L 0x002C Counter Register Low Byte
|
||
TCNT1H 0x002D Counter Register High Byte
|
||
TCCR1B 0x002E Timer/Counter1 Control Register B
|
||
TCCR1B.ICNC1 7 Input Capture1 Noise Canceler (4 CKs)
|
||
TCCR1B.ICES1 6 Input Capture1 Edge Select
|
||
TCCR1B.CTC1 3 Clear Timer/Counter1 on Compare Match
|
||
TCCR1B.CS12 2 Clock Select1, Bit 2
|
||
TCCR1B.CS11 1 Clock Select1, Bit 1
|
||
TCCR1B.CS10 0 Clock Select1, Bit 0
|
||
TCCR1A 0x002F Timer/Counter1 Control Register A
|
||
TCCR1A.COM1A1 7 Compare Output Mode1A, Bit 1
|
||
TCCR1A.COM1A0 6 Compare Output Mode1A, Bit 0
|
||
TCCR1A.COM1B1 5 Compare Output Mode1B, Bit 1
|
||
TCCR1A.COM1B0 4 Compare Output Mode1B, Bit 0
|
||
TCCR1A.FOC1A 3 Force Output Compare1A
|
||
TCCR1A.FOC1B 2 Force Output Compare1B
|
||
TCCR1A.PWM11 1 Pulse Width Modulator Select Bit 1
|
||
TCCR1A.PWM10 0 Pulse Width Modulator Select Bit 0
|
||
SFIOR 0x0030 Special Function I/O Register
|
||
SFIOR.ACME 3 Analog Comparator Multiplexer Enable
|
||
SFIOR.PUD 2 Pull-up Disable
|
||
SFIOR.PSR2 1 Prescaler Reset Timer/Counter2
|
||
SFIOR.PSR10 0 Prescaler Reset Timer/Counter1 and Timer/Counter0
|
||
OSCCAL 0x0031 Oscillator Calibration Register
|
||
OSCCAL.CAL7 7 Oscillator Calibration Value 7
|
||
OSCCAL.CAL6 6 Oscillator Calibration Value 6
|
||
OSCCAL.CAL5 5 Oscillator Calibration Value 5
|
||
OSCCAL.CAL4 4 Oscillator Calibration Value 4
|
||
OSCCAL.CAL3 3 Oscillator Calibration Value 3
|
||
OSCCAL.CAL2 2 Oscillator Calibration Value 2
|
||
OSCCAL.CAL1 1 Oscillator Calibration Value 1
|
||
OSCCAL.CAL0 0 Oscillator Calibration Value 0
|
||
TCNT0 0x0032 Timer/Counter 0
|
||
TCCR0 0x0033 Timer/Counter0 Control Register
|
||
TCCR0.CS02 2 Clock Select0, Bit 2
|
||
TCCR0.CS01 1 Clock Select0, Bit 1
|
||
TCCR0.CS00 0 Clock Select0, Bit 0
|
||
MCUSR 0x0034 MCU Status Register
|
||
MCUSR.WDRF 3 Watchdog Reset Flag
|
||
MCUSR.BORF 2 Brown-out Reset Flag
|
||
MCUSR.EXTRF 1 External Reset Flag
|
||
MCUSR.PORF 0 Power-on Reset Flag
|
||
MCUCR 0x0035 MCU Control Register
|
||
MCUCR.SE 6 Sleep Enable
|
||
MCUCR.SM1 5 Sleep Mode Select Bit 1
|
||
MCUCR.SM0 4 Sleep Mode Select Bit 0
|
||
MCUCR.ISC11 3 Interrupt Sense Control 1 Bit 1
|
||
MCUCR.ISC10 2 Interrupt Sense Control 1 Bit 0
|
||
MCUCR.ISC01 1 Interrupt Sense Control 0 Bit 1
|
||
MCUCR.ISC00 0 Interrupt Sense Control 0 Bit 0
|
||
TWCR 0x0036 2-wire Serial Interface Control Register
|
||
TWCR.TWINT 7 2-wire Serial Interface Interrupt Flag
|
||
TWCR.TWEA 6 2-wire Serial Interface Enable Acknowledge Flag
|
||
TWCR.TWSTA 5 2-wire Serial Bus START Condition Flag
|
||
TWCR.TWSTO 4 2-wire Serial Bus STOP Condition Flag
|
||
TWCR.TWWC 3 2-wire Serial Bus Write Collision Flag
|
||
TWCR.TWEN 2 2-wire Serial Interface Enable Bit
|
||
TWCR.TWIE 0 2-wire Serial Interface Interrupt Enable
|
||
SPMCR 0x0037 Store Program Memory Control Register
|
||
SPMCR.ASB 6 Application Section Busy
|
||
SPMCR.ASRE 4 Application Section Read Enable
|
||
SPMCR.BLBSET 3 Boot Lock Bit Set
|
||
SPMCR.PGWRT 2 Page Write
|
||
SPMCR.PGERS 1 Page Erase
|
||
SPMCR.SPMEN 0 Store Program Memory Enable
|
||
TIFR 0x0038 Timer/Counter Interrupt Flag Register
|
||
TIFR.OCF2 7 Output Compare Flag 2
|
||
TIFR.TOV2 6 Timer/Counter2 Overflow Flag
|
||
TIFR.ICF1 5 Input Capture Flag 1
|
||
TIFR.OCF1A 4 Output Compare Flag 1A
|
||
TIFR.OCF1B 3 Output Compare Flag 1B
|
||
TIFR.TOV1 2 Timer/Counter1 Overflow Flag
|
||
TIFR.TOV0 0 Timer/Counter0 Overflow Flag
|
||
TIMSK 0x0039 Timer/Counter Interrupt Mask Register
|
||
TIMSK.OCIE2 7 Timer/Counter2 Output Compare Match Interrupt Enable
|
||
TIMSK.TOIE2 6 Timer/Counter2 Overflow Interrupt Enable
|
||
TIMSK.TICIE1 5 Timer/Counter1 Input Capture Interrupt Enable
|
||
TIMSK.OCIE1A 4 Timer/Counter1 Output CompareA Match Interrupt Enable
|
||
TIMSK.OCIE1B 3 Timer/Counter1 Output CompareB Match Interrupt Enable
|
||
TIMSK.TOIE1 2 Timer/Counter1 Overflow Interrupt Enable
|
||
TIMSK.TOIE0 0 Timer/Counter0 Overflow Interrupt Enable
|
||
GIFR 0x003A General Interrupt Flag Register
|
||
GIFR.INTF1 7 External Interrupt Flag1
|
||
GIFR.INTF0 6 External Interrupt Flag0
|
||
GIMSK 0x003B General Interrupt Mask Register
|
||
GIMSK.INT1 7 External Interrupt Request 1 Enable
|
||
GIMSK.INT0 6 External Interrupt Request 0 Enable
|
||
RESERVED003C 0x003C RESERVED
|
||
SPL 0x003D Stack Pointer Low
|
||
SPL.SP7 7
|
||
SPL.SP6 6
|
||
SPL.SP5 5
|
||
SPL.SP4 4
|
||
SPL.SP3 3
|
||
SPL.SP2 2
|
||
SPL.SP1 1
|
||
SPL.SP0 0
|
||
SPH 0x003E Stack Pointer High
|
||
SPH.SP10 10
|
||
SPH.SP9 9
|
||
SPH.SP8 8
|
||
SREG 0x003F Status Register
|
||
SREG.I 7 Global Interrupt Enable
|
||
SREG.T 6 Bit Copy Storage
|
||
SREG.H 5 Half Carry Flag
|
||
SREG.S 4 Sign Bit
|
||
SREG.V 3 Two's Complement Overflow Flag
|
||
SREG.N 2 Negative Flag
|
||
SREG.Z 1 Zero Flag
|
||
SREG.C 0 Carry Flag
|
||
|
||
; TWBR 0x0020 The 2-wire Serial Interface Bit Rate Register
|
||
; TWBR.TWBR7 7 2-wire Serial Interface Bit Rate Register bit 7
|
||
; TWBR.TWBR6 6 2-wire Serial Interface Bit Rate Register bit 6
|
||
; TWBR.TWBR5 5 2-wire Serial Interface Bit Rate Register bit 5
|
||
; TWBR.TWBR4 4 2-wire Serial Interface Bit Rate Register bit 4
|
||
; TWBR.TWBR3 3 2-wire Serial Interface Bit Rate Register bit 3
|
||
; TWBR.TWBR2 2 2-wire Serial Interface Bit Rate Register bit 2
|
||
; TWBR.TWBR1 1 2-wire Serial Interface Bit Rate Register bit 1
|
||
; TWBR.TWBR0 0 2-wire Serial Interface Bit Rate Register bit 0
|
||
; TWSR 0x0021 The 2-wire Serial Interface Status Register
|
||
; TWSR.TWS7 7 2-wire Serial Interface Status bit 7
|
||
; TWSR.TWS6 6 2-wire Serial Interface Status bit 6
|
||
; TWSR.TWS5 5 2-wire Serial Interface Status bit 5
|
||
; TWSR.TWS4 4 2-wire Serial Interface Status bit 4
|
||
; TWSR.TWS3 3 2-wire Serial Interface Status bit 3
|
||
; TWAR 0x0022 The 2-wire Serial Interface (Slave) Address Register
|
||
; TWAR.TWA6 7 2-wire Serial Interface (Slave) Address Register bit 6
|
||
; TWAR.TWA5 6 2-wire Serial Interface (Slave) Address Register bit 5
|
||
; TWAR.TWA4 5 2-wire Serial Interface (Slave) Address Register bit 4
|
||
; TWAR.TWA3 4 2-wire Serial Interface (Slave) Address Register bit 3
|
||
; TWAR.TWA2 3 2-wire Serial Interface (Slave) Address Register bit 2
|
||
; TWAR.TWA1 2 2-wire Serial Interface (Slave) Address Register bit 1
|
||
; TWAR.TWA0 1 2-wire Serial Interface (Slave) Address Register bit 0
|
||
; TWAR.TWGCE 0 2-wire Serial Interface General Call Recognition Enable Bit
|
||
; TWDR 0x0023 The 2-wire Serial Interface Data Register
|
||
; TWDR.TWD7 7 2-wire Serial Interface Data Register bit 7
|
||
; TWDR.TWD6 6 2-wire Serial Interface Data Register bit 6
|
||
; TWDR.TWD5 5 2-wire Serial Interface Data Register bit 5
|
||
; TWDR.TWD4 4 2-wire Serial Interface Data Register bit 4
|
||
; TWDR.TWD3 3 2-wire Serial Interface Data Register bit 3
|
||
; TWDR.TWD2 2 2-wire Serial Interface Data Register bit 2
|
||
; TWDR.TWD1 1 2-wire Serial Interface Data Register bit 1
|
||
; TWDR.TWD0 0 2-wire Serial Interface Data Register bit 0
|
||
; ADCL 0x0024 The ADC Data Register Low (ADLAR = 0)
|
||
; ADCL.ADC7 7 ADC Conversion result 7
|
||
; ADCL.ADC6 6 ADC Conversion result 6
|
||
; ADCL.ADC5 5 ADC Conversion result 5
|
||
; ADCL.ADC4 4 ADC Conversion result 4
|
||
; ADCL.ADC3 3 ADC Conversion result 3
|
||
; ADCL.ADC2 2 ADC Conversion result 2
|
||
; ADCL.ADC1 1 ADC Conversion result 1
|
||
; ADCL.ADC0 0 ADC Conversion result 0
|
||
; ADCH 0x0025 The ADC Data Register High (ADLAR = 0)
|
||
; ADCH.SIGN 15
|
||
; ADCH.ADC9 9 ADC Conversion result 9
|
||
; ADCH.ADC8 8 ADC Conversion result 8
|
||
; ; ADCL 0x0024 The ADC Data Register Low (ADLAR = 1)
|
||
; ; ADCL.ADC1 7 ADC Conversion result 1
|
||
; ; ADCL.ADC0 6 ADC Conversion result 0
|
||
; ; ADCH 0x0025 The ADC Data Register High (ADLAR = 1)
|
||
; ; ADCH.ADC9 15 ADC Conversion result 9
|
||
; ; ADCH.ADC8 14 ADC Conversion result 8
|
||
; ; ADCH.ADC7 13 ADC Conversion result 7
|
||
; ; ADCH.ADC6 12 ADC Conversion result 6
|
||
; ; ADCH.ADC5 11 ADC Conversion result 5
|
||
; ; ADCH.ADC4 10 ADC Conversion result 4
|
||
; ; ADCH.ADC3 9 ADC Conversion result 3
|
||
; ; ADCH.ADC2 8 ADC Conversion result 2
|
||
; ADCSR 0x0026 The ADC Control and Status Register
|
||
; ADCSR.ADEN 7 ADC Enable
|
||
; ADCSR.ADSC 6 ADC Start Conversion
|
||
; ADCSR.ADFR 5 ADC Free Running Select
|
||
; ADCSR.ADIF 4 ADC Interrupt Flag
|
||
; ADCSR.ADIE 3 ADC Interrupt Enable
|
||
; ADCSR.ADPS2 2 ADC Prescaler Select Bit 2
|
||
; ADCSR.ADPS1 1 ADC Prescaler Select Bit 1
|
||
; ADCSR.ADPS0 0 ADC Prescaler Select Bit 0
|
||
; ADMUX 0x0027 The ADC Multiplexer Selection Register
|
||
; ADMUX.REFS1 7 Reference Selection Bit 1
|
||
; ADMUX.REFS0 6 Reference Selection Bit 0
|
||
; ADMUX.ADLAR 5 ADC Left Adjust Result
|
||
; ADMUX.MUX4 4 Analog Channel and Gain Selection Bit 4
|
||
; ADMUX.MUX3 3 Analog Channel and Gain Selection Bit 3
|
||
; ADMUX.MUX2 2 Analog Channel and Gain Selection Bit 2
|
||
; ADMUX.MUX1 1 Analog Channel and Gain Selection Bit 1
|
||
; ADMUX.MUX0 0 Analog Channel and Gain Selection Bit 0
|
||
; ACSR 0x0028 Analog Comparator Control And Status Register
|
||
; ACSR.ACD 7 Analog Comparator Disable
|
||
; ACSR.ACBG 6 Analog Comparator Bandgap Select
|
||
; ACSR.ACO 5 Analog Comparator Output
|
||
; ACSR.ACI 4 Analog Comparator Interrupt Flag
|
||
; ACSR.ACIE 3 Analog Comparator Interrupt Enable
|
||
; ACSR.ACIC 2 Analog Comparator Input Capture Enable
|
||
; ACSR.ACIS1 1 Analog Comparator Interrupt Mode Select 1
|
||
; ACSR.ACIS0 0 Analog Comparator Interrupt Mode Select 0
|
||
; UBRR 0x0029 UART Baud Rate Register
|
||
; UCSRB 0x002A UART Control and Status Register B
|
||
; UCSRB.RXCIE 7 RX Complete Interrupt Enable
|
||
; UCSRB.TXCIE 6 TX Complete Interrupt Enable
|
||
; UCSRB.UDRIE 5 UART Data Register Empty Interrupt Enable
|
||
; UCSRB.RXEN 4 Receiver Enable
|
||
; UCSRB.TXEN 3 Transmitter Enable
|
||
; UCSRB.CHR9 2 9 Bit Characters
|
||
; UCSRB.RXB8 1 Receive Data Bit 8
|
||
; UCSRB.TXB8 0 Transmit Data Bit 8
|
||
; UCSRA 0x002B UART Control and Status Register A
|
||
; UCSRA.RXC 7 UART Receive Complete
|
||
; UCSRA.TXC 6 UART Transmit Complete
|
||
; UCSRA.UDRE 5 UART Data Register Empty
|
||
; UCSRA.FE 4 Framing Error
|
||
; UCSRA.OR 3 OverRun
|
||
; UCSRA.U2X 1 Double the UART Transmission Speed
|
||
; UCSRA.MPCM 0 Multi-processor Communication Mode
|
||
; UDR 0x002C UART I/O Data Register
|
||
; SPCR 0x002D SPI Control Register
|
||
; SPCR.SPIE 7 SPI Interrupt Enable
|
||
; SPCR.SPE 6 SPI Enable
|
||
; SPCR.DORD 5 Data Order
|
||
; SPCR.MSTR 4 Master/Slave Select
|
||
; SPCR.CPOL 3 Clock Polarity
|
||
; SPCR.CPHA 2 Clock Phase
|
||
; SPCR.SPR1 1 SPI Clock Rate Select 1
|
||
; SPCR.SPR0 0 SPI Clock Rate Select 0
|
||
; SPSR 0x002E The SPI Status Register
|
||
; SPSR.SPIF 7 SPI Interrupt Flag
|
||
; SPSR.WCOL 6 Write COLlision Flag
|
||
; SPSR.SPI2X 0 Double SPI Speed Bit
|
||
; SPDR 0x002F SPI Data Register
|
||
; PIND 0x0030 Port D Input Pins Address
|
||
; PIND.PIND7 7
|
||
; PIND.PIND6 6
|
||
; PIND.PIND5 5
|
||
; PIND.PIND4 4
|
||
; PIND.PIND3 3
|
||
; PIND.PIND2 2
|
||
; PIND.PIND1 1
|
||
; PIND.PIND0 0
|
||
; DDRD 0x0031 Port D Data Direction Register
|
||
; DDRD.DDD7 7 Port D Data Direction Register bit 7
|
||
; DDRD.DDD6 6 Port D Data Direction Register bit 6
|
||
; DDRD.DDD5 5 Port D Data Direction Register bit 5
|
||
; DDRD.DDD4 4 Port D Data Direction Register bit 4
|
||
; DDRD.DDD3 3 Port D Data Direction Register bit 3
|
||
; DDRD.DDD2 2 Port D Data Direction Register bit 2
|
||
; DDRD.DDD1 1 Port D Data Direction Register bit 1
|
||
; DDRD.DDD0 0 Port D Data Direction Register bit 0
|
||
; PORTD 0x0032 Port D Data Register
|
||
; PORTD.PORTD7 7 Port D Data Register bit 7
|
||
; PORTD.PORTD6 6 Port D Data Register bit 6
|
||
; PORTD.PORTD5 5 Port D Data Register bit 5
|
||
; PORTD.PORTD4 4 Port D Data Register bit 4
|
||
; PORTD.PORTD3 3 Port D Data Register bit 3
|
||
; PORTD.PORTD2 2 Port D Data Register bit 2
|
||
; PORTD.PORTD1 1 Port D Data Register bit 1
|
||
; PORTD.PORTD0 0 Port D Data Register bit 0
|
||
; PINC 0x0033 Port C Input Pins Address
|
||
; PINC.PINC7 7
|
||
; PINC.PINC6 6
|
||
; PINC.PINC5 5
|
||
; PINC.PINC4 4
|
||
; PINC.PINC3 3
|
||
; PINC.PINC2 2
|
||
; PINC.PINC1 1
|
||
; PINC.PINC0 0
|
||
; DDRC 0x0034 Port C Data Direction Register
|
||
; DDRC.DDC7 7 Port C Data Direction Register bit 7
|
||
; DDRC.DDC6 6 Port C Data Direction Register bit 6
|
||
; DDRC.DDC5 5 Port C Data Direction Register bit 5
|
||
; DDRC.DDC4 4 Port C Data Direction Register bit 4
|
||
; DDRC.DDC3 3 Port C Data Direction Register bit 3
|
||
; DDRC.DDC2 2 Port C Data Direction Register bit 2
|
||
; DDRC.DDC1 1 Port C Data Direction Register bit 1
|
||
; DDRC.DDC0 0 Port C Data Direction Register bit 0
|
||
; PORTC 0x0035 Port C Data Register
|
||
; PORTC.PORTC7 7 Port C Data Register bit 7
|
||
; PORTC.PORTC6 6 Port C Data Register bit 6
|
||
; PORTC.PORTC5 5 Port C Data Register bit 5
|
||
; PORTC.PORTC4 4 Port C Data Register bit 4
|
||
; PORTC.PORTC3 3 Port C Data Register bit 3
|
||
; PORTC.PORTC2 2 Port C Data Register bit 2
|
||
; PORTC.PORTC1 1 Port C Data Register bit 1
|
||
; PORTC.PORTC0 0 Port C Data Register bit 0
|
||
; PINB 0x0036 Port B Input Pins Address
|
||
; PINB.PINB7 7
|
||
; PINB.PINB6 6
|
||
; PINB.PINB5 5
|
||
; PINB.PINB4 4
|
||
; PINB.PINB3 3
|
||
; PINB.PINB2 2
|
||
; PINB.PINB1 1
|
||
; PINB.PINB0 0
|
||
; DDRB 0x0037 Port B Data Direction Register
|
||
; DDRB.DDB7 7 Port B Data Direction Register bit 7
|
||
; DDRB.DDB6 6 Port B Data Direction Register bit 6
|
||
; DDRB.DDB5 5 Port B Data Direction Register bit 5
|
||
; DDRB.DDB4 4 Port B Data Direction Register bit 4
|
||
; DDRB.DDB3 3 Port B Data Direction Register bit 3
|
||
; DDRB.DDB2 2 Port B Data Direction Register bit 2
|
||
; DDRB.DDB1 1 Port B Data Direction Register bit 1
|
||
; DDRB.DDB0 0 Port B Data Direction Register bit 0
|
||
; PORTB 0x0038 Port B Data Register
|
||
; PORTB.PORTB7 7 Port B Data Register bit 7
|
||
; PORTB.PORTB6 6 Port B Data Register bit 6
|
||
; PORTB.PORTB5 5 Port B Data Register bit 5
|
||
; PORTB.PORTB4 4 Port B Data Register bit 4
|
||
; PORTB.PORTB3 3 Port B Data Register bit 3
|
||
; PORTB.PORTB2 2 Port B Data Register bit 2
|
||
; PORTB.PORTB1 1 Port B Data Register bit 1
|
||
; PORTB.PORTB0 0 Port B Data Register bit 0
|
||
; PINA 0x0039 Port A Input Pins Address
|
||
; PINA.PINA7 7
|
||
; PINA.PINA6 6
|
||
; PINA.PINA5 5
|
||
; PINA.PINA4 4
|
||
; PINA.PINA3 3
|
||
; PINA.PINA2 2
|
||
; PINA.PINA1 1
|
||
; PINA.PINA0 0
|
||
; DDRA 0x003A Port A Data Direction Register
|
||
; DDRA.DDA7 7 Port A Data Direction Register bit 7
|
||
; DDRA.DDA6 6 Port A Data Direction Register bit 6
|
||
; DDRA.DDA5 5 Port A Data Direction Register bit 5
|
||
; DDRA.DDA4 4 Port A Data Direction Register bit 4
|
||
; DDRA.DDA3 3 Port A Data Direction Register bit 3
|
||
; DDRA.DDA2 2 Port A Data Direction Register bit 2
|
||
; DDRA.DDA1 1 Port A Data Direction Register bit 1
|
||
; DDRA.DDA0 0 Port A Data Direction Register bit 0
|
||
; PORTA 0x003B Port A Data Register
|
||
; PORTA.PORTA7 7 Port A Data Register bit 7
|
||
; PORTA.PORTA6 6 Port A Data Register bit 6
|
||
; PORTA.PORTA5 5 Port A Data Register bit 5
|
||
; PORTA.PORTA4 4 Port A Data Register bit 4
|
||
; PORTA.PORTA3 3 Port A Data Register bit 3
|
||
; PORTA.PORTA2 2 Port A Data Register bit 2
|
||
; PORTA.PORTA1 1 Port A Data Register bit 1
|
||
; PORTA.PORTA0 0 Port A Data Register bit 0
|
||
; EECR 0x003C The EEPROM Control Register
|
||
; EECR.EERIE 3 EEPROM Ready Interrupt Enable
|
||
; EECR.EEMWE 2 EEPROM Master Write Enable
|
||
; EECR.EEWE 1 EEPROM Write Enable
|
||
; EECR.EERE 0 EEPROM Read Enable
|
||
; EEDR 0x003D EEPROM Data Register
|
||
; EEARL 0x003E EEPROM Address Register Low
|
||
; EEARL.EEAR7 7 EEPROM Address 7
|
||
; EEARL.EEAR6 6 EEPROM Address 6
|
||
; EEARL.EEAR5 5 EEPROM Address 5
|
||
; EEARL.EEAR4 4 EEPROM Address 4
|
||
; EEARL.EEAR3 3 EEPROM Address 3
|
||
; EEARL.EEAR2 2 EEPROM Address 2
|
||
; EEARL.EEAR1 1 EEPROM Address 1
|
||
; EEARL.EEAR0 0 EEPROM Address 0
|
||
; EEARH 0x003F EEPROM Address Register High
|
||
; EEARH.EEAR8 8 EEPROM Address 8
|
||
; UBRRHI 0x0040 UART Baud Rate Register
|
||
; WDTCR 0x0041 Watchdog Timer Control Register
|
||
; WDTCR.WDTOE 4 Watchdog Turn-off Enable
|
||
; WDTCR.WDE 3 Watchdog Enable
|
||
; WDTCR.WDP2 2 Watchdog Timer Prescaler 2
|
||
; WDTCR.WDP1 1 Watchdog Timer Prescaler 1
|
||
; WDTCR.WDP0 0 Watchdog Timer Prescaler 0
|
||
; ASSR 0x0042 Asynchronous Status Register
|
||
; ASSR.AS2 3 Asynchronous Timer/Counter2
|
||
; ASSR.TCN2UB 2 Timer/Counter2 Update Busy
|
||
; ASSR.OCR2UB 1 Output Compare Register2 Update Busy
|
||
; ASSR.TCR2UB 0 Timer/Counter Control Register2 Update Busy
|
||
; OCR2 0x0043 Timer/Counter2 Output Compare Register
|
||
; TCNT2 0x0044 Timer/Counter2
|
||
; TCCR2 0x0045 Timer/Counter2 Control Register
|
||
; TCCR2.FOC2 7 Force Output Compare
|
||
; TCCR2.PWM2 6 Pulse Width Modulator Enable
|
||
; TCCR2.COM21 5 Compare Output Mode, bit 1
|
||
; TCCR2.COM20 4 Compare Output Mode, bit 0
|
||
; TCCR2.CTC2 3 Clear Timer/Counter on Compare Match
|
||
; TCCR2.CS22 2 Clock Select Bit 2
|
||
; TCCR2.CS21 1 Clock Select Bit 1
|
||
; TCCR2.CS20 0 Clock Select Bit 0
|
||
; ICR1L 0x0046 Input Capture Register Low Byte
|
||
; ICR1H 0x0047 Input Capture Register High Byte
|
||
; OCR1BL 0x0048 Output Compare Register B Low Byte
|
||
; OCR1BH 0x0049 Output Compare Register B High Byte
|
||
; OCR1AL 0x004A Output Compare Register A Low Byte
|
||
; OCR1AH 0x004B Output Compare Register A High Byte
|
||
; TCNT1L 0x004C Counter Register Low Byte
|
||
; TCNT1H 0x004D Counter Register High Byte
|
||
; TCCR1B 0x004E Timer/Counter1 Control Register B
|
||
; TCCR1B.ICNC1 7 Input Capture1 Noise Canceler (4 CKs)
|
||
; TCCR1B.ICES1 6 Input Capture1 Edge Select
|
||
; TCCR1B.CTC1 3 Clear Timer/Counter1 on Compare Match
|
||
; TCCR1B.CS12 2 Clock Select1, Bit 2
|
||
; TCCR1B.CS11 1 Clock Select1, Bit 1
|
||
; TCCR1B.CS10 0 Clock Select1, Bit 0
|
||
; TCCR1A 0x004F Timer/Counter1 Control Register A
|
||
; TCCR1A.COM1A1 7 Compare Output Mode1A, Bit 1
|
||
; TCCR1A.COM1A0 6 Compare Output Mode1A, Bit 0
|
||
; TCCR1A.COM1B1 5 Compare Output Mode1B, Bit 1
|
||
; TCCR1A.COM1B0 4 Compare Output Mode1B, Bit 0
|
||
; TCCR1A.FOC1A 3 Force Output Compare1A
|
||
; TCCR1A.FOC1B 2 Force Output Compare1B
|
||
; TCCR1A.PWM11 1 Pulse Width Modulator Select Bit 1
|
||
; TCCR1A.PWM10 0 Pulse Width Modulator Select Bit 0
|
||
; SFIOR 0x0050 Special Function I/O Register
|
||
; SFIOR.ACME 3 Analog Comparator Multiplexer Enable
|
||
; SFIOR.PUD 2 Pull-up Disable
|
||
; SFIOR.PSR2 1 Prescaler Reset Timer/Counter2
|
||
; SFIOR.PSR10 0 Prescaler Reset Timer/Counter1 and Timer/Counter0
|
||
; OSCCAL 0x0051 Oscillator Calibration Register
|
||
; OSCCAL.CAL7 7 Oscillator Calibration Value 7
|
||
; OSCCAL.CAL6 6 Oscillator Calibration Value 6
|
||
; OSCCAL.CAL5 5 Oscillator Calibration Value 5
|
||
; OSCCAL.CAL4 4 Oscillator Calibration Value 4
|
||
; OSCCAL.CAL3 3 Oscillator Calibration Value 3
|
||
; OSCCAL.CAL2 2 Oscillator Calibration Value 2
|
||
; OSCCAL.CAL1 1 Oscillator Calibration Value 1
|
||
; OSCCAL.CAL0 0 Oscillator Calibration Value 0
|
||
; TCNT0 0x0052 Timer/Counter 0
|
||
; TCCR0 0x0053 Timer/Counter0 Control Register
|
||
; TCCR0.CS02 2 Clock Select0, Bit 2
|
||
; TCCR0.CS01 1 Clock Select0, Bit 1
|
||
; TCCR0.CS00 0 Clock Select0, Bit 0
|
||
; MCUSR 0x0054 MCU Status Register
|
||
; MCUSR.WDRF 3 Watchdog Reset Flag
|
||
; MCUSR.BORF 2 Brown-out Reset Flag
|
||
; MCUSR.EXTRF 1 External Reset Flag
|
||
; MCUSR.PORF 0 Power-on Reset Flag
|
||
; MCUCR 0x0055 MCU Control Register
|
||
; MCUCR.SE 6 Sleep Enable
|
||
; MCUCR.SM1 5 Sleep Mode Select Bit 1
|
||
; MCUCR.SM0 4 Sleep Mode Select Bit 0
|
||
; MCUCR.ISC11 3 Interrupt Sense Control 1 Bit 1
|
||
; MCUCR.ISC10 2 Interrupt Sense Control 1 Bit 0
|
||
; MCUCR.ISC01 1 Interrupt Sense Control 0 Bit 1
|
||
; MCUCR.ISC00 0 Interrupt Sense Control 0 Bit 0
|
||
; TWCR 0x0056 2-wire Serial Interface Control Register
|
||
; TWCR.TWINT 7 2-wire Serial Interface Interrupt Flag
|
||
; TWCR.TWEA 6 2-wire Serial Interface Enable Acknowledge Flag
|
||
; TWCR.TWSTA 5 2-wire Serial Bus START Condition Flag
|
||
; TWCR.TWSTO 4 2-wire Serial Bus STOP Condition Flag
|
||
; TWCR.TWWC 3 2-wire Serial Bus Write Collision Flag
|
||
; TWCR.TWEN 2 2-wire Serial Interface Enable Bit
|
||
; TWCR.TWIE 0 2-wire Serial Interface Interrupt Enable
|
||
; SPMCR 0x0057 Store Program Memory Control Register
|
||
; SPMCR.ASB 6 Application Section Busy
|
||
; SPMCR.ASRE 4 Application Section Read Enable
|
||
; SPMCR.BLBSET 3 Boot Lock Bit Set
|
||
; SPMCR.PGWRT 2 Page Write
|
||
; SPMCR.PGERS 1 Page Erase
|
||
; SPMCR.SPMEN 0 Store Program Memory Enable
|
||
; TIFR 0x0058 Timer/Counter Interrupt Flag Register
|
||
; TIFR.OCF2 7 Output Compare Flag 2
|
||
; TIFR.TOV2 6 Timer/Counter2 Overflow Flag
|
||
; TIFR.ICF1 5 Input Capture Flag 1
|
||
; TIFR.OCF1A 4 Output Compare Flag 1A
|
||
; TIFR.OCF1B 3 Output Compare Flag 1B
|
||
; TIFR.TOV1 2 Timer/Counter1 Overflow Flag
|
||
; TIFR.TOV0 0 Timer/Counter0 Overflow Flag
|
||
; TIMSK 0x0059 Timer/Counter Interrupt Mask Register
|
||
; TIMSK.OCIE2 7 Timer/Counter2 Output Compare Match Interrupt Enable
|
||
; TIMSK.TOIE2 6 Timer/Counter2 Overflow Interrupt Enable
|
||
; TIMSK.TICIE1 5 Timer/Counter1 Input Capture Interrupt Enable
|
||
; TIMSK.OCIE1A 4 Timer/Counter1 Output CompareA Match Interrupt Enable
|
||
; TIMSK.OCIE1B 3 Timer/Counter1 Output CompareB Match Interrupt Enable
|
||
; TIMSK.TOIE1 2 Timer/Counter1 Overflow Interrupt Enable
|
||
; TIMSK.TOIE0 0 Timer/Counter0 Overflow Interrupt Enable
|
||
; GIFR 0x005A General Interrupt Flag Register
|
||
; GIFR.INTF1 7 External Interrupt Flag1
|
||
; GIFR.INTF0 6 External Interrupt Flag0
|
||
; GIMSK 0x005B General Interrupt Mask Register
|
||
; GIMSK.INT1 7 External Interrupt Request 1 Enable
|
||
; GIMSK.INT0 6 External Interrupt Request 0 Enable
|
||
; RESERVED003C 0x005C RESERVED
|
||
; SPL 0x005D Stack Pointer Low
|
||
; SPL.SP7 7
|
||
; SPL.SP6 6
|
||
; SPL.SP5 5
|
||
; SPL.SP4 4
|
||
; SPL.SP3 3
|
||
; SPL.SP2 2
|
||
; SPL.SP1 1
|
||
; SPL.SP0 0
|
||
; SPH 0x005E Stack Pointer High
|
||
; SPH.SP10 10
|
||
; SPH.SP9 9
|
||
; SPH.SP8 8
|
||
; SREG 0x005F Status Register
|
||
; SREG.I 7 Global Interrupt Enable
|
||
; SREG.T 6 Bit Copy Storage
|
||
; SREG.H 5 Half Carry Flag
|
||
; SREG.S 4 Sign Bit
|
||
; SREG.V 3 Two's Complement Overflow Flag
|
||
; SREG.N 2 Negative Flag
|
||
; SREG.Z 1 Zero Flag
|
||
; SREG.C 0 Carry Flag
|
||
|
||
|
||
.ATmega16_L
|
||
SUBARCH=5
|
||
; doc2466.pdf
|
||
;
|
||
|
||
RAM=1024
|
||
ROM=16384
|
||
EEPROM=512
|
||
|
||
; MEMORY MAP
|
||
area DATA FSR 0x0000:0x0060
|
||
area DATA I_SRAM 0x0060:0x0460 Internal SRAM
|
||
|
||
|
||
; Interrupt and reset vector assignments
|
||
entry __RESET 0x0000 Hardware Pin, Power-on Reset and Watchdog Reset
|
||
entry INT0_ 0x0002 External Interrupt Request 0
|
||
entry INT1_ 0x0004 External Interrupt Request 1
|
||
entry TIMER2_COMP 0x0006 Timer/Counter2 Compare Match
|
||
entry TIMER2_OVF 0x0008 Timer/Counter2 Overflow
|
||
entry TIMER1_CAPT 0x000A Timer/Counter1 Capture Event
|
||
entry TIMER1_COMPA 0x000C Timer/Counter1 Compare Match A
|
||
entry TIMER1_COMPB 0x000E Timer/Counter1 Compare Match B
|
||
entry TIMER1_OVF 0x0010 Timer/Counter1 Overflow
|
||
entry TIMER0_OVF 0x0012 Timer/Counter0 Overflow
|
||
entry SPI_STC 0x0014 Serial Transfer Complete
|
||
entry USART_RXC 0x0016 USART, Rx Complete
|
||
entry USART_UDRE 0x0018 USART Data Register Empty
|
||
entry USART_TXC 0x001A USART, Tx Complete
|
||
entry ADC_ 0x001C ADC Conversion Complete
|
||
entry EE_RDY 0x001E EEPROM Ready
|
||
entry ANA_COMP 0x0020 Analog Comparator
|
||
entry TWI_ 0x0022 Two-wire Serial Interface
|
||
entry INT2 0x0024 External Interrupt Request 2
|
||
entry TIMER0_COMP 0x0026 Timer/Counter0 Compare Match
|
||
entry SPM_RDY 0x0028 Store Program Memory Ready
|
||
|
||
|
||
; INPUT/OUTPUT PORTS
|
||
TWBR 0x0000 TWI Bit Rate Register
|
||
TWBR.TWBR7 7 TWI Bit Rate Register bit 7
|
||
TWBR.TWBR6 6 TWI Bit Rate Register bit 6
|
||
TWBR.TWBR5 5 TWI Bit Rate Register bit 5
|
||
TWBR.TWBR4 4 TWI Bit Rate Register bit 4
|
||
TWBR.TWBR3 3 TWI Bit Rate Register bit 3
|
||
TWBR.TWBR2 2 TWI Bit Rate Register bit 2
|
||
TWBR.TWBR1 1 TWI Bit Rate Register bit 1
|
||
TWBR.TWBR0 0 TWI Bit Rate Register bit 0
|
||
TWSR 0x0001 TWI Status Register
|
||
TWSR.TWS7 7 TWI Status 7
|
||
TWSR.TWS6 6 TWI Status 6
|
||
TWSR.TWS5 5 TWI Status 5
|
||
TWSR.TWS4 4 TWI Status 4
|
||
TWSR.TWS3 3 TWI Status 3
|
||
TWSR.TWS1 1 TWI Status 1
|
||
TWSR.TWS0 0 TWI Status 0
|
||
TWAR 0x0002 TWI (Slave) Address Register
|
||
TWAR.TWA6 7 TWI (Slave) Address Register bit 6
|
||
TWAR.TWA5 6 TWI (Slave) Address Register bit 5
|
||
TWAR.TWA4 5 TWI (Slave) Address Register bit 4
|
||
TWAR.TWA3 4 TWI (Slave) Address Register bit 3
|
||
TWAR.TWA2 3 TWI (Slave) Address Register bit 2
|
||
TWAR.TWA1 2 TWI (Slave) Address Register bit 1
|
||
TWAR.TWA0 1 TWI (Slave) Address Register bit 0
|
||
TWAR.TWGCE 0 TWI General Call Recognition Enable Bit
|
||
TWDR 0x0003 TWI Data Register
|
||
TWDR.TWD7 7 TWI Data Register bit 7
|
||
TWDR.TWD6 6 TWI Data Register bit 6
|
||
TWDR.TWD5 5 TWI Data Register bit 5
|
||
TWDR.TWD4 4 TWI Data Register bit 4
|
||
TWDR.TWD3 3 TWI Data Register bit 3
|
||
TWDR.TWD2 2 TWI Data Register bit 2
|
||
TWDR.TWD1 1 TWI Data Register bit 1
|
||
TWDR.TWD0 0 TWI Data Register bit 0
|
||
ADCL 0x0004 The ADC Data Register Low (ADLAR = 0)
|
||
ADCL.ADC7 7
|
||
ADCL.ADC6 6
|
||
ADCL.ADC5 5
|
||
ADCL.ADC4 4
|
||
ADCL.ADC3 3
|
||
ADCL.ADC2 2
|
||
ADCL.ADC1 1
|
||
ADCL.ADC0 0
|
||
ADCH 0x0005 The ADC Data Register High (ADLAR = 0)
|
||
ADCH.ADC9 9
|
||
ADCH.ADC8 8
|
||
; ADCL 0x0004 The ADC Data Register Low (ADLAR = 1)
|
||
; ADCL.ADC1 7
|
||
; ADCL.ADC0 6
|
||
; ADCH 0x0005 The ADC Data Register High (ADLAR = 1)
|
||
; ADCH.ADC9 7
|
||
; ADCH.ADC8 6
|
||
; ADCH.ADC7 5
|
||
; ADCH.ADC6 4
|
||
; ADCH.ADC5 3
|
||
; ADCH.ADC4 2
|
||
; ADCH.ADC3 1
|
||
; ADCH.ADC2 0
|
||
ADCSRA 0x0006 ADC Control and Status Register A
|
||
ADCSRA.ADEN 7 ADC Enable
|
||
ADCSRA.ADSC 6 ADC Start Conversion
|
||
ADCSRA.ADATE 5 ADC Auto Trigger Enable
|
||
ADCSRA.ADIF 4 ADC Interrupt Flag
|
||
ADCSRA.ADIE 3 ADC Interrupt Enable
|
||
ADCSRA.ADPS2 2 ADC Prescaler Select Bit 2
|
||
ADCSRA.ADPS1 1 ADC Prescaler Select Bit 1
|
||
ADCSRA.ADPS0 0 ADC Prescaler Select Bit 0
|
||
ADMUX 0x0007 ADC Multiplexer Selection Register
|
||
ADMUX.REFS1 7 Reference Selection Bit 1
|
||
ADMUX.REFS0 6 Reference Selection Bit 0
|
||
ADMUX.ADLAR 5 ADC Left Adjust Result
|
||
ADMUX.MUX4 4 Analog Channel and Gain Selection Bit 4
|
||
ADMUX.MUX3 3 Analog Channel and Gain Selection Bit 3
|
||
ADMUX.MUX2 2 Analog Channel and Gain Selection Bit 2
|
||
ADMUX.MUX1 1 Analog Channel and Gain Selection Bit 1
|
||
ADMUX.MUX0 0 Analog Channel and Gain Selection Bit 0
|
||
ACSR 0x0008 Analog Comparator Control and Status Register
|
||
ACSR.ACD 7 Analog Comparator Disable
|
||
ACSR.ACBG 6 Analog Comparator Bandgap Select
|
||
ACSR.ACO 5 Analog Comparator Output
|
||
ACSR.ACI 4 Analog Comparator Interrupt Flag
|
||
ACSR.ACIE 3 Analog Comparator Interrupt Enable
|
||
ACSR.ACIC 2 Analog Comparator Input Capture Enable
|
||
ACSR.ACIS1 1 Analog Comparator Interrupt Mode Select 1
|
||
ACSR.ACIS0 0 Analog Comparator Interrupt Mode Select 0
|
||
UBRRL 0x0009 USART Baud Rate Register Low Byte
|
||
UCSRB 0x000A USART Control and Status Register B
|
||
UCSRB.RXCIE 7 RX Complete Interrupt Enable
|
||
UCSRB.TXCIE 6 TX Complete Interrupt Enable
|
||
UCSRB.UDRIE 5 USART Data Register Empty Interrupt Enable
|
||
UCSRB.RXEN 4 Receiver Enable
|
||
UCSRB.TXEN 3 Transmitter Enable
|
||
UCSRB.UCSZ2 2 Character Size
|
||
UCSRB.RXB8 1 Receive Data Bit 8
|
||
UCSRB.TXB8 0 Transmit Data Bit 8
|
||
UCSRA 0x000B USART Control and Status Register A
|
||
UCSRA.RXC 7 USART Receive Complete
|
||
UCSRA.TXC 6 USART Transmit Complete
|
||
UCSRA.UDRE 5 USART Data Register Empty
|
||
UCSRA.FE 4 Frame Error
|
||
UCSRA.DOR 3 Data OverRun
|
||
UCSRA.PE 2 Parity Error
|
||
UCSRA.U2X 1 Double the USART Transmission Speed
|
||
UCSRA.MPCM 0 Multi-processor Communication Mode
|
||
UDR 0x000C USART I/O Data Register
|
||
SPCR 0x000D SPI Control Register
|
||
SPCR.SPIE 7 SPI Interrupt Enable
|
||
SPCR.SPE 6 SPI Enable
|
||
SPCR.DORD 5 Data Order
|
||
SPCR.MSTR 4 Master/Slave Select
|
||
SPCR.CPOL 3 Clock Polarity
|
||
SPCR.CPHA 2 Clock Phase
|
||
SPCR.SPR1 1 SPI Clock Rate Select 1
|
||
SPCR.SPR0 0 SPI Clock Rate Select 0
|
||
SPSR 0x000E SPI Status Register
|
||
SPSR.SPIF 7 SPI Interrupt Flag
|
||
SPSR.WCOL 6 Write COLlision flag
|
||
SPSR.SPI2X 0 Double SPI Speed Bit
|
||
SPDR 0x000F SPI Data Register
|
||
PIND 0x0010 Port D Input Pins Address
|
||
PIND.PIND7 7
|
||
PIND.PIND6 6
|
||
PIND.PIND5 5
|
||
PIND.PIND4 4
|
||
PIND.PIND3 3
|
||
PIND.PIND2 2
|
||
PIND.PIND1 1
|
||
PIND.PIND0 0
|
||
DDRD 0x0011 Port D Data Direction Register
|
||
DDRD.DDD7 7 Port D Data Direction Register bit 7
|
||
DDRD.DDD6 6 Port D Data Direction Register bit 6
|
||
DDRD.DDD5 5 Port D Data Direction Register bit 5
|
||
DDRD.DDD4 4 Port D Data Direction Register bit 4
|
||
DDRD.DDD3 3 Port D Data Direction Register bit 3
|
||
DDRD.DDD2 2 Port D Data Direction Register bit 2
|
||
DDRD.DDD1 1 Port D Data Direction Register bit 1
|
||
DDRD.DDD0 0 Port D Data Direction Register bit 0
|
||
PORTD 0x0012 Port D Data Register
|
||
PORTD.PORTD7 7 Port D Data Register bit 7
|
||
PORTD.PORTD6 6 Port D Data Register bit 6
|
||
PORTD.PORTD5 5 Port D Data Register bit 5
|
||
PORTD.PORTD4 4 Port D Data Register bit 4
|
||
PORTD.PORTD3 3 Port D Data Register bit 3
|
||
PORTD.PORTD2 2 Port D Data Register bit 2
|
||
PORTD.PORTD1 1 Port D Data Register bit 1
|
||
PORTD.PORTD0 0 Port D Data Register bit 0
|
||
PINC 0x0013 Port C Input Pins Address
|
||
PINC.PINC7 7
|
||
PINC.PINC6 6
|
||
PINC.PINC5 5
|
||
PINC.PINC4 4
|
||
PINC.PINC3 3
|
||
PINC.PINC2 2
|
||
PINC.PINC1 1
|
||
PINC.PINC0 0
|
||
DDRC 0x0014 Port C Data Direction Register
|
||
DDRC.DDC7 7 Port C Data Direction Register bit 7
|
||
DDRC.DDC6 6 Port C Data Direction Register bit 6
|
||
DDRC.DDC5 5 Port C Data Direction Register bit 5
|
||
DDRC.DDC4 4 Port C Data Direction Register bit 4
|
||
DDRC.DDC3 3 Port C Data Direction Register bit 3
|
||
DDRC.DDC2 2 Port C Data Direction Register bit 2
|
||
DDRC.DDC1 1 Port C Data Direction Register bit 1
|
||
DDRC.DDC0 0 Port C Data Direction Register bit 0
|
||
PORTC 0x0015 Port C Data Register
|
||
PORTC.PORTC7 7 Port C Data Register bit 7
|
||
PORTC.PORTC6 6 Port C Data Register bit 6
|
||
PORTC.PORTC5 5 Port C Data Register bit 5
|
||
PORTC.PORTC4 4 Port C Data Register bit 4
|
||
PORTC.PORTC3 3 Port C Data Register bit 3
|
||
PORTC.PORTC2 2 Port C Data Register bit 2
|
||
PORTC.PORTC1 1 Port C Data Register bit 1
|
||
PORTC.PORTC0 0 Port C Data Register bit 0
|
||
PINB 0x0016 Port B Input Pins Address
|
||
PINB.PINB7 7
|
||
PINB.PINB6 6
|
||
PINB.PINB5 5
|
||
PINB.PINB4 4
|
||
PINB.PINB3 3
|
||
PINB.PINB2 2
|
||
PINB.PINB1 1
|
||
PINB.PINB0 0
|
||
DDRB 0x0017 Port B Data Direction Register
|
||
DDRB.DDB7 7 Port B Data Direction Register bit 7
|
||
DDRB.DDB6 6 Port B Data Direction Register bit 6
|
||
DDRB.DDB5 5 Port B Data Direction Register bit 5
|
||
DDRB.DDB4 4 Port B Data Direction Register bit 4
|
||
DDRB.DDB3 3 Port B Data Direction Register bit 3
|
||
DDRB.DDB2 2 Port B Data Direction Register bit 2
|
||
DDRB.DDB1 1 Port B Data Direction Register bit 1
|
||
DDRB.DDB0 0 Port B Data Direction Register bit 0
|
||
PORTB 0x0018 Port B Data Register
|
||
PORTB.PORTB7 7 Port B Data Register bit 7
|
||
PORTB.PORTB6 6 Port B Data Register bit 6
|
||
PORTB.PORTB5 5 Port B Data Register bit 5
|
||
PORTB.PORTB4 4 Port B Data Register bit 4
|
||
PORTB.PORTB3 3 Port B Data Register bit 3
|
||
PORTB.PORTB2 2 Port B Data Register bit 2
|
||
PORTB.PORTB1 1 Port B Data Register bit 1
|
||
PORTB.PORTB0 0 Port B Data Register bit 0
|
||
PINA 0x0019 Port A Input Pins Address
|
||
PINA.PINA7 7
|
||
PINA.PINA6 6
|
||
PINA.PINA5 5
|
||
PINA.PINA4 4
|
||
PINA.PINA3 3
|
||
PINA.PINA2 2
|
||
PINA.PINA1 1
|
||
PINA.PINA0 0
|
||
DDRA 0x001A Port A Data Direction Register
|
||
DDRA.DDA7 7 Port A Data Direction Register bit 7
|
||
DDRA.DDA6 6 Port A Data Direction Register bit 6
|
||
DDRA.DDA5 5 Port A Data Direction Register bit 5
|
||
DDRA.DDA4 4 Port A Data Direction Register bit 4
|
||
DDRA.DDA3 3 Port A Data Direction Register bit 3
|
||
DDRA.DDA2 2 Port A Data Direction Register bit 2
|
||
DDRA.DDA1 1 Port A Data Direction Register bit 1
|
||
DDRA.DDA0 0 Port A Data Direction Register bit 0
|
||
PORTA 0x001B Port A Data Register
|
||
PORTA.PORTA7 7 Port A Data Register bit 7
|
||
PORTA.PORTA6 6 Port A Data Register bit 6
|
||
PORTA.PORTA5 5 Port A Data Register bit 5
|
||
PORTA.PORTA4 4 Port A Data Register bit 4
|
||
PORTA.PORTA3 3 Port A Data Register bit 3
|
||
PORTA.PORTA2 2 Port A Data Register bit 2
|
||
PORTA.PORTA1 1 Port A Data Register bit 1
|
||
PORTA.PORTA0 0 Port A Data Register bit 0
|
||
EECR 0x001C EEPROM Control Register
|
||
EECR.EERIE 3 EEPROM Ready Interrupt Enable
|
||
EECR.EEMWE 2 EEPROM Master Write Enable
|
||
EECR.EEWE 1 EEPROM Write Enable
|
||
EECR.EERE 0 EEPROM Read Enable
|
||
EEDR 0x001D EEPROM Data Register
|
||
EEARL 0x001E EEPROM Address Register Low
|
||
EEARL.EEAR7 7 EEPROM Addres 7
|
||
EEARL.EEAR6 6 EEPROM Addres 6
|
||
EEARL.EEAR5 5 EEPROM Addres 5
|
||
EEARL.EEAR4 4 EEPROM Addres 4
|
||
EEARL.EEAR3 3 EEPROM Addres 3
|
||
EEARL.EEAR2 2 EEPROM Addres 2
|
||
EEARL.EEAR1 1 EEPROM Addres 1
|
||
EEARL.EEAR0 0 EEPROM Addres 0
|
||
EEARH 0x001F EEPROM Address Register High
|
||
EEARH.EEAR8 8 EEPROM Addres 8
|
||
UCSRC 0x0020 USART Control and Status Register C (page 155)
|
||
UCSRC.URSEL 7 Register Select
|
||
UCSRC.UMSEL 6 USART Mode Select
|
||
UCSRC.UPM1 5 Parity Mode 1
|
||
UCSRC.UPM0 4 Parity Mode 0
|
||
UCSRC.USBS 3 Stop Bit Select
|
||
UCSRC.UCSZ1 2 Character Size 1
|
||
UCSRC.UCSZ0 1 Character Size 0
|
||
UCSRC.UCPOL 0 Clock Polarity
|
||
; UBRRH 0x0020 USART Baud Rate Register High (page 155)
|
||
; UBRRH.URSEL 15 Register Select
|
||
; UBRRH.UBRR11 11 USART Baud Rate Register bit 11
|
||
; UBRRH.UBRR10 10 USART Baud Rate Register bit 10
|
||
; UBRRH.UBRR9 9 USART Baud Rate Register bit 9
|
||
; UBRRH.UBRR8 8 USART Baud Rate Register bit 8
|
||
WDTCR 0x0021 Watchdog Timer Control Register
|
||
WDTCR.WDTOE 4 Watchdog Turn-off Enable
|
||
WDTCR.WDE 3 Watchdog Enable
|
||
WDTCR.WDP2 2 Watchdog Timer Prescaler 2
|
||
WDTCR.WDP1 1 Watchdog Timer Prescaler 1
|
||
WDTCR.WDP0 0 Watchdog Timer Prescaler 0
|
||
ASSR 0x0022 Asynchronous Status Register
|
||
ASSR.AS2 3 Asynchronous Timer/Counter2
|
||
ASSR.TCN2UB 2 Timer/Counter2 Update Busy
|
||
ASSR.OCR2UB 1 Output Compare Register2 Update Busy
|
||
ASSR.TCR2UB 0 Timer/Counter Control Register2 Update Busy
|
||
OCR2 0x0023 Output Compare Register
|
||
TCNT2 0x0024 Timer/Counter Register
|
||
TCCR2 0x0025 Timer/Counter Control Register
|
||
TCCR2.FOC2 7 Force Output Compare
|
||
TCCR2.WGM20 6 Waveform Generation Mode 0
|
||
TCCR2.COM21 5 Waveform Generation Mode 1
|
||
TCCR2.COM20 4 Compare Match Output Mode 0
|
||
TCCR2.WGM21 3 Compare Match Output Mode 1
|
||
TCCR2.CS22 2 Clock Select 2
|
||
TCCR2.CS21 1 Clock Select 1
|
||
TCCR2.CS20 0 Clock Select 0
|
||
ICR1L 0x0026 Input Capture Register Low Byte
|
||
ICR1H 0x0027 Input Capture Register High Byte
|
||
OCR1BL 0x0028 Output Compare Register B Low Byte
|
||
OCR1BH 0x0029 Output Compare Register B High Byte
|
||
OCR1AL 0x002A Output Compare Register A Low Byte
|
||
OCR1AH 0x002B Output Compare Register A High Byte
|
||
TCNT1L 0x002C Counter Register Low Byte
|
||
TCNT1H 0x002D Counter Register High Byte
|
||
TCCR1B 0x002E Timer/Counter1 Control Register B
|
||
TCCR1B.ICNC1 7 Input Capture Noise Canceler
|
||
TCCR1B.ICES1 6 Input Capture Edge Select
|
||
TCCR1B.WGM13 4 Waveform Generation Mode 3
|
||
TCCR1B.WGM12 3 Waveform Generation Mode 2
|
||
TCCR1B.CS12 2 Clock Select 2
|
||
TCCR1B.CS11 1 Clock Select 1
|
||
TCCR1B.CS10 0 Clock Select 0
|
||
TCCR1A 0x002F Timer/Counter1 Control Register A
|
||
TCCR1A.COM1A1 7 Compare Output Mode for Channel A 1
|
||
TCCR1A.COM1A0 6 Compare Output Mode for Channel A 0
|
||
TCCR1A.COM1B1 5 Compare Output Mode for Channel B 1
|
||
TCCR1A.COM1B0 4 Compare Output Mode for Channel B 0
|
||
TCCR1A.FOC1A 3 Force Output Compare for Channel A
|
||
TCCR1A.FOC1B 2 Force Output Compare for Channel B
|
||
TCCR1A.WGM11 1 Waveform Generation Mode 1
|
||
TCCR1A.WGM10 0 Waveform Generation Mode 0
|
||
SFIOR 0x0030 Special Function I/O Register
|
||
SFIOR.ADTS2 7 ADC Auto Trigger Source 2
|
||
SFIOR.ADTS1 6 ADC Auto Trigger Source 1
|
||
SFIOR.ADTS0 5 ADC Auto Trigger Source 0
|
||
SFIOR.ADHSM 4 ADC High Speed Mode
|
||
SFIOR.ACME 3 Analog Comparator Multiplexer Enable
|
||
SFIOR.PUD 2 Pull-up disable
|
||
SFIOR.PSR2 1 Prescaler Reset Timer/Counter2
|
||
SFIOR.PSR10 0 Prescaler Reset Timer/Counter1 and Timer/Counter0
|
||
OCDR 0x0031 On-chip Debug Register
|
||
; OSCCAL 0x0031 Oscillator Calibration Register
|
||
; OSCCAL.CAL7 7 Oscillator Calibration Value 7
|
||
; OSCCAL.CAL6 6 Oscillator Calibration Value 6
|
||
; OSCCAL.CAL5 5 Oscillator Calibration Value 5
|
||
; OSCCAL.CAL4 4 Oscillator Calibration Value 4
|
||
; OSCCAL.CAL3 3 Oscillator Calibration Value 3
|
||
; OSCCAL.CAL2 2 Oscillator Calibration Value 2
|
||
; OSCCAL.CAL1 1 Oscillator Calibration Value 1
|
||
; OSCCAL.CAL0 0 Oscillator Calibration Value 0
|
||
TCNT0 0x0032 Timer/Counter Register
|
||
TCCR0 0x0033 Timer/Counter Control Register
|
||
TCCR0.FOC0 7 Force Output Compare
|
||
TCCR0.WGM00 6 Waveform Generation Mode 0
|
||
TCCR0.COM01 5 Compare Match Output Mode 1
|
||
TCCR0.COM00 4 Compare Match Output Mode 0
|
||
TCCR0.WGM01 3 Waveform Generation Mode 1
|
||
TCCR0.CS02 2 Clock Select 2
|
||
TCCR0.CS01 1 Clock Select 1
|
||
TCCR0.CS00 0 Clock Select 0
|
||
MCUCSR 0x0034 MCU Control and Status Register
|
||
MCUCSR.JTD 7 JTAG Interface Disable
|
||
MCUCSR.ISC2 6 Interrupt Sense Control 2
|
||
MCUCSR.JTRF 4 JTAG Reset Flag
|
||
MCUCSR.WDRF 3 Watchdog Reset Flag
|
||
MCUCSR.BORF 2 Brown-out Reset Flag
|
||
MCUCSR.EXTRF 1 External Reset Flag
|
||
MCUCSR.PORF 0 Power-on Reset Flag
|
||
MCUCR 0x0035 MCU Control Register
|
||
MCUCR.SM2 7 Sleep Mode Select Bit 2
|
||
MCUCR.SE 6 Sleep Enable
|
||
MCUCR.SM1 5 Sleep Mode Select Bit 1
|
||
MCUCR.SM0 4 Sleep Mode Select Bit 0
|
||
MCUCR.ISC11 3 Interrupt Sense Control 1 Bit 1
|
||
MCUCR.ISC10 2 Interrupt Sense Control 1 Bit 0
|
||
MCUCR.ISC01 1 Interrupt Sense Control 0 Bit 1
|
||
MCUCR.ISC00 0 Interrupt Sense Control 0 Bit 0
|
||
TWCR 0x0036 TWI Control Register
|
||
TWCR.TWINT 7 TWI Interrupt Flag
|
||
TWCR.TWEA 6 TWI Enable Acknowledge Bit
|
||
TWCR.TWSTA 5 TWI START Condition Bit
|
||
TWCR.TWSTO 4 TWI STOP Condition Bit
|
||
TWCR.TWWC 3 TWI Write Collision Flag
|
||
TWCR.TWEN 2 TWI Enable Bit
|
||
TWCR.TWIE 0 TWI Interrupt Enable
|
||
SPMCR 0x0037 Store Program Memory Control Register
|
||
SPMCR.SPMIE 7 SPM Interrupt Enable
|
||
SPMCR.RWWSB 6 Read-While-Write Section Busy
|
||
SPMCR.RWWSRE 4 Read-While-Write Section Read Enable
|
||
SPMCR.BLBSET 3 Boot Lock Bit Set
|
||
SPMCR.PGWRT 2 Page Write
|
||
SPMCR.PGERS 1 Page Erase
|
||
SPMCR.SPMEN 0 Store Program Memory Enable
|
||
TIFR 0x0038 Timer/Counter Interrupt Flag Register
|
||
TIFR.OCF2 7 Output Compare Flag 2
|
||
TIFR.TOV2 6 Timer/Counter0 Overflow Flag 2
|
||
TIFR.ICF1 5 Timer/Counter1, Input Capture Flag
|
||
TIFR.OCF1A 4 Timer/Counter1, Output Compare A Match Flag
|
||
TIFR.OCF1B 3 Timer/Counter1, Output Compare B Match Flag
|
||
TIFR.TOV1 2 Timer/Counter0 Overflow Flag 1
|
||
TIFR.OCF0 1 Output Compare Flag 0
|
||
TIFR.TOV0 0 Timer/Counter0 Overflow Flag 0
|
||
TIMSK 0x0039 Timer/Counter Interrupt Mask Register
|
||
TIMSK.OCIE2 7 Timer/Counter2 Output Compare Match Interrupt Enable
|
||
TIMSK.TOIE2 6 Timer/Counter2 Overflow Interrupt Enable
|
||
TIMSK.TICIE1 5 Timer/Counter1, Input Capture Interrupt Enable
|
||
TIMSK.OCIE1A 4 Timer/Counter1, Output Compare A Match Interrupt Enable
|
||
TIMSK.OCIE1B 3 Timer/Counter1, Output Compare B Match Interrupt Enable
|
||
TIMSK.TOIE1 2 Timer/Counter1, Overflow Interrupt Enable
|
||
TIMSK.OCIE0 1 Timer/Counter0 Output Compare Match Interrupt Enable
|
||
TIMSK.TOIE0 0 Timer/Counter0 Overflow Interrupt Enable
|
||
GIFR 0x003A General Interrupt Flag Register
|
||
GIFR.INTF1 7 External Interrupt Flag 1
|
||
GIFR.INTF0 6 External Interrupt Flag 0
|
||
GIFR.INTF2 5 External Interrupt Flag 2
|
||
GICR 0x003B General Interrupt Control Register
|
||
GICR.INT1 7 External Interrupt Request 1 Enable
|
||
GICR.INT0 6 External Interrupt Request 0 Enable
|
||
GICR.INT2 5 External Interrupt Request 2 Enable
|
||
GICR.IVSEL 1 Interrupt Vector Select
|
||
GICR.IVCE 0 Interrupt Vector Change Enable
|
||
OCR0 0x003C Output Compare Register
|
||
SPL 0x003D Stack Pointer Low
|
||
SPL.SP7 7
|
||
SPL.SP6 6
|
||
SPL.SP5 5
|
||
SPL.SP4 4
|
||
SPL.SP3 3
|
||
SPL.SP2 2
|
||
SPL.SP1 1
|
||
SPL.SP0 0
|
||
SPH 0x003E Stack Pointer High
|
||
SPH.SP15 15
|
||
SPH.SP14 14
|
||
SPH.SP13 13
|
||
SPH.SP12 12
|
||
SPH.SP11 11
|
||
SPH.SP10 10
|
||
SPH.SP9 9
|
||
SPH.SP8 8
|
||
SREG 0x003F Status Register
|
||
SREG.I 7 Global Interrupt Enable
|
||
SREG.T 6 Bit Copy Storage
|
||
SREG.H 5 Half Carry Flag
|
||
SREG.S 4 Sign Bit
|
||
SREG.V 3 Two's Complement Overflow Flag
|
||
SREG.N 2 Negative Flag
|
||
SREG.Z 1 Zero Flag
|
||
SREG.C 0 CarryFlag
|
||
|
||
; TWBR 0x0020 TWI Bit Rate Register
|
||
; TWBR.TWBR7 7 TWI Bit Rate Register bit 7
|
||
; TWBR.TWBR6 6 TWI Bit Rate Register bit 6
|
||
; TWBR.TWBR5 5 TWI Bit Rate Register bit 5
|
||
; TWBR.TWBR4 4 TWI Bit Rate Register bit 4
|
||
; TWBR.TWBR3 3 TWI Bit Rate Register bit 3
|
||
; TWBR.TWBR2 2 TWI Bit Rate Register bit 2
|
||
; TWBR.TWBR1 1 TWI Bit Rate Register bit 1
|
||
; TWBR.TWBR0 0 TWI Bit Rate Register bit 0
|
||
; TWSR 0x0021 TWI Status Register
|
||
; TWSR.TWS7 7 TWI Status 7
|
||
; TWSR.TWS6 6 TWI Status 6
|
||
; TWSR.TWS5 5 TWI Status 5
|
||
; TWSR.TWS4 4 TWI Status 4
|
||
; TWSR.TWS3 3 TWI Status 3
|
||
; TWSR.TWS1 1 TWI Status 1
|
||
; TWSR.TWS0 0 TWI Status 0
|
||
; TWAR 0x0022 TWI (Slave) Address Register
|
||
; TWAR.TWA6 7 TWI (Slave) Address Register bit 6
|
||
; TWAR.TWA5 6 TWI (Slave) Address Register bit 5
|
||
; TWAR.TWA4 5 TWI (Slave) Address Register bit 4
|
||
; TWAR.TWA3 4 TWI (Slave) Address Register bit 3
|
||
; TWAR.TWA2 3 TWI (Slave) Address Register bit 2
|
||
; TWAR.TWA1 2 TWI (Slave) Address Register bit 1
|
||
; TWAR.TWA0 1 TWI (Slave) Address Register bit 0
|
||
; TWAR.TWGCE 0 TWI General Call Recognition Enable Bit
|
||
; TWDR 0x0023 TWI Data Register
|
||
; TWDR.TWD7 7 TWI Data Register bit 7
|
||
; TWDR.TWD6 6 TWI Data Register bit 6
|
||
; TWDR.TWD5 5 TWI Data Register bit 5
|
||
; TWDR.TWD4 4 TWI Data Register bit 4
|
||
; TWDR.TWD3 3 TWI Data Register bit 3
|
||
; TWDR.TWD2 2 TWI Data Register bit 2
|
||
; TWDR.TWD1 1 TWI Data Register bit 1
|
||
; TWDR.TWD0 0 TWI Data Register bit 0
|
||
; ADCL 0x0024 The ADC Data Register Low (ADLAR = 0)
|
||
; ADCL.ADC7 7
|
||
; ADCL.ADC6 6
|
||
; ADCL.ADC5 5
|
||
; ADCL.ADC4 4
|
||
; ADCL.ADC3 3
|
||
; ADCL.ADC2 2
|
||
; ADCL.ADC1 1
|
||
; ADCL.ADC0 0
|
||
; ADCH 0x0025 The ADC Data Register High (ADLAR = 0)
|
||
; ADCH.ADC9 9
|
||
; ADCH.ADC8 8
|
||
; ; ADCL 0x0024 The ADC Data Register Low (ADLAR = 1)
|
||
; ; ADCL.ADC1 7
|
||
; ; ADCL.ADC0 6
|
||
; ; ADCH 0x0025 The ADC Data Register High (ADLAR = 1)
|
||
; ; ADCH.ADC9 7
|
||
; ; ADCH.ADC8 6
|
||
; ; ADCH.ADC7 5
|
||
; ; ADCH.ADC6 4
|
||
; ; ADCH.ADC5 3
|
||
; ; ADCH.ADC4 2
|
||
; ; ADCH.ADC3 1
|
||
; ; ADCH.ADC2 0
|
||
; ADCSRA 0x0026 ADC Control and Status Register A
|
||
; ADCSRA.ADEN 7 ADC Enable
|
||
; ADCSRA.ADSC 6 ADC Start Conversion
|
||
; ADCSRA.ADATE 5 ADC Auto Trigger Enable
|
||
; ADCSRA.ADIF 4 ADC Interrupt Flag
|
||
; ADCSRA.ADIE 3 ADC Interrupt Enable
|
||
; ADCSRA.ADPS2 2 ADC Prescaler Select Bit 2
|
||
; ADCSRA.ADPS1 1 ADC Prescaler Select Bit 1
|
||
; ADCSRA.ADPS0 0 ADC Prescaler Select Bit 0
|
||
; ADMUX 0x0027 ADC Multiplexer Selection Register
|
||
; ADMUX.REFS1 7 Reference Selection Bit 1
|
||
; ADMUX.REFS0 6 Reference Selection Bit 0
|
||
; ADMUX.ADLAR 5 ADC Left Adjust Result
|
||
; ADMUX.MUX4 4 Analog Channel and Gain Selection Bit 4
|
||
; ADMUX.MUX3 3 Analog Channel and Gain Selection Bit 3
|
||
; ADMUX.MUX2 2 Analog Channel and Gain Selection Bit 2
|
||
; ADMUX.MUX1 1 Analog Channel and Gain Selection Bit 1
|
||
; ADMUX.MUX0 0 Analog Channel and Gain Selection Bit 0
|
||
; ACSR 0x0028 Analog Comparator Control and Status Register
|
||
; ACSR.ACD 7 Analog Comparator Disable
|
||
; ACSR.ACBG 6 Analog Comparator Bandgap Select
|
||
; ACSR.ACO 5 Analog Comparator Output
|
||
; ACSR.ACI 4 Analog Comparator Interrupt Flag
|
||
; ACSR.ACIE 3 Analog Comparator Interrupt Enable
|
||
; ACSR.ACIC 2 Analog Comparator Input Capture Enable
|
||
; ACSR.ACIS1 1 Analog Comparator Interrupt Mode Select 1
|
||
; ACSR.ACIS0 0 Analog Comparator Interrupt Mode Select 0
|
||
; UBRRL 0x0029 USART Baud Rate Register Low Byte
|
||
; UCSRB 0x002A USART Control and Status Register B
|
||
; UCSRB.RXCIE 7 RX Complete Interrupt Enable
|
||
; UCSRB.TXCIE 6 TX Complete Interrupt Enable
|
||
; UCSRB.UDRIE 5 USART Data Register Empty Interrupt Enable
|
||
; UCSRB.RXEN 4 Receiver Enable
|
||
; UCSRB.TXEN 3 Transmitter Enable
|
||
; UCSRB.UCSZ2 2 Character Size
|
||
; UCSRB.RXB8 1 Receive Data Bit 8
|
||
; UCSRB.TXB8 0 Transmit Data Bit 8
|
||
; UCSRA 0x002B USART Control and Status Register A
|
||
; UCSRA.RXC 7 USART Receive Complete
|
||
; UCSRA.TXC 6 USART Transmit Complete
|
||
; UCSRA.UDRE 5 USART Data Register Empty
|
||
; UCSRA.FE 4 Frame Error
|
||
; UCSRA.DOR 3 Data OverRun
|
||
; UCSRA.PE 2 Parity Error
|
||
; UCSRA.U2X 1 Double the USART Transmission Speed
|
||
; UCSRA.MPCM 0 Multi-processor Communication Mode
|
||
; UDR 0x002C USART I/O Data Register
|
||
; SPCR 0x002D SPI Control Register
|
||
; SPCR.SPIE 7 SPI Interrupt Enable
|
||
; SPCR.SPE 6 SPI Enable
|
||
; SPCR.DORD 5 Data Order
|
||
; SPCR.MSTR 4 Master/Slave Select
|
||
; SPCR.CPOL 3 Clock Polarity
|
||
; SPCR.CPHA 2 Clock Phase
|
||
; SPCR.SPR1 1 SPI Clock Rate Select 1
|
||
; SPCR.SPR0 0 SPI Clock Rate Select 0
|
||
; SPSR 0x002E SPI Status Register
|
||
; SPSR.SPIF 7 SPI Interrupt Flag
|
||
; SPSR.WCOL 6 Write COLlision flag
|
||
; SPSR.SPI2X 0 Double SPI Speed Bit
|
||
; SPDR 0x002F SPI Data Register
|
||
; PIND 0x0030 Port D Input Pins Address
|
||
; PIND.PIND7 7
|
||
; PIND.PIND6 6
|
||
; PIND.PIND5 5
|
||
; PIND.PIND4 4
|
||
; PIND.PIND3 3
|
||
; PIND.PIND2 2
|
||
; PIND.PIND1 1
|
||
; PIND.PIND0 0
|
||
; DDRD 0x0031 Port D Data Direction Register
|
||
; DDRD.DDD7 7 Port D Data Direction Register bit 7
|
||
; DDRD.DDD6 6 Port D Data Direction Register bit 6
|
||
; DDRD.DDD5 5 Port D Data Direction Register bit 5
|
||
; DDRD.DDD4 4 Port D Data Direction Register bit 4
|
||
; DDRD.DDD3 3 Port D Data Direction Register bit 3
|
||
; DDRD.DDD2 2 Port D Data Direction Register bit 2
|
||
; DDRD.DDD1 1 Port D Data Direction Register bit 1
|
||
; DDRD.DDD0 0 Port D Data Direction Register bit 0
|
||
; PORTD 0x0032 Port D Data Register
|
||
; PORTD.PORTD7 7 Port D Data Register bit 7
|
||
; PORTD.PORTD6 6 Port D Data Register bit 6
|
||
; PORTD.PORTD5 5 Port D Data Register bit 5
|
||
; PORTD.PORTD4 4 Port D Data Register bit 4
|
||
; PORTD.PORTD3 3 Port D Data Register bit 3
|
||
; PORTD.PORTD2 2 Port D Data Register bit 2
|
||
; PORTD.PORTD1 1 Port D Data Register bit 1
|
||
; PORTD.PORTD0 0 Port D Data Register bit 0
|
||
; PINC 0x0033 Port C Input Pins Address
|
||
; PINC.PINC7 7
|
||
; PINC.PINC6 6
|
||
; PINC.PINC5 5
|
||
; PINC.PINC4 4
|
||
; PINC.PINC3 3
|
||
; PINC.PINC2 2
|
||
; PINC.PINC1 1
|
||
; PINC.PINC0 0
|
||
; DDRC 0x0034 Port C Data Direction Register
|
||
; DDRC.DDC7 7 Port C Data Direction Register bit 7
|
||
; DDRC.DDC6 6 Port C Data Direction Register bit 6
|
||
; DDRC.DDC5 5 Port C Data Direction Register bit 5
|
||
; DDRC.DDC4 4 Port C Data Direction Register bit 4
|
||
; DDRC.DDC3 3 Port C Data Direction Register bit 3
|
||
; DDRC.DDC2 2 Port C Data Direction Register bit 2
|
||
; DDRC.DDC1 1 Port C Data Direction Register bit 1
|
||
; DDRC.DDC0 0 Port C Data Direction Register bit 0
|
||
; PORTC 0x0035 Port C Data Register
|
||
; PORTC.PORTC7 7 Port C Data Register bit 7
|
||
; PORTC.PORTC6 6 Port C Data Register bit 6
|
||
; PORTC.PORTC5 5 Port C Data Register bit 5
|
||
; PORTC.PORTC4 4 Port C Data Register bit 4
|
||
; PORTC.PORTC3 3 Port C Data Register bit 3
|
||
; PORTC.PORTC2 2 Port C Data Register bit 2
|
||
; PORTC.PORTC1 1 Port C Data Register bit 1
|
||
; PORTC.PORTC0 0 Port C Data Register bit 0
|
||
; PINB 0x0036 Port B Input Pins Address
|
||
; PINB.PINB7 7
|
||
; PINB.PINB6 6
|
||
; PINB.PINB5 5
|
||
; PINB.PINB4 4
|
||
; PINB.PINB3 3
|
||
; PINB.PINB2 2
|
||
; PINB.PINB1 1
|
||
; PINB.PINB0 0
|
||
; DDRB 0x0037 Port B Data Direction Register
|
||
; DDRB.DDB7 7 Port B Data Direction Register bit 7
|
||
; DDRB.DDB6 6 Port B Data Direction Register bit 6
|
||
; DDRB.DDB5 5 Port B Data Direction Register bit 5
|
||
; DDRB.DDB4 4 Port B Data Direction Register bit 4
|
||
; DDRB.DDB3 3 Port B Data Direction Register bit 3
|
||
; DDRB.DDB2 2 Port B Data Direction Register bit 2
|
||
; DDRB.DDB1 1 Port B Data Direction Register bit 1
|
||
; DDRB.DDB0 0 Port B Data Direction Register bit 0
|
||
; PORTB 0x0038 Port B Data Register
|
||
; PORTB.PORTB7 7 Port B Data Register bit 7
|
||
; PORTB.PORTB6 6 Port B Data Register bit 6
|
||
; PORTB.PORTB5 5 Port B Data Register bit 5
|
||
; PORTB.PORTB4 4 Port B Data Register bit 4
|
||
; PORTB.PORTB3 3 Port B Data Register bit 3
|
||
; PORTB.PORTB2 2 Port B Data Register bit 2
|
||
; PORTB.PORTB1 1 Port B Data Register bit 1
|
||
; PORTB.PORTB0 0 Port B Data Register bit 0
|
||
; PINA 0x0039 Port A Input Pins Address
|
||
; PINA.PINA7 7
|
||
; PINA.PINA6 6
|
||
; PINA.PINA5 5
|
||
; PINA.PINA4 4
|
||
; PINA.PINA3 3
|
||
; PINA.PINA2 2
|
||
; PINA.PINA1 1
|
||
; PINA.PINA0 0
|
||
; DDRA 0x003A Port A Data Direction Register
|
||
; DDRA.DDA7 7 Port A Data Direction Register bit 7
|
||
; DDRA.DDA6 6 Port A Data Direction Register bit 6
|
||
; DDRA.DDA5 5 Port A Data Direction Register bit 5
|
||
; DDRA.DDA4 4 Port A Data Direction Register bit 4
|
||
; DDRA.DDA3 3 Port A Data Direction Register bit 3
|
||
; DDRA.DDA2 2 Port A Data Direction Register bit 2
|
||
; DDRA.DDA1 1 Port A Data Direction Register bit 1
|
||
; DDRA.DDA0 0 Port A Data Direction Register bit 0
|
||
; PORTA 0x003B Port A Data Register
|
||
; PORTA.PORTA7 7 Port A Data Register bit 7
|
||
; PORTA.PORTA6 6 Port A Data Register bit 6
|
||
; PORTA.PORTA5 5 Port A Data Register bit 5
|
||
; PORTA.PORTA4 4 Port A Data Register bit 4
|
||
; PORTA.PORTA3 3 Port A Data Register bit 3
|
||
; PORTA.PORTA2 2 Port A Data Register bit 2
|
||
; PORTA.PORTA1 1 Port A Data Register bit 1
|
||
; PORTA.PORTA0 0 Port A Data Register bit 0
|
||
; EECR 0x003C EEPROM Control Register
|
||
; EECR.EERIE 3 EEPROM Ready Interrupt Enable
|
||
; EECR.EEMWE 2 EEPROM Master Write Enable
|
||
; EECR.EEWE 1 EEPROM Write Enable
|
||
; EECR.EERE 0 EEPROM Read Enable
|
||
; EEDR 0x003D EEPROM Data Register
|
||
; EEARL 0x003E EEPROM Address Register Low
|
||
; EEARL.EEAR7 7 EEPROM Addres 7
|
||
; EEARL.EEAR6 6 EEPROM Addres 6
|
||
; EEARL.EEAR5 5 EEPROM Addres 5
|
||
; EEARL.EEAR4 4 EEPROM Addres 4
|
||
; EEARL.EEAR3 3 EEPROM Addres 3
|
||
; EEARL.EEAR2 2 EEPROM Addres 2
|
||
; EEARL.EEAR1 1 EEPROM Addres 1
|
||
; EEARL.EEAR0 0 EEPROM Addres 0
|
||
; EEARH 0x003F EEPROM Address Register High
|
||
; EEARH.EEAR8 8 EEPROM Addres 8
|
||
; UCSRC 0x0040 USART Control and Status Register C (page 155)
|
||
; UCSRC.URSEL 7 Register Select
|
||
; UCSRC.UMSEL 6 USART Mode Select
|
||
; UCSRC.UPM1 5 Parity Mode 1
|
||
; UCSRC.UPM0 4 Parity Mode 0
|
||
; UCSRC.USBS 3 Stop Bit Select
|
||
; UCSRC.UCSZ1 2 Character Size 1
|
||
; UCSRC.UCSZ0 1 Character Size 0
|
||
; UCSRC.UCPOL 0 Clock Polarity
|
||
; ; UBRRH 0x0040 USART Baud Rate Register High (page 155)
|
||
; ; UBRRH.URSEL 15 Register Select
|
||
; ; UBRRH.UBRR11 11 USART Baud Rate Register bit 11
|
||
; ; UBRRH.UBRR10 10 USART Baud Rate Register bit 10
|
||
; ; UBRRH.UBRR9 9 USART Baud Rate Register bit 9
|
||
; ; UBRRH.UBRR8 8 USART Baud Rate Register bit 8
|
||
; WDTCR 0x0041 Watchdog Timer Control Register
|
||
; WDTCR.WDTOE 4 Watchdog Turn-off Enable
|
||
; WDTCR.WDE 3 Watchdog Enable
|
||
; WDTCR.WDP2 2 Watchdog Timer Prescaler 2
|
||
; WDTCR.WDP1 1 Watchdog Timer Prescaler 1
|
||
; WDTCR.WDP0 0 Watchdog Timer Prescaler 0
|
||
; ASSR 0x0042 Asynchronous Status Register
|
||
; ASSR.AS2 3 Asynchronous Timer/Counter2
|
||
; ASSR.TCN2UB 2 Timer/Counter2 Update Busy
|
||
; ASSR.OCR2UB 1 Output Compare Register2 Update Busy
|
||
; ASSR.TCR2UB 0 Timer/Counter Control Register2 Update Busy
|
||
; OCR2 0x0043 Output Compare Register
|
||
; TCNT2 0x0044 Timer/Counter Register
|
||
; TCCR2 0x0045 Timer/Counter Control Register
|
||
; TCCR2.FOC2 7 Force Output Compare
|
||
; TCCR2.WGM20 6 Waveform Generation Mode 0
|
||
; TCCR2.COM21 5 Waveform Generation Mode 1
|
||
; TCCR2.COM20 4 Compare Match Output Mode 0
|
||
; TCCR2.WGM21 3 Compare Match Output Mode 1
|
||
; TCCR2.CS22 2 Clock Select 2
|
||
; TCCR2.CS21 1 Clock Select 1
|
||
; TCCR2.CS20 0 Clock Select 0
|
||
; ICR1L 0x0046 Input Capture Register Low Byte
|
||
; ICR1H 0x0047 Input Capture Register High Byte
|
||
; OCR1BL 0x0048 Output Compare Register B Low Byte
|
||
; OCR1BH 0x0049 Output Compare Register B High Byte
|
||
; OCR1AL 0x004A Output Compare Register A Low Byte
|
||
; OCR1AH 0x004B Output Compare Register A High Byte
|
||
; TCNT1L 0x004C Counter Register Low Byte
|
||
; TCNT1H 0x004D Counter Register High Byte
|
||
; TCCR1B 0x004E Timer/Counter1 Control Register B
|
||
; TCCR1B.ICNC1 7 Input Capture Noise Canceler
|
||
; TCCR1B.ICES1 6 Input Capture Edge Select
|
||
; TCCR1B.WGM13 4 Waveform Generation Mode 3
|
||
; TCCR1B.WGM12 3 Waveform Generation Mode 2
|
||
; TCCR1B.CS12 2 Clock Select 2
|
||
; TCCR1B.CS11 1 Clock Select 1
|
||
; TCCR1B.CS10 0 Clock Select 0
|
||
; TCCR1A 0x004F Timer/Counter1 Control Register A
|
||
; TCCR1A.COM1A1 7 Compare Output Mode for Channel A 1
|
||
; TCCR1A.COM1A0 6 Compare Output Mode for Channel A 0
|
||
; TCCR1A.COM1B1 5 Compare Output Mode for Channel B 1
|
||
; TCCR1A.COM1B0 4 Compare Output Mode for Channel B 0
|
||
; TCCR1A.FOC1A 3 Force Output Compare for Channel A
|
||
; TCCR1A.FOC1B 2 Force Output Compare for Channel B
|
||
; TCCR1A.WGM11 1 Waveform Generation Mode 1
|
||
; TCCR1A.WGM10 0 Waveform Generation Mode 0
|
||
; SFIOR 0x0050 Special Function I/O Register
|
||
; SFIOR.ADTS2 7 ADC Auto Trigger Source 2
|
||
; SFIOR.ADTS1 6 ADC Auto Trigger Source 1
|
||
; SFIOR.ADTS0 5 ADC Auto Trigger Source 0
|
||
; SFIOR.ADHSM 4 ADC High Speed Mode
|
||
; SFIOR.ACME 3 Analog Comparator Multiplexer Enable
|
||
; SFIOR.PUD 2 Pull-up disable
|
||
; SFIOR.PSR2 1 Prescaler Reset Timer/Counter2
|
||
; SFIOR.PSR10 0 Prescaler Reset Timer/Counter1 and Timer/Counter0
|
||
; OCDR 0x0051 On-chip Debug Register
|
||
; ; OSCCAL 0x0051 Oscillator Calibration Register
|
||
; ; OSCCAL.CAL7 7 Oscillator Calibration Value 7
|
||
; ; OSCCAL.CAL6 6 Oscillator Calibration Value 6
|
||
; ; OSCCAL.CAL5 5 Oscillator Calibration Value 5
|
||
; ; OSCCAL.CAL4 4 Oscillator Calibration Value 4
|
||
; ; OSCCAL.CAL3 3 Oscillator Calibration Value 3
|
||
; ; OSCCAL.CAL2 2 Oscillator Calibration Value 2
|
||
; ; OSCCAL.CAL1 1 Oscillator Calibration Value 1
|
||
; ; OSCCAL.CAL0 0 Oscillator Calibration Value 0
|
||
; TCNT0 0x0052 Timer/Counter Register
|
||
; TCCR0 0x0053 Timer/Counter Control Register
|
||
; TCCR0.FOC0 7 Force Output Compare
|
||
; TCCR0.WGM00 6 Waveform Generation Mode 0
|
||
; TCCR0.COM01 5 Compare Match Output Mode 1
|
||
; TCCR0.COM00 4 Compare Match Output Mode 0
|
||
; TCCR0.WGM01 3 Waveform Generation Mode 1
|
||
; TCCR0.CS02 2 Clock Select 2
|
||
; TCCR0.CS01 1 Clock Select 1
|
||
; TCCR0.CS00 0 Clock Select 0
|
||
; MCUCSR 0x0054 MCU Control and Status Register
|
||
; MCUCSR.JTD 7 JTAG Interface Disable
|
||
; MCUCSR.ISC2 6 Interrupt Sense Control 2
|
||
; MCUCSR.JTRF 4 JTAG Reset Flag
|
||
; MCUCSR.WDRF 3 Watchdog Reset Flag
|
||
; MCUCSR.BORF 2 Brown-out Reset Flag
|
||
; MCUCSR.EXTRF 1 External Reset Flag
|
||
; MCUCSR.PORF 0 Power-on Reset Flag
|
||
; MCUCR 0x0055 MCU Control Register
|
||
; MCUCR.SM2 7 Sleep Mode Select Bit 2
|
||
; MCUCR.SE 6 Sleep Enable
|
||
; MCUCR.SM1 5 Sleep Mode Select Bit 1
|
||
; MCUCR.SM0 4 Sleep Mode Select Bit 0
|
||
; MCUCR.ISC11 3 Interrupt Sense Control 1 Bit 1
|
||
; MCUCR.ISC10 2 Interrupt Sense Control 1 Bit 0
|
||
; MCUCR.ISC01 1 Interrupt Sense Control 0 Bit 1
|
||
; MCUCR.ISC00 0 Interrupt Sense Control 0 Bit 0
|
||
; TWCR 0x0056 TWI Control Register
|
||
; TWCR.TWINT 7 TWI Interrupt Flag
|
||
; TWCR.TWEA 6 TWI Enable Acknowledge Bit
|
||
; TWCR.TWSTA 5 TWI START Condition Bit
|
||
; TWCR.TWSTO 4 TWI STOP Condition Bit
|
||
; TWCR.TWWC 3 TWI Write Collision Flag
|
||
; TWCR.TWEN 2 TWI Enable Bit
|
||
; TWCR.TWIE 0 TWI Interrupt Enable
|
||
; SPMCR 0x0057 Store Program Memory Control Register
|
||
; SPMCR.SPMIE 7 SPM Interrupt Enable
|
||
; SPMCR.RWWSB 6 Read-While-Write Section Busy
|
||
; SPMCR.RWWSRE 4 Read-While-Write Section Read Enable
|
||
; SPMCR.BLBSET 3 Boot Lock Bit Set
|
||
; SPMCR.PGWRT 2 Page Write
|
||
; SPMCR.PGERS 1 Page Erase
|
||
; SPMCR.SPMEN 0 Store Program Memory Enable
|
||
; TIFR 0x0058 Timer/Counter Interrupt Flag Register
|
||
; TIFR.OCF2 7 Output Compare Flag 2
|
||
; TIFR.TOV2 6 Timer/Counter0 Overflow Flag 2
|
||
; TIFR.ICF1 5 Timer/Counter1, Input Capture Flag
|
||
; TIFR.OCF1A 4 Timer/Counter1, Output Compare A Match Flag
|
||
; TIFR.OCF1B 3 Timer/Counter1, Output Compare B Match Flag
|
||
; TIFR.TOV1 2 Timer/Counter0 Overflow Flag 1
|
||
; TIFR.OCF0 1 Output Compare Flag 0
|
||
; TIFR.TOV0 0 Timer/Counter0 Overflow Flag 0
|
||
; TIMSK 0x0059 Timer/Counter Interrupt Mask Register
|
||
; TIMSK.OCIE2 7 Timer/Counter2 Output Compare Match Interrupt Enable
|
||
; TIMSK.TOIE2 6 Timer/Counter2 Overflow Interrupt Enable
|
||
; TIMSK.TICIE1 5 Timer/Counter1, Input Capture Interrupt Enable
|
||
; TIMSK.OCIE1A 4 Timer/Counter1, Output Compare A Match Interrupt Enable
|
||
; TIMSK.OCIE1B 3 Timer/Counter1, Output Compare B Match Interrupt Enable
|
||
; TIMSK.TOIE1 2 Timer/Counter1, Overflow Interrupt Enable
|
||
; TIMSK.OCIE0 1 Timer/Counter0 Output Compare Match Interrupt Enable
|
||
; TIMSK.TOIE0 0 Timer/Counter0 Overflow Interrupt Enable
|
||
; GIFR 0x005A General Interrupt Flag Register
|
||
; GIFR.INTF1 7 External Interrupt Flag 1
|
||
; GIFR.INTF0 6 External Interrupt Flag 0
|
||
; GIFR.INTF2 5 External Interrupt Flag 2
|
||
; GICR 0x005B General Interrupt Control Register
|
||
; GICR.INT1 7 External Interrupt Request 1 Enable
|
||
; GICR.INT0 6 External Interrupt Request 0 Enable
|
||
; GICR.INT2 5 External Interrupt Request 2 Enable
|
||
; GICR.IVSEL 1 Interrupt Vector Select
|
||
; GICR.IVCE 0 Interrupt Vector Change Enable
|
||
; OCR0 0x005C Output Compare Register
|
||
; SPL 0x005D Stack Pointer Low
|
||
; SPL.SP7 7
|
||
; SPL.SP6 6
|
||
; SPL.SP5 5
|
||
; SPL.SP4 4
|
||
; SPL.SP3 3
|
||
; SPL.SP2 2
|
||
; SPL.SP1 1
|
||
; SPL.SP0 0
|
||
; SPH 0x005E Stack Pointer High
|
||
; SPH.SP15 15
|
||
; SPH.SP14 14
|
||
; SPH.SP13 13
|
||
; SPH.SP12 12
|
||
; SPH.SP11 11
|
||
; SPH.SP10 10
|
||
; SPH.SP9 9
|
||
; SPH.SP8 8
|
||
; SREG 0x005F Status Register
|
||
; SREG.I 7 Global Interrupt Enable
|
||
; SREG.T 6 Bit Copy Storage
|
||
; SREG.H 5 Half Carry Flag
|
||
; SREG.S 4 Sign Bit
|
||
; SREG.V 3 Two's Complement Overflow Flag
|
||
; SREG.N 2 Negative Flag
|
||
; SREG.Z 1 Zero Flag
|
||
; SREG.C 0 CarryFlag
|
||
|
||
|
||
.ATmega323_L
|
||
SUBARCH=5
|
||
; doc1457.pdf
|
||
;
|
||
|
||
RAM=2048
|
||
ROM=32768
|
||
EEPROM=1024
|
||
|
||
|
||
; MEMORY MAP
|
||
|
||
|
||
; Interrupt and reset vector assignments
|
||
entry __RESET 0x0000 External Pin, Power-on Reset, Brown-out Reset and Watchdog Reset
|
||
entry INT0_ 0x0002 External Interrupt Request 0
|
||
entry INT1_ 0x0004 External Interrupt Request 1
|
||
entry INT2_ 0x0006 External Interrupt Request 2
|
||
entry TIMER2_COMP 0x0008 Timer/Counter2 Compare Match
|
||
entry TIMER2_OVF 0x000A Timer/Counter2 Overflow
|
||
entry TIMER1_CAPT 0x000C Timer/Counter1 Capture Event
|
||
entry TIMER1_COMPA 0x000E Timer/Counter1 Compare Match A
|
||
entry TIMER1_COMPB 0x0010 Timer/Counter1 Compare Match B
|
||
entry TIMER1_OVF 0x0012 Timer/Counter1 Overflow
|
||
entry TIMER0_COMP 0x0014 Timer/Counter0 Compare Match
|
||
entry TIMER0_OVF 0x0016 Timer/Counter0 Overflow
|
||
entry SPI_STC 0x0018 Serial Transfer Complete
|
||
entry USART_RXC 0x001A USART, Rx Complete
|
||
entry USART_UDRE 0x001C USART Data Register Empty
|
||
entry USART_TXC 0x001E USART, Tx Complete
|
||
entry ADC_ 0x0020 ADC Conversion Complete
|
||
entry EE_RDY 0x0022 EEPROM Ready
|
||
entry ANA_COMP 0x0024 Analog Comparator
|
||
entry TWSI_ 0x0026 2-wire Serial Interface
|
||
|
||
|
||
; INPUT/OUTPUT PORTS
|
||
TWBR 0x0000 2-wire Serial Interface Bit vRate Register
|
||
TWBR.TWBR7 7 2-wire Serial Interface Bit Rate Register bit 7
|
||
TWBR.TWBR6 6 2-wire Serial Interface Bit Rate Register bit 6
|
||
TWBR.TWBR5 5 2-wire Serial Interface Bit Rate Register bit 5
|
||
TWBR.TWBR4 4 2-wire Serial Interface Bit Rate Register bit 4
|
||
TWBR.TWBR3 3 2-wire Serial Interface Bit Rate Register bit 3
|
||
TWBR.TWBR2 2 2-wire Serial Interface Bit Rate Register bit 2
|
||
TWBR.TWBR1 1 2-wire Serial Interface Bit Rate Register bit 1
|
||
TWBR.TWBR0 0 2-wire Serial Interface Bit Rate Register bit 0
|
||
TWSR 0x0001 2-wire Serial Interface Status Register
|
||
TWSR.TWS7 7 2-wire Serial Interface Status bit 7
|
||
TWSR.TWS6 6 2-wire Serial Interface Status bit 6
|
||
TWSR.TWS5 5 2-wire Serial Interface Status bit 5
|
||
TWSR.TWS4 4 2-wire Serial Interface Status bit 4
|
||
TWSR.TWS3 3 2-wire Serial Interface Status bit 3
|
||
TWAR 0x0002 2-wire Serial Interface (Slave) Address Register
|
||
TWAR.TWA6 7 2-wire Serial Interface (Slave) Address Register bit 6
|
||
TWAR.TWA5 6 2-wire Serial Interface (Slave) Address Register bit 5
|
||
TWAR.TWA4 5 2-wire Serial Interface (Slave) Address Register bit 4
|
||
TWAR.TWA3 4 2-wire Serial Interface (Slave) Address Register bit 3
|
||
TWAR.TWA2 3 2-wire Serial Interface (Slave) Address Register bit 2
|
||
TWAR.TWA1 2 2-wire Serial Interface (Slave) Address Register bit 1
|
||
TWAR.TWA0 1 2-wire Serial Interface (Slave) Address Register bit 0
|
||
TWAR.TWGCE 0 2-wire Serial Interface General Call Recognition Enable bit
|
||
TWDR 0x0003 2-wire Serial Interface Data Register
|
||
TWDR.TWD7 7 2-wire Serial Interface Data Register bit 7
|
||
TWDR.TWD6 6 2-wire Serial Interface Data Register bit 6
|
||
TWDR.TWD5 5 2-wire Serial Interface Data Register bit 5
|
||
TWDR.TWD4 4 2-wire Serial Interface Data Register bit 4
|
||
TWDR.TWD3 3 2-wire Serial Interface Data Register bit 3
|
||
TWDR.TWD2 2 2-wire Serial Interface Data Register bit 2
|
||
TWDR.TWD1 1 2-wire Serial Interface Data Register bit 1
|
||
TWDR.TWD0 0 2-wire Serial Interface Data Register bit 0
|
||
ADCL 0x0004 ADC Data Register Low (ADLAR = 0)
|
||
ADCL.ADC7 7 ADC Conversion Result 7
|
||
ADCL.ADC6 6 ADC Conversion Result 6
|
||
ADCL.ADC5 5 ADC Conversion Result 5
|
||
ADCL.ADC4 4 ADC Conversion Result 4
|
||
ADCL.ADC3 3 ADC Conversion Result 3
|
||
ADCL.ADC2 2 ADC Conversion Result 2
|
||
ADCL.ADC1 1 ADC Conversion Result 1
|
||
ADCL.ADC0 0 ADC Conversion Result 0
|
||
ADCH 0x0005 ADC Data Register High (ADLAR = 0)
|
||
ADCH.SIGN 15
|
||
ADCH.ADC9 9 ADC Conversion Result 9
|
||
ADCH.ADC8 8 ADC Conversion Result 8
|
||
; ADCL 0x0004 ADC Data Register Low (ADLAR = 1)
|
||
; ADCL.ADC1 7 ADC Conversion Result 1
|
||
; ADCL.ADC0 6 ADC Conversion Result 0
|
||
; ADCH 0x0005 ADC Data Register High (ADLAR = 1)
|
||
; ADCH.ADC9 15 ADC Conversion Result 9
|
||
; ADCH.ADC8 14 ADC Conversion Result 8
|
||
; ADCH.ADC7 13 ADC Conversion Result 7
|
||
; ADCH.ADC6 12 ADC Conversion Result 6
|
||
; ADCH.ADC5 11 ADC Conversion Result 5
|
||
; ADCH.ADC4 10 ADC Conversion Result 4
|
||
; ADCH.ADC3 9 ADC Conversion Result 3
|
||
; ADCH.ADC2 8 ADC Conversion Result 2
|
||
ADCSR 0x0006 ADC Control and Status Register
|
||
ADCSR.ADEN 7 ADC Enable
|
||
ADCSR.ADSC 6 ADC Start Conversion
|
||
ADCSR.ADFR 5 ADC Free Running Select
|
||
ADCSR.ADIF 4 ADC Interrupt Flag
|
||
ADCSR.ADIE 3 ADC Interrupt Enable
|
||
ADCSR.ADPS2 2 ADC Prescaler Select Bit 2
|
||
ADCSR.ADPS1 1 ADC Prescaler Select Bit 1
|
||
ADCSR.ADPS0 0 ADC Prescaler Select Bit 0
|
||
ADMUX 0x0007 ADC Multiplexer Selection Register
|
||
ADMUX.REFS1 7 Reference Selection Bit 1
|
||
ADMUX.REFS0 6 Reference Selection Bit 0
|
||
ADMUX.ADLAR 5 ADC Left Adjust Result
|
||
ADMUX.MUX4 4 Analog Channel Selection Bit 4
|
||
ADMUX.MUX3 3 Analog Channel Selection Bit 3
|
||
ADMUX.MUX2 2 Analog Channel Selection Bit 2
|
||
ADMUX.MUX1 1 Analog Channel Selection Bit 1
|
||
ADMUX.MUX0 0 Analog Channel Selection Bit 0
|
||
ACSR 0x0008 Analog Comparator Control and Status Register
|
||
ACSR.ACD 7 Analog Comparator Disable
|
||
ACSR.ACBG 6 Analog Comparator Bandgap Select
|
||
ACSR.ACO 5 Analog Comparator Output
|
||
ACSR.ACI 4 Analog Comparator Interrupt Flag
|
||
ACSR.ACIE 3 Analog Comparator Interrupt Enable
|
||
ACSR.ACIC 2 Analog Comparator Input Capture Enable
|
||
ACSR.ACIS1 1 Analog Comparator Interrupt Mode Select 1
|
||
ACSR.ACIS0 0 Analog Comparator Interrupt Mode Select 0
|
||
UBRRL 0x0009 USART Baud Rate Register Low
|
||
UBRRL.UBRR7 7 USART Baud Rate Register bit 7
|
||
UBRRL.UBRR6 6 USART Baud Rate Register bit 6
|
||
UBRRL.UBRR5 5 USART Baud Rate Register bit 5
|
||
UBRRL.UBRR4 4 USART Baud Rate Register bit 4
|
||
UBRRL.UBRR3 3 USART Baud Rate Register bit 3
|
||
UBRRL.UBRR2 2 USART Baud Rate Register bit 2
|
||
UBRRL.UBRR1 1 USART Baud Rate Register bit 1
|
||
UBRRL.UBRR0 0 USART Baud Rate Register bit 0
|
||
UCSRB 0x000A USART Control and Status Register B
|
||
UCSRB.RXCIE 7 RX Complete Interrupt Enable
|
||
UCSRB.TXCIE 6 TX Complete Interrupt Enable
|
||
UCSRB.UDRIE 5 USART Data Register Empty Interrupt Enable
|
||
UCSRB.RXEN 4 Receiver Enable
|
||
UCSRB.TXEN 3 Transmitter Enable
|
||
UCSRB.UCSZ2 2 Character Size
|
||
UCSRB.RXB8 1 Receive Data Bit 8
|
||
UCSRB.TXB8 0 Transmit Data Bit 8
|
||
UCSRA 0x000B USART Control and Status Register A
|
||
UCSRA.RXC 7 USART Receive Complete
|
||
UCSRA.TXC 6 USART Transmit Complete
|
||
UCSRA.UDRE 5 USART Data Register Empty
|
||
UCSRA.FE 4 Frame Error
|
||
UCSRA.DOR 3 Data OverRun
|
||
UCSRA.PE 2 Parity Error
|
||
UCSRA.U2X 1 Double the USART Transmission Speed
|
||
UCSRA.MPCM 0 Multi-processor Communication Mode
|
||
UDR 0x000C USART I/O Data Register
|
||
SPCR 0x000D SPI Control Register
|
||
SPCR.SPIE 7 SPI Interrupt Enable
|
||
SPCR.SPE 6 SPI Enable
|
||
SPCR.DORD 5 Data Order
|
||
SPCR.MSTR 4 Master/Slave Select
|
||
SPCR.CPOL 3 Clock Polarity
|
||
SPCR.CPHA 2 Clock Phase
|
||
SPCR.SPR1 1 SPI Clock Rate Select 1
|
||
SPCR.SPR0 0 SPI Clock Rate Select 0
|
||
SPSR 0x000E SPI Status Register
|
||
SPSR.SPIF 7 SPI Interrupt Flag
|
||
SPSR.WCOL 6 Write COLlision flag
|
||
SPSR.SPI2X 0 Double SPI Speed Bit
|
||
SPDR 0x000F SPI Data Register
|
||
PIND 0x0010 Port D Input Pins Address
|
||
PIND.PIND7 7
|
||
PIND.PIND6 6
|
||
PIND.PIND5 5
|
||
PIND.PIND4 4
|
||
PIND.PIND3 3
|
||
PIND.PIND2 2
|
||
PIND.PIND1 1
|
||
PIND.PIND0 0
|
||
DDRD 0x0011 Port D Data Direction Register
|
||
DDRD.DDD7 7 Port D Data Direction Register bit 7
|
||
DDRD.DDD6 6 Port D Data Direction Register bit 6
|
||
DDRD.DDD5 5 Port D Data Direction Register bit 5
|
||
DDRD.DDD4 4 Port D Data Direction Register bit 4
|
||
DDRD.DDD3 3 Port D Data Direction Register bit 3
|
||
DDRD.DDD2 2 Port D Data Direction Register bit 2
|
||
DDRD.DDD1 1 Port D Data Direction Register bit 1
|
||
DDRD.DDD0 0 Port D Data Direction Register bit 0
|
||
PORTD 0x0012 Port D Data Register
|
||
PORTD.PORTD7 7 Port D Data Register bit 7
|
||
PORTD.PORTD6 6 Port D Data Register bit 6
|
||
PORTD.PORTD5 5 Port D Data Register bit 5
|
||
PORTD.PORTD4 4 Port D Data Register bit 4
|
||
PORTD.PORTD3 3 Port D Data Register bit 3
|
||
PORTD.PORTD2 2 Port D Data Register bit 2
|
||
PORTD.PORTD1 1 Port D Data Register bit 1
|
||
PORTD.PORTD0 0 Port D Data Register bit 0
|
||
PINC 0x0013 Port C Input Pins Address
|
||
PINC.PINC7 7
|
||
PINC.PINC6 6
|
||
PINC.PINC5 5
|
||
PINC.PINC4 4
|
||
PINC.PINC3 3
|
||
PINC.PINC2 2
|
||
PINC.PINC1 1
|
||
PINC.PINC0 0
|
||
DDRC 0x0014 Port C Data Direction Register
|
||
DDRC.DDC7 7 Port C Data Direction Register bit 7
|
||
DDRC.DDC6 6 Port C Data Direction Register bit 6
|
||
DDRC.DDC5 5 Port C Data Direction Register bit 5
|
||
DDRC.DDC4 4 Port C Data Direction Register bit 4
|
||
DDRC.DDC3 3 Port C Data Direction Register bit 3
|
||
DDRC.DDC2 2 Port C Data Direction Register bit 2
|
||
DDRC.DDC1 1 Port C Data Direction Register bit 1
|
||
DDRC.DDC0 0 Port C Data Direction Register bit 0
|
||
PORTC 0x0015 Port C Data Register
|
||
PORTC.PORTC7 7 Port C Data Register bit 7
|
||
PORTC.PORTC6 6 Port C Data Register bit 6
|
||
PORTC.PORTC5 5 Port C Data Register bit 5
|
||
PORTC.PORTC4 4 Port C Data Register bit 4
|
||
PORTC.PORTC3 3 Port C Data Register bit 3
|
||
PORTC.PORTC2 2 Port C Data Register bit 2
|
||
PORTC.PORTC1 1 Port C Data Register bit 1
|
||
PORTC.PORTC0 0 Port C Data Register bit 0
|
||
PINB 0x0016 Port B Input Pins Address
|
||
PINB.PINB7 7
|
||
PINB.PINB6 6
|
||
PINB.PINB5 5
|
||
PINB.PINB4 4
|
||
PINB.PINB3 3
|
||
PINB.PINB2 2
|
||
PINB.PINB1 1
|
||
PINB.PINB0 0
|
||
DDRB 0x0017 Port B Data Direction Register
|
||
DDRB.DDB7 7 Port B Data Direction Register bit 7
|
||
DDRB.DDB6 6 Port B Data Direction Register bit 6
|
||
DDRB.DDB5 5 Port B Data Direction Register bit 5
|
||
DDRB.DDB4 4 Port B Data Direction Register bit 4
|
||
DDRB.DDB3 3 Port B Data Direction Register bit 3
|
||
DDRB.DDB2 2 Port B Data Direction Register bit 2
|
||
DDRB.DDB1 1 Port B Data Direction Register bit 1
|
||
DDRB.DDB0 0 Port B Data Direction Register bit 0
|
||
PORTB 0x0018 Port B Data Register
|
||
PORTB.PORTB7 7 Port B Data Register bit 7
|
||
PORTB.PORTB6 6 Port B Data Register bit 6
|
||
PORTB.PORTB5 5 Port B Data Register bit 5
|
||
PORTB.PORTB4 4 Port B Data Register bit 4
|
||
PORTB.PORTB3 3 Port B Data Register bit 3
|
||
PORTB.PORTB2 2 Port B Data Register bit 2
|
||
PORTB.PORTB1 1 Port B Data Register bit 1
|
||
PORTB.PORTB0 0 Port B Data Register bit 0
|
||
PINA 0x0019 Port A Input Pins Address
|
||
PINA.PINA7 7
|
||
PINA.PINA6 6
|
||
PINA.PINA5 5
|
||
PINA.PINA4 4
|
||
PINA.PINA3 3
|
||
PINA.PINA2 2
|
||
PINA.PINA1 1
|
||
PINA.PINA0 0
|
||
DDRA 0x001A Port A Data Direction Register
|
||
DDRA.DDA7 7 Port A Data Direction Register bit 7
|
||
DDRA.DDA6 6 Port A Data Direction Register bit 6
|
||
DDRA.DDA5 5 Port A Data Direction Register bit 5
|
||
DDRA.DDA4 4 Port A Data Direction Register bit 4
|
||
DDRA.DDA3 3 Port A Data Direction Register bit 3
|
||
DDRA.DDA2 2 Port A Data Direction Register bit 2
|
||
DDRA.DDA1 1 Port A Data Direction Register bit 1
|
||
DDRA.DDA0 0 Port A Data Direction Register bit 0
|
||
PORTA 0x001B Port A Data Register
|
||
PORTA.PORTA7 7 Port A Data Register bit 7
|
||
PORTA.PORTA6 6 Port A Data Register bit 6
|
||
PORTA.PORTA5 5 Port A Data Register bit 5
|
||
PORTA.PORTA4 4 Port A Data Register bit 4
|
||
PORTA.PORTA3 3 Port A Data Register bit 3
|
||
PORTA.PORTA2 2 Port A Data Register bit 2
|
||
PORTA.PORTA1 1 Port A Data Register bit 1
|
||
PORTA.PORTA0 0 Port A Data Register bit 0
|
||
EECR 0x001C EEPROM Control Register
|
||
EECR.EERIE 3 EEPROM Ready Interrupt Enable
|
||
EECR.EEMWE 2 EEPROM Master Write Enable
|
||
EECR.EEWE 1 EEPROM Write Enable
|
||
EECR.EERE 0 EEPROM Read Enable
|
||
EEDR 0x001D EEPROM Data Register
|
||
EEDR.EEDR7 7 EEPROM Data 7
|
||
EEDR.EEDR6 6 EEPROM Data 6
|
||
EEDR.EEDR5 5 EEPROM Data 5
|
||
EEDR.EEDR4 4 EEPROM Data 4
|
||
EEDR.EEDR3 3 EEPROM Data 3
|
||
EEDR.EEDR2 2 EEPROM Data 2
|
||
EEDR.EEDR1 1 EEPROM Data 1
|
||
EEDR.EEDR0 0 EEPROM Data 0
|
||
EEARL 0x001E EEPROM Address Register Low
|
||
EEARL.EEAR7 7 EEPROM Addres 7
|
||
EEARL.EEAR6 6 EEPROM Addres 6
|
||
EEARL.EEAR5 5 EEPROM Addres 5
|
||
EEARL.EEAR4 4 EEPROM Addres 4
|
||
EEARL.EEAR3 3 EEPROM Addres 3
|
||
EEARL.EEAR2 2 EEPROM Addres 2
|
||
EEARL.EEAR1 1 EEPROM Addres 1
|
||
EEARL.EEAR0 0 EEPROM Addres 0
|
||
EEARH 0x001F EEPROM Address Register High
|
||
EEARH.EEAR9 9 EEPROM Addres 9
|
||
EEARH.EEAR8 8 EEPROM Addres 8
|
||
UCSRC 0x0020 USART Control and Status Register (page 91)
|
||
UCSRC.URSEL 7 Register Select
|
||
UCSRC.UMSEL 6 USART Mode Select
|
||
UCSRC.UPM1 5 Parity Mode 1
|
||
UCSRC.UPM0 4 Parity Mode 0
|
||
UCSRC.USBS 3 Stop Bit Select
|
||
UCSRC.UCSZ1 2 Character Size 1
|
||
UCSRC.UCSZ0 1 Character Size 0
|
||
UCSRC.UCPOL 0 Clock Polarity
|
||
; UBRRH 0x0020 USART Baud Rate Register High (page 91)
|
||
; UBRRH.URSEL 15 Register Select
|
||
; UBRRH.UBRR11 11 USART Baud Rate Register bit 11
|
||
; UBRRH.UBRR10 10 USART Baud Rate Register bit 10
|
||
; UBRRH.UBRR9 9 USART Baud Rate Register bit 9
|
||
; UBRRH.UBRR8 8 USART Baud Rate Register bit 8
|
||
WDTCR 0x0021 Watchdog Timer Control Register
|
||
WDTCR.WDTOE 4 Watch Dog Turn-off Enable
|
||
WDTCR.WDE 3 Watch Dog Enable
|
||
WDTCR.WDP2 2 Watch Dog Timer Prescaler 2
|
||
WDTCR.WDP1 1 Watch Dog Timer Prescaler 1
|
||
WDTCR.WDP0 0 Watch Dog Timer Prescaler 0
|
||
ASSR 0x0022 Asynchronous Status Register
|
||
ASSR.AS2 3 Asynchronous Timer/Counter2
|
||
ASSR.TCN2UB 2 Timer/Counter2 Update Busy
|
||
ASSR.OCR2UB 1 Output Compare Register2 Update Busy
|
||
ASSR.TCR2UB 0 Timer/Counter Control Register2 Update Busy
|
||
OCR2 0x0023 Timer/Counter2 Output Compare Register
|
||
TCNT2 0x0024 Timer/Counter2
|
||
TCCR2 0x0025 Timer/Counter2 Control Register
|
||
TCCR2.FOC2 7 Force Output Compare
|
||
TCCR2.PWM2 6 Pulse Width Modulator Enable
|
||
TCCR2.COM21 5 Compare Output Mode, Bit 1
|
||
TCCR2.COM20 4 Compare Output Mode, Bit 0
|
||
TCCR2.CTC2 3 Clear Timer/Counter on Compare Match
|
||
TCCR2.CS22 2 Clock Select bit 2
|
||
TCCR2.CS21 1 Clock Select bit 1
|
||
TCCR2.CS20 0 Clock Select bit 0
|
||
ICR1L 0x0026 Input Capture Register Low Byte
|
||
ICR1H 0x0027 Input Capture Register High Byte
|
||
OCR1BL 0x0028 Output Compare Register B Low Byte
|
||
OCR1BH 0x0029 Output Compare Register B High Byte
|
||
OCR1AL 0x002A Output Compare Register A Low Byte
|
||
OCR1AH 0x002B Output Compare Register A High Byte
|
||
TCNT1L 0x002C Counter Register Low Byte
|
||
TCNT1H 0x002D Counter Register High Byte
|
||
TCCR1B 0x002E Timer/Counter1 Control Register B
|
||
TCCR1B.ICNC1 7 Input Capture1 Noise Canceler (4 CKs)
|
||
TCCR1B.ICES1 6 Input Capture1 Edge Select
|
||
TCCR1B.CTC1 3 Clear Timer/Counter1 on Compare Match
|
||
TCCR1B.CS12 2 Clock Select1, Bit 2
|
||
TCCR1B.CS11 1 Clock Select1, Bit 1
|
||
TCCR1B.CS10 0 Clock Select1, Bit 0
|
||
TCCR1A 0x002F Timer/Counter1 Control Register A
|
||
TCCR1A.COM1A1 7 Compare Output Mode1A, bit 1
|
||
TCCR1A.COM1A0 6 Compare Output Mode1A, bit 0
|
||
TCCR1A.COM1B1 5 Compare Output Mode1B, bit 1
|
||
TCCR1A.COM1B0 4 Compare Output Mode1B, bit 0
|
||
TCCR1A.FOC1A 3 Force Output Compare1A
|
||
TCCR1A.FOC1B 2 Force Output Compare1B
|
||
TCCR1A.PWM11 1 Pulse Width Modulator Select Bit 1
|
||
TCCR1A.PWM10 0 Pulse Width Modulator Select Bit 0
|
||
SFIOR 0x0030 Special Function IO Register
|
||
SFIOR.ACME 3 Analog Comparator Multiplexer Enable
|
||
SFIOR.PUD 2 Pull-up Disable
|
||
SFIOR.PSR2 1 Prescaler Reset Timer/Counter2
|
||
SFIOR.PSR10 0 Prescaler Reset Timer/Counter1 and Timer/Counter0
|
||
OCRD 0x0031 On-chip Debug Register
|
||
; OSCCAL 0x0031 Oscillator Calibration Register
|
||
; OSCCAL.CAL7 7 Oscillator Calibration Value 7
|
||
; OSCCAL.CAL6 6 Oscillator Calibration Value 6
|
||
; OSCCAL.CAL5 5 Oscillator Calibration Value 5
|
||
; OSCCAL.CAL4 4 Oscillator Calibration Value 4
|
||
; OSCCAL.CAL3 3 Oscillator Calibration Value 3
|
||
; OSCCAL.CAL2 2 Oscillator Calibration Value 2
|
||
; OSCCAL.CAL1 1 Oscillator Calibration Value 1
|
||
; OSCCAL.CAL0 0 Oscillator Calibration Value 0
|
||
TCNT0 0x0032 Timer/Counter0
|
||
TCCR0 0x0033 Timer/Counter0 Control Register
|
||
TCCR0.FOC0 7 Force Output Compare
|
||
TCCR0.PWM0 6 Pulse Width Modulator Enable
|
||
TCCR0.COM01 5 Compare Output Mode, Bit 1
|
||
TCCR0.COM00 4 Compare Output Mode, Bit 0
|
||
TCCR0.CTC0 3 Clear Timer/Counter on Compare Match
|
||
TCCR0.CS02 2 Clock Select bit 2
|
||
TCCR0.CS01 1 Clock Select bit 1
|
||
TCCR0.CS00 0 Clock Select bit 0
|
||
MCUCSR 0x0034 MCU Control and Status Register
|
||
MCUCSR.JTD 7 JTAG interface disable
|
||
MCUCSR.ISC2 6 Interrupt Sense Control 2
|
||
MCUCSR.JTRF 4 JTAG Reset Flag
|
||
MCUCSR.WDRF 3 Watchdog Reset Flag
|
||
MCUCSR.BORF 2 Brown-out Reset Flag
|
||
MCUCSR.EXTRF 1 External Reset Flag
|
||
MCUCSR.PORF 0 Power-on Reset Flag
|
||
MCUCR 0x0035 MCU Control Register
|
||
MCUCR.SE 7 Sleep Enable
|
||
MCUCR.SM2 6 Sleep Mode Select Bit 2
|
||
MCUCR.SM1 5 Sleep Mode Select Bit 1
|
||
MCUCR.SM0 4 Sleep Mode Select Bit 0
|
||
MCUCR.ISC11 3 Interrupt Sense Control 1 Bit 1
|
||
MCUCR.ISC10 2 Interrupt Sense Control 1 Bit 0
|
||
MCUCR.ISC01 1 Interrupt Sense Control 0 Bit 1
|
||
MCUCR.ISC00 0 Interrupt Sense Control 0 Bit 0
|
||
TWCR 0x0036 2-wire Serial Interface Control Register
|
||
TWCR.TWINT 7 2-wire Serial Interface Interrupt Flag
|
||
TWCR.TWEA 6 2-wire Serial Interface Enable Acknowledge Flag
|
||
TWCR.TWSTA 5 2-wire Serial Bus START Condition Flag
|
||
TWCR.TWSTO 4 2-wire Serial Bus STOP Condition Flag
|
||
TWCR.TWWC 3 2-wire Serial Bus Write Collision Flag
|
||
TWCR.TWEN 2 2-wire Serial Interface Enable Bit
|
||
TWCR.TWIE 0 2-wire Serial Interface Interrupt Enable
|
||
SPMCR 0x0037 Store Program Memory Control Register
|
||
SPMCR.ASB 6 Application Section Busy
|
||
SPMCR.ASRE 4 Application Section Read Enable
|
||
SPMCR.BLBSET 3 Boot Lock Bit Set
|
||
SPMCR.PGWRT 2 Page Write
|
||
SPMCR.PGERS 1 Page Erase
|
||
SPMCR.SPMEN 0 Store Program Memory Enable
|
||
TIFR 0x0038 Timer/Counter Interrupt Flag Register
|
||
TIFR.OCF2 7 Output Compare Flag 2
|
||
TIFR.TOV2 6 Timer/Counter2 Overflow Flag
|
||
TIFR.ICF1 5 Input Capture Flag 1
|
||
TIFR.OCF1A 4 Output Compare Flag 1A
|
||
TIFR.OCF1B 3 Output Compare Flag 1B
|
||
TIFR.TOV1 2 Timer/Counter1 Overflow Flag
|
||
TIFR.OCF0 1 Output Compare Flag 0
|
||
TIFR.TOV0 0 Timer/Counter0 Overflow Flag
|
||
TIMSK 0x0039 Timer/Counter Interrupt Flag Register
|
||
TIMSK.OCF2 7 Output Compare Flag 2
|
||
TIMSK.TOV2 6 Timer/Counter2 Overflow Flag
|
||
TIMSK.ICF1 5 Input Capture Flag 1
|
||
TIMSK.OCF1A 4 Output Compare Flag 1A
|
||
TIMSK.OCF1B 3 Output Compare Flag 1B
|
||
TIMSK.TOV1 2 Timer/Counter1 Overflow Flag
|
||
TIMSK.OCF0 1 Output Compare Flag 0
|
||
TIMSK.TOV0 0 Timer/Counter0 Overflow Flag
|
||
GIFR 0x003A General Interrupt Flag Register
|
||
GIFR.INTF1 7 External Interrupt Flag1
|
||
GIFR.INTF0 6 External Interrupt Flag0
|
||
GIFR.INTF2 5 External Interrupt Flag2
|
||
GICR 0x003B General Interrupt Control Register
|
||
GICR.INT1 7 External Interrupt Request 1 Enable
|
||
GICR.INT0 6 External Interrupt Request 0 Enable
|
||
GICR.INT2 5 External Interrupt Request 2 Enable
|
||
GICR.IVSEL 1 Interrupt Vector Select
|
||
GICR.IVCE 0 Interrupt Vector Change Enable
|
||
OCR0 0x003C Timer/Counter0 Output Compare Register
|
||
SPL 0x003D Stack Pointer Low
|
||
SPL.SP7 7
|
||
SPL.SP6 6
|
||
SPL.SP5 5
|
||
SPL.SP4 4
|
||
SPL.SP3 3
|
||
SPL.SP2 2
|
||
SPL.SP1 1
|
||
SPL.SP0 0
|
||
SPH 0x003E Stack Pointer High
|
||
SPH.SP11 11
|
||
SPH.SP10 10
|
||
SPH.SP9 9
|
||
SPH.SP8 8
|
||
SREG 0x003F Status Register
|
||
SREG.I 7 Global Interrupt Enable
|
||
SREG.T 6 Bit Copy Storage
|
||
SREG.H 5 Half Carry Flag
|
||
SREG.S 4 Sign Bit
|
||
SREG.V 3 Two's Complement Overflow Flag
|
||
SREG.N 2 Negative Flag
|
||
SREG.Z 1 Zero Flag
|
||
SREG.C 0 Carry Flag
|
||
|
||
; TWBR 0x0020 2-wire Serial Interface Bit vRate Register
|
||
; TWBR.TWBR7 7 2-wire Serial Interface Bit Rate Register bit 7
|
||
; TWBR.TWBR6 6 2-wire Serial Interface Bit Rate Register bit 6
|
||
; TWBR.TWBR5 5 2-wire Serial Interface Bit Rate Register bit 5
|
||
; TWBR.TWBR4 4 2-wire Serial Interface Bit Rate Register bit 4
|
||
; TWBR.TWBR3 3 2-wire Serial Interface Bit Rate Register bit 3
|
||
; TWBR.TWBR2 2 2-wire Serial Interface Bit Rate Register bit 2
|
||
; TWBR.TWBR1 1 2-wire Serial Interface Bit Rate Register bit 1
|
||
; TWBR.TWBR0 0 2-wire Serial Interface Bit Rate Register bit 0
|
||
; TWSR 0x0021 2-wire Serial Interface Status Register
|
||
; TWSR.TWS7 7 2-wire Serial Interface Status bit 7
|
||
; TWSR.TWS6 6 2-wire Serial Interface Status bit 6
|
||
; TWSR.TWS5 5 2-wire Serial Interface Status bit 5
|
||
; TWSR.TWS4 4 2-wire Serial Interface Status bit 4
|
||
; TWSR.TWS3 3 2-wire Serial Interface Status bit 3
|
||
; TWAR 0x0022 2-wire Serial Interface (Slave) Address Register
|
||
; TWAR.TWA6 7 2-wire Serial Interface (Slave) Address Register bit 6
|
||
; TWAR.TWA5 6 2-wire Serial Interface (Slave) Address Register bit 5
|
||
; TWAR.TWA4 5 2-wire Serial Interface (Slave) Address Register bit 4
|
||
; TWAR.TWA3 4 2-wire Serial Interface (Slave) Address Register bit 3
|
||
; TWAR.TWA2 3 2-wire Serial Interface (Slave) Address Register bit 2
|
||
; TWAR.TWA1 2 2-wire Serial Interface (Slave) Address Register bit 1
|
||
; TWAR.TWA0 1 2-wire Serial Interface (Slave) Address Register bit 0
|
||
; TWAR.TWGCE 0 2-wire Serial Interface General Call Recognition Enable bit
|
||
; TWDR 0x0023 2-wire Serial Interface Data Register
|
||
; TWDR.TWD7 7 2-wire Serial Interface Data Register bit 7
|
||
; TWDR.TWD6 6 2-wire Serial Interface Data Register bit 6
|
||
; TWDR.TWD5 5 2-wire Serial Interface Data Register bit 5
|
||
; TWDR.TWD4 4 2-wire Serial Interface Data Register bit 4
|
||
; TWDR.TWD3 3 2-wire Serial Interface Data Register bit 3
|
||
; TWDR.TWD2 2 2-wire Serial Interface Data Register bit 2
|
||
; TWDR.TWD1 1 2-wire Serial Interface Data Register bit 1
|
||
; TWDR.TWD0 0 2-wire Serial Interface Data Register bit 0
|
||
; ADCL 0x0024 ADC Data Register Low (ADLAR = 0)
|
||
; ADCL.ADC7 7 ADC Conversion Result 7
|
||
; ADCL.ADC6 6 ADC Conversion Result 6
|
||
; ADCL.ADC5 5 ADC Conversion Result 5
|
||
; ADCL.ADC4 4 ADC Conversion Result 4
|
||
; ADCL.ADC3 3 ADC Conversion Result 3
|
||
; ADCL.ADC2 2 ADC Conversion Result 2
|
||
; ADCL.ADC1 1 ADC Conversion Result 1
|
||
; ADCL.ADC0 0 ADC Conversion Result 0
|
||
; ADCH 0x0025 ADC Data Register High (ADLAR = 0)
|
||
; ADCH.SIGN 15
|
||
; ADCH.ADC9 9 ADC Conversion Result 9
|
||
; ADCH.ADC8 8 ADC Conversion Result 8
|
||
; ; ADCL 0x0024 ADC Data Register Low (ADLAR = 1)
|
||
; ; ADCL.ADC1 7 ADC Conversion Result 1
|
||
; ; ADCL.ADC0 6 ADC Conversion Result 0
|
||
; ; ADCH 0x0025 ADC Data Register High (ADLAR = 1)
|
||
; ; ADCH.ADC9 15 ADC Conversion Result 9
|
||
; ; ADCH.ADC8 14 ADC Conversion Result 8
|
||
; ; ADCH.ADC7 13 ADC Conversion Result 7
|
||
; ; ADCH.ADC6 12 ADC Conversion Result 6
|
||
; ; ADCH.ADC5 11 ADC Conversion Result 5
|
||
; ; ADCH.ADC4 10 ADC Conversion Result 4
|
||
; ; ADCH.ADC3 9 ADC Conversion Result 3
|
||
; ; ADCH.ADC2 8 ADC Conversion Result 2
|
||
; ADCSR 0x0026 ADC Control and Status Register
|
||
; ADCSR.ADEN 7 ADC Enable
|
||
; ADCSR.ADSC 6 ADC Start Conversion
|
||
; ADCSR.ADFR 5 ADC Free Running Select
|
||
; ADCSR.ADIF 4 ADC Interrupt Flag
|
||
; ADCSR.ADIE 3 ADC Interrupt Enable
|
||
; ADCSR.ADPS2 2 ADC Prescaler Select Bit 2
|
||
; ADCSR.ADPS1 1 ADC Prescaler Select Bit 1
|
||
; ADCSR.ADPS0 0 ADC Prescaler Select Bit 0
|
||
; ADMUX 0x0027 ADC Multiplexer Selection Register
|
||
; ADMUX.REFS1 7 Reference Selection Bit 1
|
||
; ADMUX.REFS0 6 Reference Selection Bit 0
|
||
; ADMUX.ADLAR 5 ADC Left Adjust Result
|
||
; ADMUX.MUX4 4 Analog Channel Selection Bit 4
|
||
; ADMUX.MUX3 3 Analog Channel Selection Bit 3
|
||
; ADMUX.MUX2 2 Analog Channel Selection Bit 2
|
||
; ADMUX.MUX1 1 Analog Channel Selection Bit 1
|
||
; ADMUX.MUX0 0 Analog Channel Selection Bit 0
|
||
; ACSR 0x0028 Analog Comparator Control and Status Register
|
||
; ACSR.ACD 7 Analog Comparator Disable
|
||
; ACSR.ACBG 6 Analog Comparator Bandgap Select
|
||
; ACSR.ACO 5 Analog Comparator Output
|
||
; ACSR.ACI 4 Analog Comparator Interrupt Flag
|
||
; ACSR.ACIE 3 Analog Comparator Interrupt Enable
|
||
; ACSR.ACIC 2 Analog Comparator Input Capture Enable
|
||
; ACSR.ACIS1 1 Analog Comparator Interrupt Mode Select 1
|
||
; ACSR.ACIS0 0 Analog Comparator Interrupt Mode Select 0
|
||
; UBRRL 0x0029 USART Baud Rate Register Low
|
||
; UBRRL.UBRR7 7 USART Baud Rate Register bit 7
|
||
; UBRRL.UBRR6 6 USART Baud Rate Register bit 6
|
||
; UBRRL.UBRR5 5 USART Baud Rate Register bit 5
|
||
; UBRRL.UBRR4 4 USART Baud Rate Register bit 4
|
||
; UBRRL.UBRR3 3 USART Baud Rate Register bit 3
|
||
; UBRRL.UBRR2 2 USART Baud Rate Register bit 2
|
||
; UBRRL.UBRR1 1 USART Baud Rate Register bit 1
|
||
; UBRRL.UBRR0 0 USART Baud Rate Register bit 0
|
||
; UCSRB 0x002A USART Control and Status Register B
|
||
; UCSRB.RXCIE 7 RX Complete Interrupt Enable
|
||
; UCSRB.TXCIE 6 TX Complete Interrupt Enable
|
||
; UCSRB.UDRIE 5 USART Data Register Empty Interrupt Enable
|
||
; UCSRB.RXEN 4 Receiver Enable
|
||
; UCSRB.TXEN 3 Transmitter Enable
|
||
; UCSRB.UCSZ2 2 Character Size
|
||
; UCSRB.RXB8 1 Receive Data Bit 8
|
||
; UCSRB.TXB8 0 Transmit Data Bit 8
|
||
; UCSRA 0x002B USART Control and Status Register A
|
||
; UCSRA.RXC 7 USART Receive Complete
|
||
; UCSRA.TXC 6 USART Transmit Complete
|
||
; UCSRA.UDRE 5 USART Data Register Empty
|
||
; UCSRA.FE 4 Frame Error
|
||
; UCSRA.DOR 3 Data OverRun
|
||
; UCSRA.PE 2 Parity Error
|
||
; UCSRA.U2X 1 Double the USART Transmission Speed
|
||
; UCSRA.MPCM 0 Multi-processor Communication Mode
|
||
; UDR 0x002C USART I/O Data Register
|
||
; SPCR 0x002D SPI Control Register
|
||
; SPCR.SPIE 7 SPI Interrupt Enable
|
||
; SPCR.SPE 6 SPI Enable
|
||
; SPCR.DORD 5 Data Order
|
||
; SPCR.MSTR 4 Master/Slave Select
|
||
; SPCR.CPOL 3 Clock Polarity
|
||
; SPCR.CPHA 2 Clock Phase
|
||
; SPCR.SPR1 1 SPI Clock Rate Select 1
|
||
; SPCR.SPR0 0 SPI Clock Rate Select 0
|
||
; SPSR 0x002E SPI Status Register
|
||
; SPSR.SPIF 7 SPI Interrupt Flag
|
||
; SPSR.WCOL 6 Write COLlision flag
|
||
; SPSR.SPI2X 0 Double SPI Speed Bit
|
||
; SPDR 0x002F SPI Data Register
|
||
; PIND 0x0030 Port D Input Pins Address
|
||
; PIND.PIND7 7
|
||
; PIND.PIND6 6
|
||
; PIND.PIND5 5
|
||
; PIND.PIND4 4
|
||
; PIND.PIND3 3
|
||
; PIND.PIND2 2
|
||
; PIND.PIND1 1
|
||
; PIND.PIND0 0
|
||
; DDRD 0x0031 Port D Data Direction Register
|
||
; DDRD.DDD7 7 Port D Data Direction Register bit 7
|
||
; DDRD.DDD6 6 Port D Data Direction Register bit 6
|
||
; DDRD.DDD5 5 Port D Data Direction Register bit 5
|
||
; DDRD.DDD4 4 Port D Data Direction Register bit 4
|
||
; DDRD.DDD3 3 Port D Data Direction Register bit 3
|
||
; DDRD.DDD2 2 Port D Data Direction Register bit 2
|
||
; DDRD.DDD1 1 Port D Data Direction Register bit 1
|
||
; DDRD.DDD0 0 Port D Data Direction Register bit 0
|
||
; PORTD 0x0032 Port D Data Register
|
||
; PORTD.PORTD7 7 Port D Data Register bit 7
|
||
; PORTD.PORTD6 6 Port D Data Register bit 6
|
||
; PORTD.PORTD5 5 Port D Data Register bit 5
|
||
; PORTD.PORTD4 4 Port D Data Register bit 4
|
||
; PORTD.PORTD3 3 Port D Data Register bit 3
|
||
; PORTD.PORTD2 2 Port D Data Register bit 2
|
||
; PORTD.PORTD1 1 Port D Data Register bit 1
|
||
; PORTD.PORTD0 0 Port D Data Register bit 0
|
||
; PINC 0x0033 Port C Input Pins Address
|
||
; PINC.PINC7 7
|
||
; PINC.PINC6 6
|
||
; PINC.PINC5 5
|
||
; PINC.PINC4 4
|
||
; PINC.PINC3 3
|
||
; PINC.PINC2 2
|
||
; PINC.PINC1 1
|
||
; PINC.PINC0 0
|
||
; DDRC 0x0034 Port C Data Direction Register
|
||
; DDRC.DDC7 7 Port C Data Direction Register bit 7
|
||
; DDRC.DDC6 6 Port C Data Direction Register bit 6
|
||
; DDRC.DDC5 5 Port C Data Direction Register bit 5
|
||
; DDRC.DDC4 4 Port C Data Direction Register bit 4
|
||
; DDRC.DDC3 3 Port C Data Direction Register bit 3
|
||
; DDRC.DDC2 2 Port C Data Direction Register bit 2
|
||
; DDRC.DDC1 1 Port C Data Direction Register bit 1
|
||
; DDRC.DDC0 0 Port C Data Direction Register bit 0
|
||
; PORTC 0x0035 Port C Data Register
|
||
; PORTC.PORTC7 7 Port C Data Register bit 7
|
||
; PORTC.PORTC6 6 Port C Data Register bit 6
|
||
; PORTC.PORTC5 5 Port C Data Register bit 5
|
||
; PORTC.PORTC4 4 Port C Data Register bit 4
|
||
; PORTC.PORTC3 3 Port C Data Register bit 3
|
||
; PORTC.PORTC2 2 Port C Data Register bit 2
|
||
; PORTC.PORTC1 1 Port C Data Register bit 1
|
||
; PORTC.PORTC0 0 Port C Data Register bit 0
|
||
; PINB 0x0036 Port B Input Pins Address
|
||
; PINB.PINB7 7
|
||
; PINB.PINB6 6
|
||
; PINB.PINB5 5
|
||
; PINB.PINB4 4
|
||
; PINB.PINB3 3
|
||
; PINB.PINB2 2
|
||
; PINB.PINB1 1
|
||
; PINB.PINB0 0
|
||
; DDRB 0x0037 Port B Data Direction Register
|
||
; DDRB.DDB7 7 Port B Data Direction Register bit 7
|
||
; DDRB.DDB6 6 Port B Data Direction Register bit 6
|
||
; DDRB.DDB5 5 Port B Data Direction Register bit 5
|
||
; DDRB.DDB4 4 Port B Data Direction Register bit 4
|
||
; DDRB.DDB3 3 Port B Data Direction Register bit 3
|
||
; DDRB.DDB2 2 Port B Data Direction Register bit 2
|
||
; DDRB.DDB1 1 Port B Data Direction Register bit 1
|
||
; DDRB.DDB0 0 Port B Data Direction Register bit 0
|
||
; PORTB 0x0038 Port B Data Register
|
||
; PORTB.PORTB7 7 Port B Data Register bit 7
|
||
; PORTB.PORTB6 6 Port B Data Register bit 6
|
||
; PORTB.PORTB5 5 Port B Data Register bit 5
|
||
; PORTB.PORTB4 4 Port B Data Register bit 4
|
||
; PORTB.PORTB3 3 Port B Data Register bit 3
|
||
; PORTB.PORTB2 2 Port B Data Register bit 2
|
||
; PORTB.PORTB1 1 Port B Data Register bit 1
|
||
; PORTB.PORTB0 0 Port B Data Register bit 0
|
||
; PINA 0x0039 Port A Input Pins Address
|
||
; PINA.PINA7 7
|
||
; PINA.PINA6 6
|
||
; PINA.PINA5 5
|
||
; PINA.PINA4 4
|
||
; PINA.PINA3 3
|
||
; PINA.PINA2 2
|
||
; PINA.PINA1 1
|
||
; PINA.PINA0 0
|
||
; DDRA 0x003A Port A Data Direction Register
|
||
; DDRA.DDA7 7 Port A Data Direction Register bit 7
|
||
; DDRA.DDA6 6 Port A Data Direction Register bit 6
|
||
; DDRA.DDA5 5 Port A Data Direction Register bit 5
|
||
; DDRA.DDA4 4 Port A Data Direction Register bit 4
|
||
; DDRA.DDA3 3 Port A Data Direction Register bit 3
|
||
; DDRA.DDA2 2 Port A Data Direction Register bit 2
|
||
; DDRA.DDA1 1 Port A Data Direction Register bit 1
|
||
; DDRA.DDA0 0 Port A Data Direction Register bit 0
|
||
; PORTA 0x003B Port A Data Register
|
||
; PORTA.PORTA7 7 Port A Data Register bit 7
|
||
; PORTA.PORTA6 6 Port A Data Register bit 6
|
||
; PORTA.PORTA5 5 Port A Data Register bit 5
|
||
; PORTA.PORTA4 4 Port A Data Register bit 4
|
||
; PORTA.PORTA3 3 Port A Data Register bit 3
|
||
; PORTA.PORTA2 2 Port A Data Register bit 2
|
||
; PORTA.PORTA1 1 Port A Data Register bit 1
|
||
; PORTA.PORTA0 0 Port A Data Register bit 0
|
||
; EECR 0x003C EEPROM Control Register
|
||
; EECR.EERIE 3 EEPROM Ready Interrupt Enable
|
||
; EECR.EEMWE 2 EEPROM Master Write Enable
|
||
; EECR.EEWE 1 EEPROM Write Enable
|
||
; EECR.EERE 0 EEPROM Read Enable
|
||
; EEDR 0x003D EEPROM Data Register
|
||
; EEDR.EEDR7 7 EEPROM Data 7
|
||
; EEDR.EEDR6 6 EEPROM Data 6
|
||
; EEDR.EEDR5 5 EEPROM Data 5
|
||
; EEDR.EEDR4 4 EEPROM Data 4
|
||
; EEDR.EEDR3 3 EEPROM Data 3
|
||
; EEDR.EEDR2 2 EEPROM Data 2
|
||
; EEDR.EEDR1 1 EEPROM Data 1
|
||
; EEDR.EEDR0 0 EEPROM Data 0
|
||
; EEARL 0x003E EEPROM Address Register Low
|
||
; EEARL.EEAR7 7 EEPROM Addres 7
|
||
; EEARL.EEAR6 6 EEPROM Addres 6
|
||
; EEARL.EEAR5 5 EEPROM Addres 5
|
||
; EEARL.EEAR4 4 EEPROM Addres 4
|
||
; EEARL.EEAR3 3 EEPROM Addres 3
|
||
; EEARL.EEAR2 2 EEPROM Addres 2
|
||
; EEARL.EEAR1 1 EEPROM Addres 1
|
||
; EEARL.EEAR0 0 EEPROM Addres 0
|
||
; EEARH 0x003F EEPROM Address Register High
|
||
; EEARH.EEAR9 9 EEPROM Addres 9
|
||
; EEARH.EEAR8 8 EEPROM Addres 8
|
||
; UCSRC 0x0040 USART Control and Status Register (page 91)
|
||
; UCSRC.URSEL 7 Register Select
|
||
; UCSRC.UMSEL 6 USART Mode Select
|
||
; UCSRC.UPM1 5 Parity Mode 1
|
||
; UCSRC.UPM0 4 Parity Mode 0
|
||
; UCSRC.USBS 3 Stop Bit Select
|
||
; UCSRC.UCSZ1 2 Character Size 1
|
||
; UCSRC.UCSZ0 1 Character Size 0
|
||
; UCSRC.UCPOL 0 Clock Polarity
|
||
; ; UBRRH 0x0040 USART Baud Rate Register High (page 91)
|
||
; ; UBRRH.URSEL 15 Register Select
|
||
; ; UBRRH.UBRR11 11 USART Baud Rate Register bit 11
|
||
; ; UBRRH.UBRR10 10 USART Baud Rate Register bit 10
|
||
; ; UBRRH.UBRR9 9 USART Baud Rate Register bit 9
|
||
; ; UBRRH.UBRR8 8 USART Baud Rate Register bit 8
|
||
; WDTCR 0x0041 Watchdog Timer Control Register
|
||
; WDTCR.WDTOE 4 Watch Dog Turn-off Enable
|
||
; WDTCR.WDE 3 Watch Dog Enable
|
||
; WDTCR.WDP2 2 Watch Dog Timer Prescaler 2
|
||
; WDTCR.WDP1 1 Watch Dog Timer Prescaler 1
|
||
; WDTCR.WDP0 0 Watch Dog Timer Prescaler 0
|
||
; ASSR 0x0042 Asynchronous Status Register
|
||
; ASSR.AS2 3 Asynchronous Timer/Counter2
|
||
; ASSR.TCN2UB 2 Timer/Counter2 Update Busy
|
||
; ASSR.OCR2UB 1 Output Compare Register2 Update Busy
|
||
; ASSR.TCR2UB 0 Timer/Counter Control Register2 Update Busy
|
||
; OCR2 0x0043 Timer/Counter2 Output Compare Register
|
||
; TCNT2 0x0044 Timer/Counter2
|
||
; TCCR2 0x0045 Timer/Counter2 Control Register
|
||
; TCCR2.FOC2 7 Force Output Compare
|
||
; TCCR2.PWM2 6 Pulse Width Modulator Enable
|
||
; TCCR2.COM21 5 Compare Output Mode, Bit 1
|
||
; TCCR2.COM20 4 Compare Output Mode, Bit 0
|
||
; TCCR2.CTC2 3 Clear Timer/Counter on Compare Match
|
||
; TCCR2.CS22 2 Clock Select bit 2
|
||
; TCCR2.CS21 1 Clock Select bit 1
|
||
; TCCR2.CS20 0 Clock Select bit 0
|
||
; ICR1L 0x0026 Input Capture Register Low Byte
|
||
; ICR1H 0x0027 Input Capture Register High Byte
|
||
; OCR1BL 0x0028 Output Compare Register B Low Byte
|
||
; OCR1BH 0x0029 Output Compare Register B High Byte
|
||
; OCR1AL 0x002A Output Compare Register A Low Byte
|
||
; OCR1AH 0x002B Output Compare Register A High Byte
|
||
; TCNT1L 0x002C Counter Register Low Byte
|
||
; TCNT1H 0x002D Counter Register High Byte
|
||
; TCCR1B 0x002E Timer/Counter1 Control Register B
|
||
; TCCR1B.ICNC1 7 Input Capture1 Noise Canceler (4 CKs)
|
||
; TCCR1B.ICES1 6 Input Capture1 Edge Select
|
||
; TCCR1B.CTC1 3 Clear Timer/Counter1 on Compare Match
|
||
; TCCR1B.CS12 2 Clock Select1, Bit 2
|
||
; TCCR1B.CS11 1 Clock Select1, Bit 1
|
||
; TCCR1B.CS10 0 Clock Select1, Bit 0
|
||
; TCCR1A 0x004F Timer/Counter1 Control Register A
|
||
; TCCR1A.COM1A1 7 Compare Output Mode1A, bit 1
|
||
; TCCR1A.COM1A0 6 Compare Output Mode1A, bit 0
|
||
; TCCR1A.COM1B1 5 Compare Output Mode1B, bit 1
|
||
; TCCR1A.COM1B0 4 Compare Output Mode1B, bit 0
|
||
; TCCR1A.FOC1A 3 Force Output Compare1A
|
||
; TCCR1A.FOC1B 2 Force Output Compare1B
|
||
; TCCR1A.PWM11 1 Pulse Width Modulator Select Bit 1
|
||
; TCCR1A.PWM10 0 Pulse Width Modulator Select Bit 0
|
||
; SFIOR 0x0050 Special Function IO Register
|
||
; SFIOR.ACME 3 Analog Comparator Multiplexer Enable
|
||
; SFIOR.PUD 2 Pull-up Disable
|
||
; SFIOR.PSR2 1 Prescaler Reset Timer/Counter2
|
||
; SFIOR.PSR10 0 Prescaler Reset Timer/Counter1 and Timer/Counter0
|
||
; OCRD 0x0051 On-chip Debug Register
|
||
; ; OSCCAL 0x0051 Oscillator Calibration Register
|
||
; ; OSCCAL.CAL7 7 Oscillator Calibration Value 7
|
||
; ; OSCCAL.CAL6 6 Oscillator Calibration Value 6
|
||
; ; OSCCAL.CAL5 5 Oscillator Calibration Value 5
|
||
; ; OSCCAL.CAL4 4 Oscillator Calibration Value 4
|
||
; ; OSCCAL.CAL3 3 Oscillator Calibration Value 3
|
||
; ; OSCCAL.CAL2 2 Oscillator Calibration Value 2
|
||
; ; OSCCAL.CAL1 1 Oscillator Calibration Value 1
|
||
; ; OSCCAL.CAL0 0 Oscillator Calibration Value 0
|
||
; TCNT0 0x0052 Timer/Counter0
|
||
; TCCR0 0x0053 Timer/Counter0 Control Register
|
||
; TCCR0.FOC0 7 Force Output Compare
|
||
; TCCR0.PWM0 6 Pulse Width Modulator Enable
|
||
; TCCR0.COM01 5 Compare Output Mode, Bit 1
|
||
; TCCR0.COM00 4 Compare Output Mode, Bit 0
|
||
; TCCR0.CTC0 3 Clear Timer/Counter on Compare Match
|
||
; TCCR0.CS02 2 Clock Select bit 2
|
||
; TCCR0.CS01 1 Clock Select bit 1
|
||
; TCCR0.CS00 0 Clock Select bit 0
|
||
; MCUCSR 0x0054 MCU Control and Status Register
|
||
; MCUCSR.JTD 7 JTAG interface disable
|
||
; MCUCSR.ISC2 6 Interrupt Sense Control 2
|
||
; MCUCSR.JTRF 4 JTAG Reset Flag
|
||
; MCUCSR.WDRF 3 Watchdog Reset Flag
|
||
; MCUCSR.BORF 2 Brown-out Reset Flag
|
||
; MCUCSR.EXTRF 1 External Reset Flag
|
||
; MCUCSR.PORF 0 Power-on Reset Flag
|
||
; MCUCR 0x0055 MCU Control Register
|
||
; MCUCR.SE 7 Sleep Enable
|
||
; MCUCR.SM2 6 Sleep Mode Select Bit 2
|
||
; MCUCR.SM1 5 Sleep Mode Select Bit 1
|
||
; MCUCR.SM0 4 Sleep Mode Select Bit 0
|
||
; MCUCR.ISC11 3 Interrupt Sense Control 1 Bit 1
|
||
; MCUCR.ISC10 2 Interrupt Sense Control 1 Bit 0
|
||
; MCUCR.ISC01 1 Interrupt Sense Control 0 Bit 1
|
||
; MCUCR.ISC00 0 Interrupt Sense Control 0 Bit 0
|
||
; TWCR 0x0056 2-wire Serial Interface Control Register
|
||
; TWCR.TWINT 7 2-wire Serial Interface Interrupt Flag
|
||
; TWCR.TWEA 6 2-wire Serial Interface Enable Acknowledge Flag
|
||
; TWCR.TWSTA 5 2-wire Serial Bus START Condition Flag
|
||
; TWCR.TWSTO 4 2-wire Serial Bus STOP Condition Flag
|
||
; TWCR.TWWC 3 2-wire Serial Bus Write Collision Flag
|
||
; TWCR.TWEN 2 2-wire Serial Interface Enable Bit
|
||
; TWCR.TWIE 0 2-wire Serial Interface Interrupt Enable
|
||
; SPMCR 0x0057 Store Program Memory Control Register
|
||
; SPMCR.ASB 6 Application Section Busy
|
||
; SPMCR.ASRE 4 Application Section Read Enable
|
||
; SPMCR.BLBSET 3 Boot Lock Bit Set
|
||
; SPMCR.PGWRT 2 Page Write
|
||
; SPMCR.PGERS 1 Page Erase
|
||
; SPMCR.SPMEN 0 Store Program Memory Enable
|
||
; TIFR 0x0058 Timer/Counter Interrupt Flag Register
|
||
; TIFR.OCF2 7 Output Compare Flag 2
|
||
; TIFR.TOV2 6 Timer/Counter2 Overflow Flag
|
||
; TIFR.ICF1 5 Input Capture Flag 1
|
||
; TIFR.OCF1A 4 Output Compare Flag 1A
|
||
; TIFR.OCF1B 3 Output Compare Flag 1B
|
||
; TIFR.TOV1 2 Timer/Counter1 Overflow Flag
|
||
; TIFR.OCF0 1 Output Compare Flag 0
|
||
; TIFR.TOV0 0 Timer/Counter0 Overflow Flag
|
||
; TIMSK 0x0059 Timer/Counter Interrupt Flag Register
|
||
; TIMSK.OCF2 7 Output Compare Flag 2
|
||
; TIMSK.TOV2 6 Timer/Counter2 Overflow Flag
|
||
; TIMSK.ICF1 5 Input Capture Flag 1
|
||
; TIMSK.OCF1A 4 Output Compare Flag 1A
|
||
; TIMSK.OCF1B 3 Output Compare Flag 1B
|
||
; TIMSK.TOV1 2 Timer/Counter1 Overflow Flag
|
||
; TIMSK.OCF0 1 Output Compare Flag 0
|
||
; TIMSK.TOV0 0 Timer/Counter0 Overflow Flag
|
||
; GIFR 0x005A General Interrupt Flag Register
|
||
; GIFR.INTF1 7 External Interrupt Flag1
|
||
; GIFR.INTF0 6 External Interrupt Flag0
|
||
; GIFR.INTF2 5 External Interrupt Flag2
|
||
; GICR 0x005B General Interrupt Control Register
|
||
; GICR.INT1 7 External Interrupt Request 1 Enable
|
||
; GICR.INT0 6 External Interrupt Request 0 Enable
|
||
; GICR.INT2 5 External Interrupt Request 2 Enable
|
||
; GICR.IVSEL 1 Interrupt Vector Select
|
||
; GICR.IVCE 0 Interrupt Vector Change Enable
|
||
; OCR0 0x005C Timer/Counter0 Output Compare Register
|
||
; SPL 0x005D Stack Pointer Low
|
||
; SPL.SP7 7
|
||
; SPL.SP6 6
|
||
; SPL.SP5 5
|
||
; SPL.SP4 4
|
||
; SPL.SP3 3
|
||
; SPL.SP2 2
|
||
; SPL.SP1 1
|
||
; SPL.SP0 0
|
||
; SPH 0x005E Stack Pointer High
|
||
; SPH.SP11 11
|
||
; SPH.SP10 10
|
||
; SPH.SP9 9
|
||
; SPH.SP8 8
|
||
; SREG 0x005F Status Register
|
||
; SREG.I 7 Global Interrupt Enable
|
||
; SREG.T 6 Bit Copy Storage
|
||
; SREG.H 5 Half Carry Flag
|
||
; SREG.S 4 Sign Bit
|
||
; SREG.V 3 Two's Complement Overflow Flag
|
||
; SREG.N 2 Negative Flag
|
||
; SREG.Z 1 Zero Flag
|
||
; SREG.C 0 Carry Flag
|
||
|
||
|
||
.ATmega32_L
|
||
SUBARCH=5
|
||
; doc2503.pdf
|
||
;
|
||
|
||
RAM=2048
|
||
ROM=32768
|
||
EEPROM=1024
|
||
|
||
; MEMORY MAP
|
||
|
||
|
||
; Interrupt and reset vector assignments
|
||
entry __RESET 0x0000 External Pin, Power-on Reset, Brown-out
|
||
entry INT0_ 0x0002 External Interrupt Request 0
|
||
entry INT1_ 0x0004 External Interrupt Request 1
|
||
entry INT2_ 0x0006 External Interrupt Request 2
|
||
entry TIMER2_COMP 0x0008 Timer/Counter2 Compare Match
|
||
entry TIMER2_OVF 0x000A Timer/Counter2 Overflow
|
||
entry TIMER1_CAPT 0x000C Timer/Counter1 Capture Event
|
||
entry TIMER1_COMPA 0x000E Timer/Counter1 Compare Match A
|
||
entry TIMER1_COMPB 0x0010 Timer/Counter1 Compare Match B
|
||
entry TIMER1_OVF 0x0012 Timer/Counter1 Overflow
|
||
entry TIMER0_COMP 0x0014 Timer/Counter0 Compare Match
|
||
entry TIMER0_OVF 0x0016 Timer/Counter0 Overflow
|
||
entry SPI_STC 0x0018 Serial Transfer Complete
|
||
entry USART_RXC 0x001A USART, Rx Complete
|
||
entry USART_UDRE 0x001C USART Data Register Empty
|
||
entry USART_TXC 0x001E USART, Tx Complete
|
||
entry ADC_ 0x0020 ADC Conversion Complete
|
||
entry EE_RDY 0x0022 EEPROM Ready
|
||
entry ANA_COMP 0x0024 Analog Comparator
|
||
entry TWI_ 0x0026 Two-wire Serial Interface
|
||
entry SPM_RDY 0x0028 Store Program Memory Ready
|
||
|
||
|
||
; INPUT/OUTPUT PORTS
|
||
TWBR 0x0000 Two-wire Serial Interface Bit Rate Register
|
||
TWBR.TWBR7 7 TWI Bit Rate Register bit 7
|
||
TWBR.TWBR6 6 TWI Bit Rate Register bit 6
|
||
TWBR.TWBR5 5 TWI Bit Rate Register bit 5
|
||
TWBR.TWBR4 4 TWI Bit Rate Register bit 4
|
||
TWBR.TWBR3 3 TWI Bit Rate Register bit 3
|
||
TWBR.TWBR2 2 TWI Bit Rate Register bit 2
|
||
TWBR.TWBR1 1 TWI Bit Rate Register bit 1
|
||
TWBR.TWBR0 0 TWI Bit Rate Register bit 0
|
||
TWSR 0x0001 TWI Status Register
|
||
TWSR.TWS7 7 TWI Status 7
|
||
TWSR.TWS6 6 TWI Status 6
|
||
TWSR.TWS5 5 TWI Status 5
|
||
TWSR.TWS4 4 TWI Status 4
|
||
TWSR.TWS3 3 TWI Status 3
|
||
TWSR.TWS1 1 TWI Prescaler Bit 1
|
||
TWSR.TWS0 0 TWI Prescaler Bit 0
|
||
TWAR 0x0002 TWI (Slave) Address Register
|
||
TWAR.TWA6 7 TWI (Slave) Address Register bit 6
|
||
TWAR.TWA5 6 TWI (Slave) Address Register bit 5
|
||
TWAR.TWA4 5 TWI (Slave) Address Register bit 4
|
||
TWAR.TWA3 4 TWI (Slave) Address Register bit 3
|
||
TWAR.TWA2 3 TWI (Slave) Address Register bit 2
|
||
TWAR.TWA1 2 TWI (Slave) Address Register bit 1
|
||
TWAR.TWA0 1 TWI (Slave) Address Register bit 0
|
||
TWAR.TWGCE 0 TWI General Call Recognition Enable Bit
|
||
TWDR 0x0003 TWI Data Register
|
||
TWDR.TWD7 7 TWI Data Register bit 7
|
||
TWDR.TWD6 6 TWI Data Register bit 6
|
||
TWDR.TWD5 5 TWI Data Register bit 5
|
||
TWDR.TWD4 4 TWI Data Register bit 4
|
||
TWDR.TWD3 3 TWI Data Register bit 3
|
||
TWDR.TWD2 2 TWI Data Register bit 2
|
||
TWDR.TWD1 1 TWI Data Register bit 1
|
||
TWDR.TWD0 0 TWI Data Register bit 0
|
||
ADCL 0x0004 The ADC Data Register Low (ADLAR = 0)
|
||
ADCL.ADC7 7 ADC Conversion result 7
|
||
ADCL.ADC6 6 ADC Conversion result 6
|
||
ADCL.ADC5 5 ADC Conversion result 5
|
||
ADCL.ADC4 4 ADC Conversion result 4
|
||
ADCL.ADC3 3 ADC Conversion result 3
|
||
ADCL.ADC2 2 ADC Conversion result 2
|
||
ADCL.ADC1 1 ADC Conversion result 1
|
||
ADCL.ADC0 0 ADC Conversion result 0
|
||
ADCH 0x0005 The ADC Data Register High (ADLAR = 0)
|
||
ADCH.ADC9 9 ADC Conversion result 9
|
||
ADCH.ADC8 8 ADC Conversion result 8
|
||
; ADCL 0x0004 The ADC Data Register Low (ADLAR = 1)
|
||
; ADCL.ADC1 7 ADC Conversion result 1
|
||
; ADCL.ADC0 6 ADC Conversion result 0
|
||
; ADCH 0x0005 The ADC Data Register High (ADLAR = 1)
|
||
; ADCH.ADC9 15 ADC Conversion result 9
|
||
; ADCH.ADC8 14 ADC Conversion result 8
|
||
; ADCH.ADC7 13 ADC Conversion result 7
|
||
; ADCH.ADC6 12 ADC Conversion result 6
|
||
; ADCH.ADC5 11 ADC Conversion result 5
|
||
; ADCH.ADC4 10 ADC Conversion result 4
|
||
; ADCH.ADC3 9 ADC Conversion result 3
|
||
; ADCH.ADC2 8 ADC Conversion result 2
|
||
ADCSRA 0x0006 ADC Control and Status Register A
|
||
ADCSRA.ADEN 7 ADC Enable
|
||
ADCSRA.ADSC 6 ADC Start Conversion
|
||
ADCSRA.ADATE 5 ADC Auto Trigger Enable
|
||
ADCSRA.ADIF 4 ADC Interrupt Flag
|
||
ADCSRA.ADIE 3 ADC Interrupt Enable
|
||
ADCSRA.ADPS2 2 ADC Prescaler Select Bit 2
|
||
ADCSRA.ADPS1 1 ADC Prescaler Select Bit 1
|
||
ADCSRA.ADPS0 0 ADC Prescaler Select Bit 0
|
||
ADMUX 0x0007 ADC Multiplexer Selection Register
|
||
ADMUX.REFS1 7 Reference Selection Bit
|
||
ADMUX.REFS0 6 Reference Selection Bit
|
||
ADMUX.ADLAR 5 ADC Left Adjust Result
|
||
ADMUX.MUX4 4 Analog Channel and Gain Selection Bit 4
|
||
ADMUX.MUX3 3 Analog Channel and Gain Selection Bit 3
|
||
ADMUX.MUX2 2 Analog Channel and Gain Selection Bit 2
|
||
ADMUX.MUX1 1 Analog Channel and Gain Selection Bit 1
|
||
ADMUX.MUX0 0 Analog Channel and Gain Selection Bit 0
|
||
ACSR 0x0008 Analog Comparator Control and Status Register
|
||
ACSR.ACD 7 Analog Comparator Disable
|
||
ACSR.ACBG 6 Analog Comparator Bandgap Select
|
||
ACSR.ACO 5 Analog Comparator Output
|
||
ACSR.ACI 4 Analog Comparator Interrupt Flag
|
||
ACSR.ACIE 3 Analog Comparator Interrupt Enable
|
||
ACSR.ACIC 2 Analog Comparator Input Capture Enable
|
||
ACSR.ACIS1 1 Analog Comparator Interrupt Mode Select 1
|
||
ACSR.ACIS0 0 Analog Comparator Interrupt Mode Select 0
|
||
UBRRL 0x0009 USART Baud Rate Register Low
|
||
UBRRL.UBRR7 7 USART Baud Rate Register bit 7
|
||
UBRRL.UBRR6 6 USART Baud Rate Register bit 6
|
||
UBRRL.UBRR5 5 USART Baud Rate Register bit 5
|
||
UBRRL.UBRR4 4 USART Baud Rate Register bit 4
|
||
UBRRL.UBRR3 3 USART Baud Rate Register bit 3
|
||
UBRRL.UBRR2 2 USART Baud Rate Register bit 2
|
||
UBRRL.UBRR1 1 USART Baud Rate Register bit 1
|
||
UBRRL.UBRR0 0 USART Baud Rate Register bit 0
|
||
UCSRB 0x000A USART Control and Status Register B
|
||
UCSRB.RXCIE 7 RX Complete Interrupt Enable
|
||
UCSRB.TXCIE 6 TX Complete Interrupt Enable
|
||
UCSRB.UDRIE 5 USART Data Register Empty Interrupt Enable
|
||
UCSRB.RXEN 4 Receiver Enable
|
||
UCSRB.TXEN 3 Transmitter Enable
|
||
UCSRB.UCSZ2 2 Character Size
|
||
UCSRB.RXB8 1 Receive Data Bit 8
|
||
UCSRB.TXB8 0 Transmit Data Bit 8
|
||
UCSRA 0x000B USART Control and Status Register A
|
||
UCSRA.RXC 7 USART Receive Complete
|
||
UCSRA.TXC 6 USART Transmit Complete
|
||
UCSRA.UDRE 5 USART Data Register Empty
|
||
UCSRA.FE 4 Frame Error
|
||
UCSRA.DOR 3 Data OverRun
|
||
UCSRA.PE 2 Parity Error
|
||
UCSRA.U2X 1 Double the USART Transmission Speed
|
||
UCSRA.MPCM 0 Multi-processor Communication Mode
|
||
UDR 0x000C USART I/O Data Register
|
||
SPCR 0x000D SPI Control Register
|
||
SPCR.SPIE 7 SPI Interrupt Enable
|
||
SPCR.SPE 6 SPI Enable
|
||
SPCR.DORD 5 Data Order
|
||
SPCR.MSTR 4 Master/Slave Select
|
||
SPCR.CPOL 3 Clock Polarity
|
||
SPCR.CPHA 2 Clock Phase
|
||
SPCR.SPR1 1 SPI Clock Rate Select 1
|
||
SPCR.SPR0 0 SPI Clock Rate Select 0
|
||
SPSR 0x000E SPI Status Register
|
||
SPSR.SPIF 7 SPI Interrupt Flag
|
||
SPSR.WCOL 6 Write COLlision flag
|
||
SPSR.SPI2X 0 Double SPI Speed Bit
|
||
SPDR 0x000F SPI Data Register
|
||
PIND 0x0010 Port D Input Pins Address
|
||
PIND.PIND7 7
|
||
PIND.PIND6 6
|
||
PIND.PIND5 5
|
||
PIND.PIND4 4
|
||
PIND.PIND3 3
|
||
PIND.PIND2 2
|
||
PIND.PIND1 1
|
||
PIND.PIND0 0
|
||
DDRD 0x0011 Port D Data Direction Register
|
||
DDRD.DDD7 7 Port D Data Direction Register bit 7
|
||
DDRD.DDD6 6 Port D Data Direction Register bit 6
|
||
DDRD.DDD5 5 Port D Data Direction Register bit 5
|
||
DDRD.DDD4 4 Port D Data Direction Register bit 4
|
||
DDRD.DDD3 3 Port D Data Direction Register bit 3
|
||
DDRD.DDD2 2 Port D Data Direction Register bit 2
|
||
DDRD.DDD1 1 Port D Data Direction Register bit 1
|
||
DDRD.DDD0 0 Port D Data Direction Register bit 0
|
||
PORTD 0x0012 Port D Data Register
|
||
PORTD.PORTD7 7 Port D Data Register bit 7
|
||
PORTD.PORTD6 6 Port D Data Register bit 6
|
||
PORTD.PORTD5 5 Port D Data Register bit 5
|
||
PORTD.PORTD4 4 Port D Data Register bit 4
|
||
PORTD.PORTD3 3 Port D Data Register bit 3
|
||
PORTD.PORTD2 2 Port D Data Register bit 2
|
||
PORTD.PORTD1 1 Port D Data Register bit 1
|
||
PORTD.PORTD0 0 Port D Data Register bit 0
|
||
PINC 0x0013 Port C Input Pins Address
|
||
PINC.PINC7 7
|
||
PINC.PINC6 6
|
||
PINC.PINC5 5
|
||
PINC.PINC4 4
|
||
PINC.PINC3 3
|
||
PINC.PINC2 2
|
||
PINC.PINC1 1
|
||
PINC.PINC0 0
|
||
DDRC 0x0014 Port C Data Direction Register
|
||
DDRC.DDC7 7 Port C Data Direction Register bit 7
|
||
DDRC.DDC6 6 Port C Data Direction Register bit 6
|
||
DDRC.DDC5 5 Port C Data Direction Register bit 5
|
||
DDRC.DDC4 4 Port C Data Direction Register bit 4
|
||
DDRC.DDC3 3 Port C Data Direction Register bit 3
|
||
DDRC.DDC2 2 Port C Data Direction Register bit 2
|
||
DDRC.DDC1 1 Port C Data Direction Register bit 1
|
||
DDRC.DDC0 0 Port C Data Direction Register bit 0
|
||
PORTC 0x0015 Port C Data Register
|
||
PORTC.PORTC7 7 Port C Data Register bit 7
|
||
PORTC.PORTC6 6 Port C Data Register bit 6
|
||
PORTC.PORTC5 5 Port C Data Register bit 5
|
||
PORTC.PORTC4 4 Port C Data Register bit 4
|
||
PORTC.PORTC3 3 Port C Data Register bit 3
|
||
PORTC.PORTC2 2 Port C Data Register bit 2
|
||
PORTC.PORTC1 1 Port C Data Register bit 1
|
||
PORTC.PORTC0 0 Port C Data Register bit 0
|
||
PINB 0x0016 Port B Input Pins Address
|
||
PINB.PINB7 7
|
||
PINB.PINB6 6
|
||
PINB.PINB5 5
|
||
PINB.PINB4 4
|
||
PINB.PINB3 3
|
||
PINB.PINB2 2
|
||
PINB.PINB1 1
|
||
PINB.PINB0 0
|
||
DDRB 0x0017 Port B Data Direction Register
|
||
DDRB.DDB7 7 Port B Data Direction Register bit 7
|
||
DDRB.DDB6 6 Port B Data Direction Register bit 6
|
||
DDRB.DDB5 5 Port B Data Direction Register bit 5
|
||
DDRB.DDB4 4 Port B Data Direction Register bit 4
|
||
DDRB.DDB3 3 Port B Data Direction Register bit 3
|
||
DDRB.DDB2 2 Port B Data Direction Register bit 2
|
||
DDRB.DDB1 1 Port B Data Direction Register bit 1
|
||
DDRB.DDB0 0 Port B Data Direction Register bit 0
|
||
PORTB 0x0018 Port B Data Register
|
||
PORTB.PORTB7 7 Port B Data Register bit 7
|
||
PORTB.PORTB6 6 Port B Data Register bit 6
|
||
PORTB.PORTB5 5 Port B Data Register bit 5
|
||
PORTB.PORTB4 4 Port B Data Register bit 4
|
||
PORTB.PORTB3 3 Port B Data Register bit 3
|
||
PORTB.PORTB2 2 Port B Data Register bit 2
|
||
PORTB.PORTB1 1 Port B Data Register bit 1
|
||
PORTB.PORTB0 0 Port B Data Register bit 0
|
||
PINA 0x0019 Port A Input Pins Address
|
||
PINA.PINA7 7
|
||
PINA.PINA6 6
|
||
PINA.PINA5 5
|
||
PINA.PINA4 4
|
||
PINA.PINA3 3
|
||
PINA.PINA2 2
|
||
PINA.PINA1 1
|
||
PINA.PINA0 0
|
||
DDRA 0x001A Port A Data Direction Register
|
||
DDRA.DDA7 7 Port A Data Direction Register bit 7
|
||
DDRA.DDA6 6 Port A Data Direction Register bit 6
|
||
DDRA.DDA5 5 Port A Data Direction Register bit 5
|
||
DDRA.DDA4 4 Port A Data Direction Register bit 4
|
||
DDRA.DDA3 3 Port A Data Direction Register bit 3
|
||
DDRA.DDA2 2 Port A Data Direction Register bit 2
|
||
DDRA.DDA1 1 Port A Data Direction Register bit 1
|
||
DDRA.DDA0 0 Port A Data Direction Register bit 0
|
||
PORTA 0x001B Port A Data Register
|
||
PORTA.PORTA7 7 Port A Data Register bit 7
|
||
PORTA.PORTA6 6 Port A Data Register bit 6
|
||
PORTA.PORTA5 5 Port A Data Register bit 5
|
||
PORTA.PORTA4 4 Port A Data Register bit 4
|
||
PORTA.PORTA3 3 Port A Data Register bit 3
|
||
PORTA.PORTA2 2 Port A Data Register bit 2
|
||
PORTA.PORTA1 1 Port A Data Register bit 1
|
||
PORTA.PORTA0 0 Port A Data Register bit 0
|
||
EECR 0x001C The EEPROM Control Register
|
||
EECR.EERIE 3 EEPROM Ready Interrupt Enable
|
||
EECR.EEMWE 2 EEPROM Master Write Enable
|
||
EECR.EEWE 1 EEPROM Write Enable
|
||
EECR.EERE 0 EEPROM Read Enable
|
||
EEDR 0x001D The EEPROM Data Register
|
||
SPSR 0x001E SPI Status Register
|
||
;SPSR.SPIF 7 SPI Interrupt Flag
|
||
;SPSR.WCOL 6 Write COLlision flag
|
||
;SPSR.SPI2X 0 Double SPI Speed Bit
|
||
EEARH 0x001F EEPROM Address Register High
|
||
EEARH.EEAR9 9 EEPROM Addres 9
|
||
EEARH.EEAR8 8 EEPROM Addres 8
|
||
UCSRC 0x0020 USART Control and Status Register C (page 155)
|
||
UCSRC.URSEL 7 Register Select
|
||
UCSRC.UMSEL 6 USART Mode Select
|
||
UCSRC.UPM1 5 Parity Mode 1
|
||
UCSRC.UPM0 4 Parity Mode 0
|
||
UCSRC.USBS 3 Stop Bit Select
|
||
UCSRC.UCSZ1 2 Character Size 1
|
||
UCSRC.UCSZ0 1 Character Size 0
|
||
UCSRC.UCPOL 0 Clock Polarity
|
||
; UBRRH 0x0020 USART Baud Rate Register (page 155)
|
||
; URSEL 15 Register Select
|
||
; UBRR11 11 USART Baud Rate Register bit 11
|
||
; UBRR10 10 USART Baud Rate Register bit 10
|
||
; UBRR9 9 USART Baud Rate Register bit 9
|
||
; UBRR8 8 USART Baud Rate Register bit 8
|
||
WDTCR 0x0021 Watchdog Timer Control Register
|
||
WDTCR.WDTOE 4 Watchdog Turn-off Enable
|
||
WDTCR.WDE 3 Watchdog Enable
|
||
WDTCR.WDP2 2 Watchdog Timer Prescaler 2
|
||
WDTCR.WDP1 1 Watchdog Timer Prescaler 1
|
||
WDTCR.WDP0 9 Watchdog Timer Prescaler 9
|
||
ASSR 0x0022 Asynchronous Status Register
|
||
ASSR.AS2 3 Asynchronous Timer/Counter2
|
||
ASSR.TCN2UB 2 Timer/Counter2 Update Busy
|
||
ASSR.OCR2UB 1 Output Compare Register2 Update Busy
|
||
ASSR.TCR2UB 0 Timer/Counter Control Register2 Update Busy
|
||
OCR2 0x0023 Timer/Counter2 Output Compare Register
|
||
TCNT2 0x0024 Timer/Counter Register
|
||
TCNT2.TCNT2_7 7
|
||
TCNT2.TCNT2_6 6
|
||
TCNT2.TCNT2_5 5
|
||
TCNT2.TCNT2_4 4
|
||
TCNT2.TCNT2_3 3
|
||
TCNT2.TCNT2_2 2
|
||
TCNT2.TCNT2_1 1
|
||
TCNT2.TCNT2_0 0
|
||
TCCR2 0x0025 Timer/Counter Control Register
|
||
TCCR2.FOC2 7 Force Output Compare
|
||
TCCR2.WGM20 6 Waveform Generation Mode 0
|
||
TCCR2.COM21 5 Compare Match Output Mode 1
|
||
TCCR2.COM20 4 Compare Match Output Mode 0
|
||
TCCR2.WGM21 3 Waveform Generation Mode 1
|
||
TCCR2.CS22 2 Clock Select 2
|
||
TCCR2.CS21 1 Clock Select 1
|
||
TCCR2.CS20 0 Clock Select 0
|
||
ICR1L 0x0026 Input Capture Register Low Byte
|
||
ICR1H 0x0027 Input Capture Register High Byte
|
||
OCR1BL 0x0028 Output Compare Register B Low Byte
|
||
OCR1BH 0x0029 Output Compare Register B High Byte
|
||
OCR1AL 0x002A Output Compare Register A Low Byte
|
||
OCR1AH 0x002B Output Compare Register A High Byte
|
||
TCNT1L 0x002C Counter Register Low Byte
|
||
TCNT1H 0x002D Counter Register High Byte
|
||
TCCR1B 0x002E Timer/Counter1 Control Register B
|
||
TCCR1B.ICNC1 7 Input Capture Noise Canceler
|
||
TCCR1B.ICES1 6 Input Capture Edge Select
|
||
TCCR1B.WGM13 4 Waveform Generation Mode 3
|
||
TCCR1B.WGM12 3 Waveform Generation Mode 2
|
||
TCCR1B.CS12 2 Clock Select 2
|
||
TCCR1B.CS11 1 Clock Select 1
|
||
TCCR1B.CS10 0 Clock Select 0
|
||
TCCR1A 0x002F Timer/Counter1 Control Register A
|
||
TCCR1A.COM1A1 7 Compare Output Mode for Channel A 1
|
||
TCCR1A.COM1A0 6 Compare Output Mode for Channel A 0
|
||
TCCR1A.COM1B1 5 Compare Output Mode for Channel B 1
|
||
TCCR1A.COM1B0 4 Compare Output Mode for Channel B 0
|
||
TCCR1A.FOC1A 3 Force Output Compare for Channel A
|
||
TCCR1A.FOC1B 2 Force Output Compare for Channel B
|
||
TCCR1A.WGM11 1 Waveform Generation Mode 1
|
||
TCCR1A.WGM10 0 Waveform Generation Mode 0
|
||
SFIOR 0x0030 Special Function I/O Register
|
||
SFIOR.ADTS2 7 ADC Auto Trigger Source 2
|
||
SFIOR.ADTS1 6 ADC Auto Trigger Source 1
|
||
SFIOR.ADTS0 5 ADC Auto Trigger Source 0
|
||
SFIOR.ADHSM 4 ADC High Speed Mode
|
||
SFIOR.ACME 3 Analog Comparator Multiplexer Enable
|
||
SFIOR.PUD 2 Pull-up disable
|
||
SFIOR.PSR2 1 Prescaler Reset Timer/Counter2
|
||
SFIOR.PSR10 0 Prescaler Reset Timer/Counter1 and Timer/Counter0
|
||
OCDR 0x0031 On-Chip Debug Register
|
||
; OSCCAL 0x0031 Oscillator Calibration Register
|
||
; OSCCAL.CAL7 7 Oscillator Calibration Value 7
|
||
; OSCCAL.CAL6 6 Oscillator Calibration Value 6
|
||
; OSCCAL.CAL5 5 Oscillator Calibration Value 5
|
||
; OSCCAL.CAL4 4 Oscillator Calibration Value 4
|
||
; OSCCAL.CAL3 3 Oscillator Calibration Value 3
|
||
; OSCCAL.CAL2 2 Oscillator Calibration Value 2
|
||
; OSCCAL.CAL1 1 Oscillator Calibration Value 1
|
||
; OSCCAL.CAL0 0 Oscillator Calibration Value 0
|
||
TCNT0 0x0032 Timer/Counter Register
|
||
TCNT0.TCNT0_7 7
|
||
TCNT0.TCNT0_6 6
|
||
TCNT0.TCNT0_5 5
|
||
TCNT0.TCNT0_4 4
|
||
TCNT0.TCNT0_3 3
|
||
TCNT0.TCNT0_2 2
|
||
TCNT0.TCNT0_1 1
|
||
TCNT0.TCNT0_0 0
|
||
TCCR0 0x0033 Timer/Counter Control Register
|
||
TCCR0.FOC0 7 Force Output Compare
|
||
TCCR0.WGM00 6 Waveform Generation Mode 0
|
||
TCCR0.COM01 5 Compare Match Output Mode 1
|
||
TCCR0.COM00 4 Compare Match Output Mode 0
|
||
TCCR0.WGM01 3 Waveform Generation Mode 1
|
||
TCCR0.CS02 2 Clock Select 2
|
||
TCCR0.CS01 1 Clock Select 1
|
||
TCCR0.CS00 0 Clock Select 0
|
||
MCUCSR 0x0034 MCU Control and Status Register
|
||
MCUCSR.JTD 7 JTAG Interface Disable
|
||
MCUCSR.ISC2 6 Interrupt Sense Control 2
|
||
MCUCSR.JTRF 4 JTAG Reset Flag
|
||
MCUCSR.WDRF 3 Watchdog Reset Flag
|
||
MCUCSR.BORF 2 Brown-out Reset Flag
|
||
MCUCSR.EXTRF 1 External Reset Flag
|
||
MCUCSR.PORF 0 Power-on Reset Flag
|
||
MCUCR 0x0035 MCU Control Register
|
||
MCUCR.SE 7 Sleep Enable
|
||
MCUCR.SM2 6 Sleep Mode Select Bit 2
|
||
MCUCR.SM1 5 Sleep Mode Select Bit 1
|
||
MCUCR.SM0 4 Sleep Mode Select Bit 0
|
||
MCUCR.ISC11 3 Interrupt Sense Control 1 Bit 1
|
||
MCUCR.ISC10 2 Interrupt Sense Control 1 Bit 0
|
||
MCUCR.ISC01 1 Interrupt Sense Control 0 Bit 1
|
||
MCUCR.ISC00 0 CInterrupt Sense Control 0 Bit 0
|
||
TWCR 0x0036 TWI Control Register
|
||
TWCR.TWINT 7 TWI Interrupt Flag
|
||
TWCR.TWEA 6 TWI Enable Acknowledge Bit
|
||
TWCR.TWSTA 5 TWI START Condition Bit
|
||
TWCR.TWSTO 4 TWI STOP Condition Bit
|
||
TWCR.TWWC 3 TWI Write Collision Flag
|
||
TWCR.TWEN 2 TWI Enable Bit
|
||
TWCR.TWIE 0 TWI Interrupt Enable
|
||
SPMCR 0x0037 Store Program Memory Control Register
|
||
SPMCR.SPMIE 7 SPM Interrupt Enable
|
||
SPMCR.RWWSB 6 Read-While-Write Section Busy
|
||
SPMCR.RWWSRE 4 Read-While-Write Section Read Enable
|
||
SPMCR.BLBSET 3 Boot Lock Bit Set
|
||
SPMCR.PGWRT 2 Page Write
|
||
SPMCR.PGERS 1 Page Erase
|
||
SPMCR.SPMEN 0 Store Program Memory Enable
|
||
TIFR 0x0038 Timer/Counter Interrupt Flag Register
|
||
TIFR.OCF2 7 Output Compare Flag 2
|
||
TIFR.TOV2 6 Timer/Counter2 Overflow Flag
|
||
TIFR.ICF1 5 Timer/Counter1, Input Capture Flag
|
||
TIFR.OCF1A 4 Timer/Counter1, Output Compare A Match Flag
|
||
TIFR.OCF1B 3 Timer/Counter1, Output Compare B Match Flag
|
||
TIFR.TOV1 2 Timer/Counter1, Overflow Flag
|
||
TIFR.OCF0 1 Output Compare Flag 0
|
||
TIFR.TOV0 0 Timer/Counter0 Overflow Flag
|
||
TIMSK 0x0039 Timer/Counter Interrupt Mask Register
|
||
TIMSK.OCIE2 7 Timer/Counter2 Output Compare Match Interrupt Enable
|
||
TIMSK.TOIE2 6 Timer/Counter2 Overflow Interrupt Enable
|
||
TIMSK.TICIE1 5 Timer/Counter1, Input Capture Interrupt Enable
|
||
TIMSK.OCIE1A 4 Timer/Counter1, Output Compare A Match Interrupt Enable
|
||
TIMSK.OCIE1B 3 Timer/Counter1, Output Compare B Match Interrupt Enable
|
||
TIMSK.TOIE1 2 Timer/Counter1, Overflow Interrupt Enable
|
||
TIMSK.OCIE0 1 Timer/Counter0 Output Compare Match Interrupt Enable
|
||
TIMSK.TOIE0 0 Timer/Counter0 Overflow Interrupt Enable
|
||
GIFR 0x003A General Interrupt Flag Register
|
||
GIFR.INTF1 7 External Interrupt Flag 1
|
||
GIFR.INTF0 6 External Interrupt Flag 0
|
||
GIFR.INTF2 5 External Interrupt Flag 2
|
||
GICR 0x003B General Interrupt Control
|
||
GICR.INT1 7 External Interrupt Request 1 Enable
|
||
GICR.INT0 6 External Interrupt Request 0 Enable
|
||
GICR.INT2 5 External Interrupt Request 2 Enable
|
||
GICR.IVSEL 1 Interrupt Vector Select
|
||
GICR.IVCE 0 Interrupt Vector Change Enable
|
||
OCR0 0x003C Timer/Counter0 Output Compare Register
|
||
SPL 0x003D Stack Pointer Low
|
||
SPL.SP7 7
|
||
SPL.SP6 6
|
||
SPL.SP5 5
|
||
SPL.SP4 4
|
||
SPL.SP3 3
|
||
SPL.SP2 2
|
||
SPL.SP1 1
|
||
SPL.SP0 0
|
||
SPH 0x003E Stack Pointer High
|
||
SPH.SP15 15
|
||
SPH.SP14 14
|
||
SPH.SP13 13
|
||
SPH.SP12 12
|
||
SPH.SP11 11
|
||
SPH.SP10 10
|
||
SPH.SP9 9
|
||
SPH.SP8 8
|
||
SREG 0x003F Status Register
|
||
SREG.I 7 Global Interrupt Enable
|
||
SREG.T 6 Bit Copy Storage
|
||
SREG.H 5 Half Carry Flag
|
||
SREG.S 4 Sign Bit
|
||
SREG.V 3 Two's Complement Overflow Flag
|
||
SREG.N 2 Negative Flag
|
||
SREG.Z 1 Zero Flag
|
||
SREG.C 0 Carry Flag
|
||
|
||
; TWBR 0x0020 Two-wire Serial Interface Bit Rate Register
|
||
; TWBR.TWBR7 7 TWI Bit Rate Register bit 7
|
||
; TWBR.TWBR6 6 TWI Bit Rate Register bit 6
|
||
; TWBR.TWBR5 5 TWI Bit Rate Register bit 5
|
||
; TWBR.TWBR4 4 TWI Bit Rate Register bit 4
|
||
; TWBR.TWBR3 3 TWI Bit Rate Register bit 3
|
||
; TWBR.TWBR2 2 TWI Bit Rate Register bit 2
|
||
; TWBR.TWBR1 1 TWI Bit Rate Register bit 1
|
||
; TWBR.TWBR0 0 TWI Bit Rate Register bit 0
|
||
; TWSR 0x0021 TWI Status Register
|
||
; TWSR.TWS7 7 TWI Status 7
|
||
; TWSR.TWS6 6 TWI Status 6
|
||
; TWSR.TWS5 5 TWI Status 5
|
||
; TWSR.TWS4 4 TWI Status 4
|
||
; TWSR.TWS3 3 TWI Status 3
|
||
; TWSR.TWS1 1 TWI Prescaler Bit 1
|
||
; TWSR.TWS0 0 TWI Prescaler Bit 0
|
||
; TWAR 0x0022 TWI (Slave) Address Register
|
||
; TWAR.TWA6 7 TWI (Slave) Address Register bit 6
|
||
; TWAR.TWA5 6 TWI (Slave) Address Register bit 5
|
||
; TWAR.TWA4 5 TWI (Slave) Address Register bit 4
|
||
; TWAR.TWA3 4 TWI (Slave) Address Register bit 3
|
||
; TWAR.TWA2 3 TWI (Slave) Address Register bit 2
|
||
; TWAR.TWA1 2 TWI (Slave) Address Register bit 1
|
||
; TWAR.TWA0 1 TWI (Slave) Address Register bit 0
|
||
; TWAR.TWGCE 0 TWI General Call Recognition Enable Bit
|
||
; TWDR 0x0023 TWI Data Register
|
||
; TWDR.TWD7 7 TWI Data Register bit 7
|
||
; TWDR.TWD6 6 TWI Data Register bit 6
|
||
; TWDR.TWD5 5 TWI Data Register bit 5
|
||
; TWDR.TWD4 4 TWI Data Register bit 4
|
||
; TWDR.TWD3 3 TWI Data Register bit 3
|
||
; TWDR.TWD2 2 TWI Data Register bit 2
|
||
; TWDR.TWD1 1 TWI Data Register bit 1
|
||
; TWDR.TWD0 0 TWI Data Register bit 0
|
||
; ADCL 0x0024 The ADC Data Register Low (ADLAR = 0)
|
||
; ADCL.ADC7 7 ADC Conversion result 7
|
||
; ADCL.ADC6 6 ADC Conversion result 6
|
||
; ADCL.ADC5 5 ADC Conversion result 5
|
||
; ADCL.ADC4 4 ADC Conversion result 4
|
||
; ADCL.ADC3 3 ADC Conversion result 3
|
||
; ADCL.ADC2 2 ADC Conversion result 2
|
||
; ADCL.ADC1 1 ADC Conversion result 1
|
||
; ADCL.ADC0 0 ADC Conversion result 0
|
||
; ADCH 0x0025 The ADC Data Register High (ADLAR = 0)
|
||
; ADCH.ADC9 9 ADC Conversion result 9
|
||
; ADCH.ADC8 8 ADC Conversion result 8
|
||
; ; ADCL 0x0024 The ADC Data Register Low (ADLAR = 1)
|
||
; ; ADCL.ADC1 7 ADC Conversion result 1
|
||
; ; ADCL.ADC0 6 ADC Conversion result 0
|
||
; ; ADCH 0x0025 The ADC Data Register High (ADLAR = 1)
|
||
; ; ADCH.ADC9 15 ADC Conversion result 9
|
||
; ; ADCH.ADC8 14 ADC Conversion result 8
|
||
; ; ADCH.ADC7 13 ADC Conversion result 7
|
||
; ; ADCH.ADC6 12 ADC Conversion result 6
|
||
; ; ADCH.ADC5 11 ADC Conversion result 5
|
||
; ; ADCH.ADC4 10 ADC Conversion result 4
|
||
; ; ADCH.ADC3 9 ADC Conversion result 3
|
||
; ; ADCH.ADC2 8 ADC Conversion result 2
|
||
; ADCSRA 0x0026 ADC Control and Status Register A
|
||
; ADCSRA.ADEN 7 ADC Enable
|
||
; ADCSRA.ADSC 6 ADC Start Conversion
|
||
; ADCSRA.ADATE 5 ADC Auto Trigger Enable
|
||
; ADCSRA.ADIF 4 ADC Interrupt Flag
|
||
; ADCSRA.ADIE 3 ADC Interrupt Enable
|
||
; ADCSRA.ADPS2 2 ADC Prescaler Select Bit 2
|
||
; ADCSRA.ADPS1 1 ADC Prescaler Select Bit 1
|
||
; ADCSRA.ADPS0 0 ADC Prescaler Select Bit 0
|
||
; ADMUX 0x0027 ADC Multiplexer Selection Register
|
||
; ADMUX.REFS1 7 Reference Selection Bit
|
||
; ADMUX.REFS0 6 Reference Selection Bit
|
||
; ADMUX.ADLAR 5 ADC Left Adjust Result
|
||
; ADMUX.MUX4 4 Analog Channel and Gain Selection Bit 4
|
||
; ADMUX.MUX3 3 Analog Channel and Gain Selection Bit 3
|
||
; ADMUX.MUX2 2 Analog Channel and Gain Selection Bit 2
|
||
; ADMUX.MUX1 1 Analog Channel and Gain Selection Bit 1
|
||
; ADMUX.MUX0 0 Analog Channel and Gain Selection Bit 0
|
||
; ACSR 0x0028 Analog Comparator Control and Status Register
|
||
; ACSR.ACD 7 Analog Comparator Disable
|
||
; ACSR.ACBG 6 Analog Comparator Bandgap Select
|
||
; ACSR.ACO 5 Analog Comparator Output
|
||
; ACSR.ACI 4 Analog Comparator Interrupt Flag
|
||
; ACSR.ACIE 3 Analog Comparator Interrupt Enable
|
||
; ACSR.ACIC 2 Analog Comparator Input Capture Enable
|
||
; ACSR.ACIS1 1 Analog Comparator Interrupt Mode Select 1
|
||
; ACSR.ACIS0 0 Analog Comparator Interrupt Mode Select 0
|
||
; UBRRL 0x0029 USART Baud Rate Register Low
|
||
; UBRRL.UBRR7 7 USART Baud Rate Register bit 7
|
||
; UBRRL.UBRR6 6 USART Baud Rate Register bit 6
|
||
; UBRRL.UBRR5 5 USART Baud Rate Register bit 5
|
||
; UBRRL.UBRR4 4 USART Baud Rate Register bit 4
|
||
; UBRRL.UBRR3 3 USART Baud Rate Register bit 3
|
||
; UBRRL.UBRR2 2 USART Baud Rate Register bit 2
|
||
; UBRRL.UBRR1 1 USART Baud Rate Register bit 1
|
||
; UBRRL.UBRR0 0 USART Baud Rate Register bit 0
|
||
; UCSRB 0x002A USART Control and Status Register B
|
||
; UCSRB.RXCIE 7 RX Complete Interrupt Enable
|
||
; UCSRB.TXCIE 6 TX Complete Interrupt Enable
|
||
; UCSRB.UDRIE 5 USART Data Register Empty Interrupt Enable
|
||
; UCSRB.RXEN 4 Receiver Enable
|
||
; UCSRB.TXEN 3 Transmitter Enable
|
||
; UCSRB.UCSZ2 2 Character Size
|
||
; UCSRB.RXB8 1 Receive Data Bit 8
|
||
; UCSRB.TXB8 0 Transmit Data Bit 8
|
||
; UCSRA 0x002B USART Control and Status Register A
|
||
; UCSRA.RXC 7 USART Receive Complete
|
||
; UCSRA.TXC 6 USART Transmit Complete
|
||
; UCSRA.UDRE 5 USART Data Register Empty
|
||
; UCSRA.FE 4 Frame Error
|
||
; UCSRA.DOR 3 Data OverRun
|
||
; UCSRA.PE 2 Parity Error
|
||
; UCSRA.U2X 1 Double the USART Transmission Speed
|
||
; UCSRA.MPCM 0 Multi-processor Communication Mode
|
||
; UDR 0x002C USART I/O Data Register
|
||
; SPCR 0x002D SPI Control Register
|
||
; SPCR.SPIE 7 SPI Interrupt Enable
|
||
; SPCR.SPE 6 SPI Enable
|
||
; SPCR.DORD 5 Data Order
|
||
; SPCR.MSTR 4 Master/Slave Select
|
||
; SPCR.CPOL 3 Clock Polarity
|
||
; SPCR.CPHA 2 Clock Phase
|
||
; SPCR.SPR1 1 SPI Clock Rate Select 1
|
||
; SPCR.SPR0 0 SPI Clock Rate Select 0
|
||
; SPSR 0x002E SPI Status Register
|
||
; SPSR.SPIF 7 SPI Interrupt Flag
|
||
; SPSR.WCOL 6 Write COLlision flag
|
||
; SPSR.SPI2X 0 Double SPI Speed Bit
|
||
; SPDR 0x002F SPI Data Register
|
||
; PIND 0x0030 Port D Input Pins Address
|
||
; PIND.PIND7 7
|
||
; PIND.PIND6 6
|
||
; PIND.PIND5 5
|
||
; PIND.PIND4 4
|
||
; PIND.PIND3 3
|
||
; PIND.PIND2 2
|
||
; PIND.PIND1 1
|
||
; PIND.PIND0 0
|
||
; DDRD 0x0031 Port D Data Direction Register
|
||
; DDRD.DDD7 7 Port D Data Direction Register bit 7
|
||
; DDRD.DDD6 6 Port D Data Direction Register bit 6
|
||
; DDRD.DDD5 5 Port D Data Direction Register bit 5
|
||
; DDRD.DDD4 4 Port D Data Direction Register bit 4
|
||
; DDRD.DDD3 3 Port D Data Direction Register bit 3
|
||
; DDRD.DDD2 2 Port D Data Direction Register bit 2
|
||
; DDRD.DDD1 1 Port D Data Direction Register bit 1
|
||
; DDRD.DDD0 0 Port D Data Direction Register bit 0
|
||
; PORTD 0x0032 Port D Data Register
|
||
; PORTD.PORTD7 7 Port D Data Register bit 7
|
||
; PORTD.PORTD6 6 Port D Data Register bit 6
|
||
; PORTD.PORTD5 5 Port D Data Register bit 5
|
||
; PORTD.PORTD4 4 Port D Data Register bit 4
|
||
; PORTD.PORTD3 3 Port D Data Register bit 3
|
||
; PORTD.PORTD2 2 Port D Data Register bit 2
|
||
; PORTD.PORTD1 1 Port D Data Register bit 1
|
||
; PORTD.PORTD0 0 Port D Data Register bit 0
|
||
; PINC 0x0033 Port C Input Pins Address
|
||
; PINC.PINC7 7
|
||
; PINC.PINC6 6
|
||
; PINC.PINC5 5
|
||
; PINC.PINC4 4
|
||
; PINC.PINC3 3
|
||
; PINC.PINC2 2
|
||
; PINC.PINC1 1
|
||
; PINC.PINC0 0
|
||
; DDRC 0x0034 Port C Data Direction Register
|
||
; DDRC.DDC7 7 Port C Data Direction Register bit 7
|
||
; DDRC.DDC6 6 Port C Data Direction Register bit 6
|
||
; DDRC.DDC5 5 Port C Data Direction Register bit 5
|
||
; DDRC.DDC4 4 Port C Data Direction Register bit 4
|
||
; DDRC.DDC3 3 Port C Data Direction Register bit 3
|
||
; DDRC.DDC2 2 Port C Data Direction Register bit 2
|
||
; DDRC.DDC1 1 Port C Data Direction Register bit 1
|
||
; DDRC.DDC0 0 Port C Data Direction Register bit 0
|
||
; PORTC 0x0035 Port C Data Register
|
||
; PORTC.PORTC7 7 Port C Data Register bit 7
|
||
; PORTC.PORTC6 6 Port C Data Register bit 6
|
||
; PORTC.PORTC5 5 Port C Data Register bit 5
|
||
; PORTC.PORTC4 4 Port C Data Register bit 4
|
||
; PORTC.PORTC3 3 Port C Data Register bit 3
|
||
; PORTC.PORTC2 2 Port C Data Register bit 2
|
||
; PORTC.PORTC1 1 Port C Data Register bit 1
|
||
; PORTC.PORTC0 0 Port C Data Register bit 0
|
||
; PINB 0x0036 Port B Input Pins Address
|
||
; PINB.PINB7 7
|
||
; PINB.PINB6 6
|
||
; PINB.PINB5 5
|
||
; PINB.PINB4 4
|
||
; PINB.PINB3 3
|
||
; PINB.PINB2 2
|
||
; PINB.PINB1 1
|
||
; PINB.PINB0 0
|
||
; DDRB 0x0037 Port B Data Direction Register
|
||
; DDRB.DDB7 7 Port B Data Direction Register bit 7
|
||
; DDRB.DDB6 6 Port B Data Direction Register bit 6
|
||
; DDRB.DDB5 5 Port B Data Direction Register bit 5
|
||
; DDRB.DDB4 4 Port B Data Direction Register bit 4
|
||
; DDRB.DDB3 3 Port B Data Direction Register bit 3
|
||
; DDRB.DDB2 2 Port B Data Direction Register bit 2
|
||
; DDRB.DDB1 1 Port B Data Direction Register bit 1
|
||
; DDRB.DDB0 0 Port B Data Direction Register bit 0
|
||
; PORTB 0x0038 Port B Data Register
|
||
; PORTB.PORTB7 7 Port B Data Register bit 7
|
||
; PORTB.PORTB6 6 Port B Data Register bit 6
|
||
; PORTB.PORTB5 5 Port B Data Register bit 5
|
||
; PORTB.PORTB4 4 Port B Data Register bit 4
|
||
; PORTB.PORTB3 3 Port B Data Register bit 3
|
||
; PORTB.PORTB2 2 Port B Data Register bit 2
|
||
; PORTB.PORTB1 1 Port B Data Register bit 1
|
||
; PORTB.PORTB0 0 Port B Data Register bit 0
|
||
; PINA 0x0039 Port A Input Pins Address
|
||
; PINA.PINA7 7
|
||
; PINA.PINA6 6
|
||
; PINA.PINA5 5
|
||
; PINA.PINA4 4
|
||
; PINA.PINA3 3
|
||
; PINA.PINA2 2
|
||
; PINA.PINA1 1
|
||
; PINA.PINA0 0
|
||
; DDRA 0x003A Port A Data Direction Register
|
||
; DDRA.DDA7 7 Port A Data Direction Register bit 7
|
||
; DDRA.DDA6 6 Port A Data Direction Register bit 6
|
||
; DDRA.DDA5 5 Port A Data Direction Register bit 5
|
||
; DDRA.DDA4 4 Port A Data Direction Register bit 4
|
||
; DDRA.DDA3 3 Port A Data Direction Register bit 3
|
||
; DDRA.DDA2 2 Port A Data Direction Register bit 2
|
||
; DDRA.DDA1 1 Port A Data Direction Register bit 1
|
||
; DDRA.DDA0 0 Port A Data Direction Register bit 0
|
||
; PORTA 0x003B Port A Data Register
|
||
; PORTA.PORTA7 7 Port A Data Register bit 7
|
||
; PORTA.PORTA6 6 Port A Data Register bit 6
|
||
; PORTA.PORTA5 5 Port A Data Register bit 5
|
||
; PORTA.PORTA4 4 Port A Data Register bit 4
|
||
; PORTA.PORTA3 3 Port A Data Register bit 3
|
||
; PORTA.PORTA2 2 Port A Data Register bit 2
|
||
; PORTA.PORTA1 1 Port A Data Register bit 1
|
||
; PORTA.PORTA0 0 Port A Data Register bit 0
|
||
; EECR 0x003C The EEPROM Control Register
|
||
; EECR.EERIE 3 EEPROM Ready Interrupt Enable
|
||
; EECR.EEMWE 2 EEPROM Master Write Enable
|
||
; EECR.EEWE 1 EEPROM Write Enable
|
||
; EECR.EERE 0 EEPROM Read Enable
|
||
; EEDR 0x003D The EEPROM Data Register
|
||
; SPSR 0x003E SPI Status Register
|
||
; SPSR.SPIF 7 SPI Interrupt Flag
|
||
; SPSR.WCOL 6 Write COLlision flag
|
||
; SPSR.SPI2X 0 Double SPI Speed Bit
|
||
; EEARH 0x003F EEPROM Address Register High
|
||
; EEARH.EEAR9 9 EEPROM Addres 9
|
||
; EEARH.EEAR8 8 EEPROM Addres 8
|
||
; UCSRC 0x0040 USART Control and Status Register C (page 155)
|
||
; UCSRC.URSEL 7 Register Select
|
||
; UCSRC.UMSEL 6 USART Mode Select
|
||
; UCSRC.UPM1 5 Parity Mode 1
|
||
; UCSRC.UPM0 4 Parity Mode 0
|
||
; UCSRC.USBS 3 Stop Bit Select
|
||
; UCSRC.UCSZ1 2 Character Size 1
|
||
; UCSRC.UCSZ0 1 Character Size 0
|
||
; UCSRC.UCPOL 0 Clock Polarity
|
||
; ; UBRRH 0x0040 USART Baud Rate Register (page 155)
|
||
; ; URSEL 15 Register Select
|
||
; ; UBRR11 11 USART Baud Rate Register bit 11
|
||
; ; UBRR10 10 USART Baud Rate Register bit 10
|
||
; ; UBRR9 9 USART Baud Rate Register bit 9
|
||
; ; UBRR8 8 USART Baud Rate Register bit 8
|
||
; WDTCR 0x0041 Watchdog Timer Control Register
|
||
; WDTCR.WDTOE 4 Watchdog Turn-off Enable
|
||
; WDTCR.WDE 3 Watchdog Enable
|
||
; WDTCR.WDP2 2 Watchdog Timer Prescaler 2
|
||
; WDTCR.WDP1 1 Watchdog Timer Prescaler 1
|
||
; WDTCR.WDP0 9 Watchdog Timer Prescaler 9
|
||
; ASSR 0x0042 Asynchronous Status Register
|
||
; ASSR.AS2 3 Asynchronous Timer/Counter2
|
||
; ASSR.TCN2UB 2 Timer/Counter2 Update Busy
|
||
; ASSR.OCR2UB 1 Output Compare Register2 Update Busy
|
||
; ASSR.TCR2UB 0 Timer/Counter Control Register2 Update Busy
|
||
; OCR2 0x0043 Timer/Counter2 Output Compare Register
|
||
; TCNT2 0x0044 Timer/Counter Register
|
||
; TCNT2.TCNT2_7 7
|
||
; TCNT2.TCNT2_6 6
|
||
; TCNT2.TCNT2_5 5
|
||
; TCNT2.TCNT2_4 4
|
||
; TCNT2.TCNT2_3 3
|
||
; TCNT2.TCNT2_2 2
|
||
; TCNT2.TCNT2_1 1
|
||
; TCNT2.TCNT2_0 0
|
||
; TCCR2 0x0045 Timer/Counter Control Register
|
||
; TCCR2.FOC2 7 Force Output Compare
|
||
; TCCR2.WGM20 6 Waveform Generation Mode 0
|
||
; TCCR2.COM21 5 Compare Match Output Mode 1
|
||
; TCCR2.COM20 4 Compare Match Output Mode 0
|
||
; TCCR2.WGM21 3 Waveform Generation Mode 1
|
||
; TCCR2.CS22 2 Clock Select 2
|
||
; TCCR2.CS21 1 Clock Select 1
|
||
; TCCR2.CS20 0 Clock Select 0
|
||
; ICR1L 0x0046 Input Capture Register Low Byte
|
||
; ICR1H 0x0047 Input Capture Register High Byte
|
||
; OCR1BL 0x0048 Output Compare Register B Low Byte
|
||
; OCR1BH 0x0049 Output Compare Register B High Byte
|
||
; OCR1AL 0x004A Output Compare Register A Low Byte
|
||
; OCR1AH 0x004B Output Compare Register A High Byte
|
||
; TCNT1L 0x004C Counter Register Low Byte
|
||
; TCNT1H 0x004D Counter Register High Byte
|
||
; TCCR1B 0x004E Timer/Counter1 Control Register B
|
||
; TCCR1B.ICNC1 7 Input Capture Noise Canceler
|
||
; TCCR1B.ICES1 6 Input Capture Edge Select
|
||
; TCCR1B.WGM13 4 Waveform Generation Mode 3
|
||
; TCCR1B.WGM12 3 Waveform Generation Mode 2
|
||
; TCCR1B.CS12 2 Clock Select 2
|
||
; TCCR1B.CS11 1 Clock Select 1
|
||
; TCCR1B.CS10 0 Clock Select 0
|
||
; TCCR1A 0x004F Timer/Counter1 Control Register A
|
||
; TCCR1A.COM1A1 7 Compare Output Mode for Channel A 1
|
||
; TCCR1A.COM1A0 6 Compare Output Mode for Channel A 0
|
||
; TCCR1A.COM1B1 5 Compare Output Mode for Channel B 1
|
||
; TCCR1A.COM1B0 4 Compare Output Mode for Channel B 0
|
||
; TCCR1A.FOC1A 3 Force Output Compare for Channel A
|
||
; TCCR1A.FOC1B 2 Force Output Compare for Channel B
|
||
; TCCR1A.WGM11 1 Waveform Generation Mode 1
|
||
; TCCR1A.WGM10 0 Waveform Generation Mode 0
|
||
; SFIOR 0x0050 Special Function I/O Register
|
||
; SFIOR.ADTS2 7 ADC Auto Trigger Source 2
|
||
; SFIOR.ADTS1 6 ADC Auto Trigger Source 1
|
||
; SFIOR.ADTS0 5 ADC Auto Trigger Source 0
|
||
; SFIOR.ADHSM 4 ADC High Speed Mode
|
||
; SFIOR.ACME 3 Analog Comparator Multiplexer Enable
|
||
; SFIOR.PUD 2 Pull-up disable
|
||
; SFIOR.PSR2 1 Prescaler Reset Timer/Counter2
|
||
; SFIOR.PSR10 0 Prescaler Reset Timer/Counter1 and Timer/Counter0
|
||
; OCDR 0x0051 On-Chip Debug Register
|
||
; ; OSCCAL 0x0051 Oscillator Calibration Register
|
||
; ; OSCCAL.CAL7 7 Oscillator Calibration Value 7
|
||
; ; OSCCAL.CAL6 6 Oscillator Calibration Value 6
|
||
; ; OSCCAL.CAL5 5 Oscillator Calibration Value 5
|
||
; ; OSCCAL.CAL4 4 Oscillator Calibration Value 4
|
||
; ; OSCCAL.CAL3 3 Oscillator Calibration Value 3
|
||
; ; OSCCAL.CAL2 2 Oscillator Calibration Value 2
|
||
; ; OSCCAL.CAL1 1 Oscillator Calibration Value 1
|
||
; ; OSCCAL.CAL0 0 Oscillator Calibration Value 0
|
||
; TCNT0 0x0052 Timer/Counter Register
|
||
; TCNT0.TCNT0_7 7
|
||
; TCNT0.TCNT0_6 6
|
||
; TCNT0.TCNT0_5 5
|
||
; TCNT0.TCNT0_4 4
|
||
; TCNT0.TCNT0_3 3
|
||
; TCNT0.TCNT0_2 2
|
||
; TCNT0.TCNT0_1 1
|
||
; TCNT0.TCNT0_0 0
|
||
; TCCR0 0x0053 Timer/Counter Control Register
|
||
; TCCR0.FOC0 7 Force Output Compare
|
||
; TCCR0.WGM00 6 Waveform Generation Mode 0
|
||
; TCCR0.COM01 5 Compare Match Output Mode 1
|
||
; TCCR0.COM00 4 Compare Match Output Mode 0
|
||
; TCCR0.WGM01 3 Waveform Generation Mode 1
|
||
; TCCR0.CS02 2 Clock Select 2
|
||
; TCCR0.CS01 1 Clock Select 1
|
||
; TCCR0.CS00 0 Clock Select 0
|
||
; MCUCSR 0x0054 MCU Control and Status Register
|
||
; MCUCSR.JTD 7 JTAG Interface Disable
|
||
; MCUCSR.ISC2 6 Interrupt Sense Control 2
|
||
; MCUCSR.JTRF 4 JTAG Reset Flag
|
||
; MCUCSR.WDRF 3 Watchdog Reset Flag
|
||
; MCUCSR.BORF 2 Brown-out Reset Flag
|
||
; MCUCSR.EXTRF 1 External Reset Flag
|
||
; MCUCSR.PORF 0 Power-on Reset Flag
|
||
; MCUCR 0x0055 MCU Control Register
|
||
; MCUCR.SE 7 Sleep Enable
|
||
; MCUCR.SM2 6 Sleep Mode Select Bit 2
|
||
; MCUCR.SM1 5 Sleep Mode Select Bit 1
|
||
; MCUCR.SM0 4 Sleep Mode Select Bit 0
|
||
; MCUCR.ISC11 3 Interrupt Sense Control 1 Bit 1
|
||
; MCUCR.ISC10 2 Interrupt Sense Control 1 Bit 0
|
||
; MCUCR.ISC01 1 Interrupt Sense Control 0 Bit 1
|
||
; MCUCR.ISC00 0 CInterrupt Sense Control 0 Bit 0
|
||
; TWCR 0x0056 TWI Control Register
|
||
; TWCR.TWINT 7 TWI Interrupt Flag
|
||
; TWCR.TWEA 6 TWI Enable Acknowledge Bit
|
||
; TWCR.TWSTA 5 TWI START Condition Bit
|
||
; TWCR.TWSTO 4 TWI STOP Condition Bit
|
||
; TWCR.TWWC 3 TWI Write Collision Flag
|
||
; TWCR.TWEN 2 TWI Enable Bit
|
||
; TWCR.TWIE 0 TWI Interrupt Enable
|
||
; SPMCR 0x0057 Store Program Memory Control Register
|
||
; SPMCR.SPMIE 7 SPM Interrupt Enable
|
||
; SPMCR.RWWSB 6 Read-While-Write Section Busy
|
||
; SPMCR.RWWSRE 4 Read-While-Write Section Read Enable
|
||
; SPMCR.BLBSET 3 Boot Lock Bit Set
|
||
; SPMCR.PGWRT 2 Page Write
|
||
; SPMCR.PGERS 1 Page Erase
|
||
; SPMCR.SPMEN 0 Store Program Memory Enable
|
||
; TIFR 0x0058 Timer/Counter Interrupt Flag Register
|
||
; TIFR.OCF2 7 Output Compare Flag 2
|
||
; TIFR.TOV2 6 Timer/Counter2 Overflow Flag
|
||
; TIFR.ICF1 5 Timer/Counter1, Input Capture Flag
|
||
; TIFR.OCF1A 4 Timer/Counter1, Output Compare A Match Flag
|
||
; TIFR.OCF1B 3 Timer/Counter1, Output Compare B Match Flag
|
||
; TIFR.TOV1 2 Timer/Counter1, Overflow Flag
|
||
; TIFR.OCF0 1 Output Compare Flag 0
|
||
; TIFR.TOV0 0 Timer/Counter0 Overflow Flag
|
||
; TIMSK 0x0059 Timer/Counter Interrupt Mask Register
|
||
; TIMSK.OCIE2 7 Timer/Counter2 Output Compare Match Interrupt Enable
|
||
; TIMSK.TOIE2 6 Timer/Counter2 Overflow Interrupt Enable
|
||
; TIMSK.TICIE1 5 Timer/Counter1, Input Capture Interrupt Enable
|
||
; TIMSK.OCIE1A 4 Timer/Counter1, Output Compare A Match Interrupt Enable
|
||
; TIMSK.OCIE1B 3 Timer/Counter1, Output Compare B Match Interrupt Enable
|
||
; TIMSK.TOIE1 2 Timer/Counter1, Overflow Interrupt Enable
|
||
; TIMSK.OCIE0 1 Timer/Counter0 Output Compare Match Interrupt Enable
|
||
; TIMSK.TOIE0 0 Timer/Counter0 Overflow Interrupt Enable
|
||
; GIFR 0x005A General Interrupt Flag Register
|
||
; GIFR.INTF1 7 External Interrupt Flag 1
|
||
; GIFR.INTF0 6 External Interrupt Flag 0
|
||
; GIFR.INTF2 5 External Interrupt Flag 2
|
||
; GICR 0x005B General Interrupt Control
|
||
; GICR.INT1 7 External Interrupt Request 1 Enable
|
||
; GICR.INT0 6 External Interrupt Request 0 Enable
|
||
; GICR.INT2 5 External Interrupt Request 2 Enable
|
||
; GICR.IVSEL 1 Interrupt Vector Select
|
||
; GICR.IVCE 0 Interrupt Vector Change Enable
|
||
; OCR0 0x005C Timer/Counter0 Output Compare Register
|
||
; SPL 0x005D Stack Pointer Low
|
||
; SPL.SP7 7
|
||
; SPL.SP6 6
|
||
; SPL.SP5 5
|
||
; SPL.SP4 4
|
||
; SPL.SP3 3
|
||
; SPL.SP2 2
|
||
; SPL.SP1 1
|
||
; SPL.SP0 0
|
||
; SPH 0x005E Stack Pointer High
|
||
; SPH.SP15 15
|
||
; SPH.SP14 14
|
||
; SPH.SP13 13
|
||
; SPH.SP12 12
|
||
; SPH.SP11 11
|
||
; SPH.SP10 10
|
||
; SPH.SP9 9
|
||
; SPH.SP8 8
|
||
; SREG 0x005F Status Register
|
||
; SREG.I 7 Global Interrupt Enable
|
||
; SREG.T 6 Bit Copy Storage
|
||
; SREG.H 5 Half Carry Flag
|
||
; SREG.S 4 Sign Bit
|
||
; SREG.V 3 Two's Complement Overflow Flag
|
||
; SREG.N 2 Negative Flag
|
||
; SREG.Z 1 Zero Flag
|
||
; SREG.C 0 Carry Flag
|
||
|
||
|
||
.ATmega64_L
|
||
SUBARCH=5
|
||
; doc2490.pdf
|
||
;
|
||
RAM=4096
|
||
ROM=65536
|
||
EEPROM=2048
|
||
|
||
; MEMORY MAP
|
||
; Memory configuration A
|
||
area DATA FSR1 0x0000:0x0060
|
||
area DATA FSR2 0x0060:0x009E Ext I/O Reg.
|
||
area BSS RESERVED 0x009E:0x0100
|
||
area DATA I_SRAM 0x0100:0x1100 Internal SRAM
|
||
area DATA E_SRAM 0x1100:0x10000 External SRAM
|
||
; Memory configuration B
|
||
; area DATA FSR 0x0000:0x0060
|
||
; area DATA I_SRAM 0x0060:0x1000 Internal SRAM
|
||
; area DATA E_SRAM 0x1000:0x10000 External SRAM
|
||
|
||
|
||
; Interrupt and reset vector assignments
|
||
entry __RESET 0x0000 External Pin, Power-on Reset, Brown-out Reset, Watchdog Reset, and JTAG AVR Reset
|
||
entry INT0_ 0x0002 External Interrupt Request 0
|
||
entry INT1_ 0x0004 External Interrupt Request 1
|
||
entry INT2_ 0x0006 External Interrupt Request 2
|
||
entry INT3_ 0x0008 External Interrupt Request 3
|
||
entry INT4_ 0x000A External Interrupt Request 4
|
||
entry INT5_ 0x000C External Interrupt Request 5
|
||
entry INT6_ 0x000E External Interrupt Request 6
|
||
entry INT7_ 0x0010 External Interrupt Request 7
|
||
entry TIMER2_COMP 0x0012 Timer/Counter2 Compare Match
|
||
entry TIMER2_OVF 0x0014 Timer/Counter2 Overflow
|
||
entry TIMER1_CAPT 0x0016 Timer/Counter1 Capture Event
|
||
entry TIMER1_COMPA 0x0018 Timer/Counter1 Compare Match A
|
||
entry TIMER1_COMPB 0x001A Timer/Counter1 Compare Match B
|
||
entry TIMER1_OVF 0x001C Timer/Counter1 Overflow
|
||
entry TIMER0_COMP 0x001E Timer/Counter0 Compare Match
|
||
entry TIMER0_OVF 0x0020 Timer/Counter0 Overflow
|
||
entry SPI_STC 0x0022 SPI Serial Transfer Complete
|
||
entry USART0_RX 0x0024 USART0, Rx Complete
|
||
entry USART0_UDRE 0x0026 USART0 Data Register Empty
|
||
entry USART0_TX 0x0028 USART0, Tx Complete
|
||
entry ADC_ 0x002A ADC Conversion Complete
|
||
entry EE_READY 0x002C EEPROM Ready
|
||
entry ANALOG_COMP 0x002E Analog Comparator
|
||
entry TIMER1_COMPC 0x0030 Timer/Countre1 Compare Match C
|
||
entry TIMER3_CAPT 0x0032 Timer/Counter3 Capture Event
|
||
entry TIMER3_COMPA 0x0034 Timer/Counter3 Compare Match A
|
||
entry TIMER3_COMPB 0x0036 Timer/Counter3 Compare Match B
|
||
entry TIMER3_COMPC 0x0038 Timer/Counter3 Compare Match C
|
||
entry TIMER3_OVF 0x003A Timer/Counter3 Overflow
|
||
entry USART1_RX 0x003C USART1, Rx Complete
|
||
entry USART1_UDRE 0x003E USART1 Data Register Empty
|
||
entry USART1_TX 0x0040 USART1, Tx Complete
|
||
entry TWI_ 0x0042 2-wire Serial Interface
|
||
entry SPM_READY 0x0044 Store Program Memory Ready
|
||
|
||
|
||
; INPUT/OUTPUT PORTS
|
||
PINF 0x0000 Port F Input Pins Address
|
||
PINF.PINF7 7
|
||
PINF.PINF6 6
|
||
PINF.PINF5 5
|
||
PINF.PINF4 4
|
||
PINF.PINF3 3
|
||
PINF.PINF2 2
|
||
PINF.PINF1 1
|
||
PINF.PINF0 0
|
||
PINE 0x0001 Port E Input Pins Address
|
||
PINE.PINE7 7
|
||
PINE.PINE6 6
|
||
PINE.PINE5 5
|
||
PINE.PINE4 4
|
||
PINE.PINE3 3
|
||
PINE.PINE2 2
|
||
PINE.PINE1 1
|
||
PINE.PINE0 0
|
||
DDRE 0x0002 Port E Data Direction Register
|
||
DDRE.DDE7 7 Port E Data Direction Register bit 7
|
||
DDRE.DDE6 6 Port E Data Direction Register bit 6
|
||
DDRE.DDE5 5 Port E Data Direction Register bit 5
|
||
DDRE.DDE4 4 Port E Data Direction Register bit 4
|
||
DDRE.DDE3 3 Port E Data Direction Register bit 3
|
||
DDRE.DDE2 2 Port E Data Direction Register bit 2
|
||
DDRE.DDE1 1 Port E Data Direction Register bit 1
|
||
DDRE.DDE0 0 Port E Data Direction Register bit 0
|
||
PORTE 0x0003 Port E Data Register
|
||
PORTE.PORTE7 7 Port E Data Register bit 7
|
||
PORTE.PORTE6 6 Port E Data Register bit 6
|
||
PORTE.PORTE5 5 Port E Data Register bit 5
|
||
PORTE.PORTE4 4 Port E Data Register bit 4
|
||
PORTE.PORTE3 3 Port E Data Register bit 3
|
||
PORTE.PORTE2 2 Port E Data Register bit 2
|
||
PORTE.PORTE1 1 Port E Data Register bit 1
|
||
PORTE.PORTE0 0 Port E Data Register bit 0
|
||
ADCL 0x0004 ADC Data Register Low (ADLAR = 0)
|
||
ADCL.ADC7 7 ADC Conversion Result 7
|
||
ADCL.ADC6 6 ADC Conversion Result 6
|
||
ADCL.ADC5 5 ADC Conversion Result 5
|
||
ADCL.ADC4 4 ADC Conversion Result 4
|
||
ADCL.ADC3 3 ADC Conversion Result 3
|
||
ADCL.ADC2 2 ADC Conversion Result 2
|
||
ADCL.ADC1 1 ADC Conversion Result 1
|
||
ADCL.ADC0 0 ADC Conversion Result 0
|
||
ADCH 0x0005 ADC Data Register High (ADLAR = 0)
|
||
ADCH.ADC9 9 ADC Conversion Result 9
|
||
ADCH.ADC8 8 ADC Conversion Result 8
|
||
; ADCL 0x0004 ADC Data Register Low (ADLAR = 1)
|
||
; ADCL.ADC1 7 ADC Conversion Result 1
|
||
; ADCL.ADC0 6 ADC Conversion Result 0
|
||
; ADCH 0x0005 ADC Data Register High (ADLAR = 1)
|
||
; ADCH.ADC9 15 ADC Conversion Result 9
|
||
; ADCH.ADC8 14 ADC Conversion Result 8
|
||
; ADCH.ADC7 13 ADC Conversion Result 7
|
||
; ADCH.ADC6 12 ADC Conversion Result 6
|
||
; ADCH.ADC5 11 ADC Conversion Result 5
|
||
; ADCH.ADC4 10 ADC Conversion Result 4
|
||
; ADCH.ADC3 9 ADC Conversion Result 3
|
||
; ADCH.ADC2 8 ADC Conversion Result 2
|
||
ADCSRA 0x0006 ADC Control and Status Register A
|
||
ADCSRA.ADEN 7 ADC Enable
|
||
ADCSRA.ADSC 6 ADC Start Conversion
|
||
ADCSRA.ADATE 5 ADC Auto Trigger Enable
|
||
ADCSRA.ADIF 4 ADC Interrupt Flag
|
||
ADCSRA.ADIE 3 ADC Interrupt Enable
|
||
ADCSRA.ADPS2 2 ADC Prescaler Select Bit 2
|
||
ADCSRA.ADPS1 1 ADC Prescaler Select Bit 1
|
||
ADCSRA.ADPS0 0 ADC Prescaler Select Bit 0
|
||
ADMUX 0x0007 ADC Multiplexer Selection Register
|
||
ADMUX.REFS1 7 Reference Selection Bit 1
|
||
ADMUX.REFS0 6 Reference Selection Bit 0
|
||
ADMUX.ADLAR 5 ADC Left Adjust Result
|
||
ADMUX.MUX4 4 Analog Channel and Gain Selection Bit 4
|
||
ADMUX.MUX3 3 Analog Channel and Gain Selection Bit 3
|
||
ADMUX.MUX2 2 Analog Channel and Gain Selection Bit 2
|
||
ADMUX.MUX1 1 Analog Channel and Gain Selection Bit 1
|
||
ADMUX.MUX0 0 Analog Channel and Gain Selection Bit 0
|
||
ACSR 0x0008 Analog Comparator Control and Status Register
|
||
ACSR.ACD 7 Analog Comparator Disable
|
||
ACSR.ACBG 6 Analog Comparator Bandgap Select
|
||
ACSR.ACO 5 Analog Comparator Output
|
||
ACSR.ACI 4 Analog Comparator Interrupt Flag
|
||
ACSR.ACIE 3 Analog Comparator Interrupt Enable
|
||
ACSR.ACIC 2 Analog Comparator Input Capture Enable
|
||
ACSR.ACIS1 1 Analog Comparator Interrupt Mode Select 1
|
||
ACSR.ACIS0 0 Analog Comparator Interrupt Mode Select 0
|
||
UBRR0L 0x0009 USART Baud Rate Register
|
||
UBRR0L.UBRR7 7 USART Baud Rate Register bit 7
|
||
UBRR0L.UBRR6 6 USART Baud Rate Register bit 6
|
||
UBRR0L.UBRR5 5 USART Baud Rate Register bit 5
|
||
UBRR0L.UBRR4 4 USART Baud Rate Register bit 4
|
||
UBRR0L.UBRR3 3 USART Baud Rate Register bit 3
|
||
UBRR0L.UBRR2 2 USART Baud Rate Register bit 2
|
||
UBRR0L.UBRR1 1 USART Baud Rate Register bit 1
|
||
UBRR0L.UBRR0 0 USART Baud Rate Register bit 0
|
||
UCSR0B 0x000A USART Control and Status Register B
|
||
UCSR0B.RXCIE 7 RX Complete Interrupt Enable
|
||
UCSR0B.TXCIE 6 TX Complete Interrupt Enable
|
||
UCSR0B.UDRIE 5 USART Data Register Empty Interrupt Enable
|
||
UCSR0B.RXEN 4 Receiver Enable
|
||
UCSR0B.TXEN 3 Transmitter Enable
|
||
UCSR0B.UCSZ2 2 Character Size
|
||
UCSR0B.RXB8 1 Receive Data Bit 8
|
||
UCSR0B.TXB8 0 Transmit Data Bit 8
|
||
UCSR0A 0x000B USART Control and Status Register A
|
||
UCSR0A.RXC 7 USART Receive Complete
|
||
UCSR0A.TXC 6 USART Transmit Complete
|
||
UCSR0A.UDRE 5 USART Data Register Empty
|
||
UCSR0A.FE 4 Frame Error
|
||
UCSR0A.DOR 3 Data OverRun
|
||
UCSR0A.UPE 2 USART Parity Error
|
||
UCSR0A.U2X 1 Double the USART Transmission Speed
|
||
UCSR0A.MPCM 0 Multi-processor Communication Mode
|
||
UDR0 0x000C USART0 I/O Data Register
|
||
SPCR 0x000D SPI Control Register
|
||
SPCR.SPIE 7 SPI Interrupt Enable
|
||
SPCR.SPE 6 SPI Enable
|
||
SPCR.DORD 5 Data Order
|
||
SPCR.MSTR 4 Master/Slave Select
|
||
SPCR.CPOL 3 Clock Polarity
|
||
SPCR.CPHA 2 Clock Phase
|
||
SPCR.SPR1 1 SPI Clock Rate Select 1
|
||
SPCR.SPR0 0 SPI Clock Rate Select 0
|
||
SPSR 0x000E SPI Status Register
|
||
SPSR.SPIF 7 SPI Interrupt Flag
|
||
SPSR.WCOL 6 Write COLlision Flag
|
||
SPSR.SPI2X 0 Double SPI Speed Bit
|
||
SPDR 0x000F SPI Data Register
|
||
PIND 0x0010 Port D Input Pins Address
|
||
PIND.PIND7 7
|
||
PIND.PIND6 6
|
||
PIND.PIND5 5
|
||
PIND.PIND4 4
|
||
PIND.PIND3 3
|
||
PIND.PIND2 2
|
||
PIND.PIND1 1
|
||
PIND.PIND0 0
|
||
DDRD 0x0011 Port D Data Direction Register
|
||
DDRD.DDD7 7 Port D Data Direction Register bit 7
|
||
DDRD.DDD6 6 Port D Data Direction Register bit 6
|
||
DDRD.DDD5 5 Port D Data Direction Register bit 5
|
||
DDRD.DDD4 4 Port D Data Direction Register bit 4
|
||
DDRD.DDD3 3 Port D Data Direction Register bit 3
|
||
DDRD.DDD2 2 Port D Data Direction Register bit 2
|
||
DDRD.DDD1 1 Port D Data Direction Register bit 1
|
||
DDRD.DDD0 0 Port D Data Direction Register bit 0
|
||
PORTD 0x0012 Port D Data Register
|
||
PORTD.PORTD7 7 Port D Data Register bit 7
|
||
PORTD.PORTD6 6 Port D Data Register bit 6
|
||
PORTD.PORTD5 5 Port D Data Register bit 5
|
||
PORTD.PORTD4 4 Port D Data Register bit 4
|
||
PORTD.PORTD3 3 Port D Data Register bit 3
|
||
PORTD.PORTD2 2 Port D Data Register bit 2
|
||
PORTD.PORTD1 1 Port D Data Register bit 1
|
||
PORTD.PORTD0 0 Port D Data Register bit 0
|
||
PINC 0x0013 Port C Input Pins Address
|
||
PINC.PINC7 7
|
||
PINC.PINC6 6
|
||
PINC.PINC5 5
|
||
PINC.PINC4 4
|
||
PINC.PINC3 3
|
||
PINC.PINC2 2
|
||
PINC.PINC1 1
|
||
PINC.PINC0 0
|
||
DDRC 0x0014 Port C Data Direction Register
|
||
DDRC.DDC7 7 Port C Data Direction Register bit 7
|
||
DDRC.DDC6 6 Port C Data Direction Register bit 6
|
||
DDRC.DDC5 5 Port C Data Direction Register bit 5
|
||
DDRC.DDC4 4 Port C Data Direction Register bit 4
|
||
DDRC.DDC3 3 Port C Data Direction Register bit 3
|
||
DDRC.DDC2 2 Port C Data Direction Register bit 2
|
||
DDRC.DDC1 1 Port C Data Direction Register bit 1
|
||
DDRC.DDC0 0 Port C Data Direction Register bit 0
|
||
PORTC 0x0015 Port C Data Register
|
||
PORTC.PORTC7 7 Port C Data Register bit 7
|
||
PORTC.PORTC6 6 Port C Data Register bit 6
|
||
PORTC.PORTC5 5 Port C Data Register bit 5
|
||
PORTC.PORTC4 4 Port C Data Register bit 4
|
||
PORTC.PORTC3 3 Port C Data Register bit 3
|
||
PORTC.PORTC2 2 Port C Data Register bit 2
|
||
PORTC.PORTC1 1 Port C Data Register bit 1
|
||
PORTC.PORTC0 0 Port C Data Register bit 0
|
||
PINB 0x0016 Port B Input Pins Address
|
||
PINB.PINB7 7
|
||
PINB.PINB6 6
|
||
PINB.PINB5 5
|
||
PINB.PINB4 4
|
||
PINB.PINB3 3
|
||
PINB.PINB2 2
|
||
PINB.PINB1 1
|
||
PINB.PINB0 0
|
||
DDRB 0x0017 Port B Data Direction Register
|
||
DDRB.DDB7 7 Port B Data Direction Register bit 7
|
||
DDRB.DDB6 6 Port B Data Direction Register bit 6
|
||
DDRB.DDB5 5 Port B Data Direction Register bit 5
|
||
DDRB.DDB4 4 Port B Data Direction Register bit 4
|
||
DDRB.DDB3 3 Port B Data Direction Register bit 3
|
||
DDRB.DDB2 2 Port B Data Direction Register bit 2
|
||
DDRB.DDB1 1 Port B Data Direction Register bit 1
|
||
DDRB.DDB0 0 Port B Data Direction Register bit 0
|
||
PORTB 0x0018 Port B Data Register
|
||
PORTB.PORTB7 7 Port B Data Register bit 7
|
||
PORTB.PORTB6 6 Port B Data Register bit 6
|
||
PORTB.PORTB5 5 Port B Data Register bit 5
|
||
PORTB.PORTB4 4 Port B Data Register bit 4
|
||
PORTB.PORTB3 3 Port B Data Register bit 3
|
||
PORTB.PORTB2 2 Port B Data Register bit 2
|
||
PORTB.PORTB1 1 Port B Data Register bit 1
|
||
PORTB.PORTB0 0 Port B Data Register bit 0
|
||
PINA 0x0019 Port A Input Pins Address
|
||
PINA.PINA7 7
|
||
PINA.PINA6 6
|
||
PINA.PINA5 5
|
||
PINA.PINA4 4
|
||
PINA.PINA3 3
|
||
PINA.PINA2 2
|
||
PINA.PINA1 1
|
||
PINA.PINA0 0
|
||
DDRA 0x001A Port A Data Direction Register
|
||
DDRA.DDA7 7 Port A Data Direction Register bit 7
|
||
DDRA.DDA6 6 Port A Data Direction Register bit 6
|
||
DDRA.DDA5 5 Port A Data Direction Register bit 5
|
||
DDRA.DDA4 4 Port A Data Direction Register bit 4
|
||
DDRA.DDA3 3 Port A Data Direction Register bit 3
|
||
DDRA.DDA2 2 Port A Data Direction Register bit 2
|
||
DDRA.DDA1 1 Port A Data Direction Register bit 1
|
||
DDRA.DDA0 0 Port A Data Direction Register bit 0
|
||
PORTA 0x001B Port A Data Register
|
||
PORTA.PORTA7 7 Port A Data Register bit 7
|
||
PORTA.PORTA6 6 Port A Data Register bit 6
|
||
PORTA.PORTA5 5 Port A Data Register bit 5
|
||
PORTA.PORTA4 4 Port A Data Register bit 4
|
||
PORTA.PORTA3 3 Port A Data Register bit 3
|
||
PORTA.PORTA2 2 Port A Data Register bit 2
|
||
PORTA.PORTA1 1 Port A Data Register bit 1
|
||
PORTA.PORTA0 0 Port A Data Register bit 0
|
||
EECR 0x001C EEPROM Control Register
|
||
EECR.EERIE 3 EEPROM Ready Interrupt Enable
|
||
EECR.EEMWE 2 EEPROM Master Write Enable
|
||
EECR.EEWE 1 EEPROM Write Enable
|
||
EECR.EERE 0 EEPROM Read Enable
|
||
EEDR 0x001D EEPROM Data Register
|
||
EEDR.EEDR7 7 EEPROM Data 7
|
||
EEDR.EEDR6 6 EEPROM Data 6
|
||
EEDR.EEDR5 5 EEPROM Data 5
|
||
EEDR.EEDR4 4 EEPROM Data 4
|
||
EEDR.EEDR3 3 EEPROM Data 3
|
||
EEDR.EEDR2 2 EEPROM Data 2
|
||
EEDR.EEDR1 1 EEPROM Data 1
|
||
EEDR.EEDR0 0 EEPROM Data 0
|
||
EEARL 0x001E EEPROM Address Register Low
|
||
EEARL.EEAR7 7 EEPROM Addres 7
|
||
EEARL.EEAR6 6 EEPROM Addres 6
|
||
EEARL.EEAR5 5 EEPROM Addres 5
|
||
EEARL.EEAR4 4 EEPROM Addres 4
|
||
EEARL.EEAR3 3 EEPROM Addres 3
|
||
EEARL.EEAR2 2 EEPROM Addres 2
|
||
EEARL.EEAR1 1 EEPROM Addres 1
|
||
EEARL.EEAR0 0 EEPROM Addres 0
|
||
EEARH 0x001F EEPROM Address Register High
|
||
EEARH.EEAR10 10 EEPROM Addres 10
|
||
EEARH.EEAR9 9 EEPROM Addres 9
|
||
EEARH.EEAR8 8 EEPROM Addres 8
|
||
SFIOR 0x0020 Special Function IO Register
|
||
SFIOR.TSM 7 Timer/Counter Synchronization Mode
|
||
SFIOR.ADHSM 4 ADC High Speed Mode
|
||
SFIOR.ACME 3 Analog Comparator Multiplexer Enable
|
||
SFIOR.PUD 2 Pull-up disable
|
||
SFIOR.PSR0 1 Prescaler Reset Timer/Counter0
|
||
SFIOR.PSR321 0 Prescaler Reset Timer/Counter3, Timer/Counter2, and Timer/Counter1
|
||
WDTCR 0x0021 Watchdog Timer Control Register
|
||
WDTCR.WDCE 4 Watchdog Change Enable
|
||
WDTCR.WDE 3 Watchdog Enable
|
||
WDTCR.WDP2 2 Watchdog Timer Prescaler 2
|
||
WDTCR.WDP1 1 Watchdog Timer Prescaler 1
|
||
WDTCR.WDP0 0 Watchdog Timer Prescaler 0
|
||
OCDR 0x0022 On-chip Debug Register
|
||
OCDR.IDRD_OCDR7 7
|
||
OCDR.OCDR6 6
|
||
OCDR.OCDR5 5
|
||
OCDR.OCDR4 4
|
||
OCDR.OCDR3 3
|
||
OCDR.OCDR2 2
|
||
OCDR.OCDR1 1
|
||
OCDR.OCDR0 0
|
||
OCR2 0x0023 Output Compare Register
|
||
OCR2.OCR2_7 7
|
||
OCR2.OCR2_6 6
|
||
OCR2.OCR2_5 5
|
||
OCR2.OCR2_4 4
|
||
OCR2.OCR2_3 3
|
||
OCR2.OCR2_2 2
|
||
OCR2.OCR2_1 1
|
||
OCR2.OCR2_0 0
|
||
TCNT2 0x0024 Timer/Counter Register
|
||
TCNT2.TCNT2_7 7
|
||
TCNT2.TCNT2_6 6
|
||
TCNT2.TCNT2_5 5
|
||
TCNT2.TCNT2_4 4
|
||
TCNT2.TCNT2_3 3
|
||
TCNT2.TCNT2_2 2
|
||
TCNT2.TCNT2_1 1
|
||
TCNT2.TCNT2_0 0
|
||
TCCR2 0x0025 Timer/Counter Control Register
|
||
TCCR2.FOC2 7 Force Output Compare
|
||
TCCR2.WGM20 6 Waveform Generation Mode 0
|
||
TCCR2.COM21 5 Compare Match Output Mode 1
|
||
TCCR2.COM20 4 Compare Match Output Mode 0
|
||
TCCR2.WGM21 3 Waveform Generation Mode 1
|
||
TCCR2.CS22 2 Clock Select 2
|
||
TCCR2.CS21 1 Clock Select 1
|
||
TCCR2.CS20 0 Clock Select 0
|
||
ICR1L 0x0026 Input Capture Register 1 Low
|
||
ICR1L.ICR1_7 7
|
||
ICR1L.ICR1_6 6
|
||
ICR1L.ICR1_5 5
|
||
ICR1L.ICR1_4 4
|
||
ICR1L.ICR1_3 3
|
||
ICR1L.ICR1_2 2
|
||
ICR1L.ICR1_1 1
|
||
ICR1L.ICR1_0 0
|
||
ICR1H 0x0027 Input Capture Register 1 High
|
||
ICR1H.ICR1_15 15
|
||
ICR1H.ICR1_14 14
|
||
ICR1H.ICR1_13 13
|
||
ICR1H.ICR1_12 12
|
||
ICR1H.ICR1_11 11
|
||
ICR1H.ICR1_10 10
|
||
ICR1H.ICR1_9 9
|
||
ICR1H.ICR1_8 8
|
||
OCR1BL 0x0028 Output Compare Register 1 B Low
|
||
OCR1BL.OCR1B_7 7
|
||
OCR1BL.OCR1B_6 6
|
||
OCR1BL.OCR1B_5 5
|
||
OCR1BL.OCR1B_4 4
|
||
OCR1BL.OCR1B_3 3
|
||
OCR1BL.OCR1B_2 2
|
||
OCR1BL.OCR1B_1 1
|
||
OCR1BL.OCR1B_0 0
|
||
OCR1BH 0x0029 Output Compare Register 1 B High
|
||
OCR1BH.OCR1B_15 15
|
||
OCR1BH.OCR1B_14 14
|
||
OCR1BH.OCR1B_13 13
|
||
OCR1BH.OCR1B_12 12
|
||
OCR1BH.OCR1B_11 11
|
||
OCR1BH.OCR1B_10 10
|
||
OCR1BH.OCR1B_9 9
|
||
OCR1BH.OCR1B_8 8
|
||
OCR1AL 0x002A Output Compare Register 1 A Low
|
||
OCR1AL.OCR1A_7 7
|
||
OCR1AL.OCR1A_6 6
|
||
OCR1AL.OCR1A_5 5
|
||
OCR1AL.OCR1A_4 4
|
||
OCR1AL.OCR1A_3 3
|
||
OCR1AL.OCR1A_2 2
|
||
OCR1AL.OCR1A_1 1
|
||
OCR1AL.OCR1A_0 0
|
||
OCR1AH 0x002B Output Compare Register 1 A High
|
||
OCR1AH.OCR1A_15 15
|
||
OCR1AH.OCR1A_14 14
|
||
OCR1AH.OCR1A_13 13
|
||
OCR1AH.OCR1A_12 12
|
||
OCR1AH.OCR1A_11 11
|
||
OCR1AH.OCR1A_10 10
|
||
OCR1AH.OCR1A_9 9
|
||
OCR1AH.OCR1A_8 8
|
||
TCNT1L 0x002C Timer/Counter 1 Low
|
||
TCNT1L.TCNT1_7 7
|
||
TCNT1L.TCNT1_6 6
|
||
TCNT1L.TCNT1_5 5
|
||
TCNT1L.TCNT1_4 4
|
||
TCNT1L.TCNT1_3 3
|
||
TCNT1L.TCNT1_2 2
|
||
TCNT1L.TCNT1_1 1
|
||
TCNT1L.TCNT1_0 0
|
||
TCNT1H 0x002D Timer/Counter 1 High
|
||
TCNT1H.TCNT1_15 15
|
||
TCNT1H.TCNT1_14 14
|
||
TCNT1H.TCNT1_13 13
|
||
TCNT1H.TCNT1_12 12
|
||
TCNT1H.TCNT1_11 11
|
||
TCNT1H.TCNT1_10 10
|
||
TCNT1H.TCNT1_9 9
|
||
TCNT1H.TCNT1_8 8
|
||
TCCR1B 0x002E Timer/Counter 1 Control Register B
|
||
TCCR1B.ICNC1 7 Input Capture Noise Canceler
|
||
TCCR1B.ICES1 6 Input Capture Edge Select
|
||
TCCR1B.WGM13 4 Waveform Generation Mode 3
|
||
TCCR1B.WGM12 3 Waveform Generation Mode 2
|
||
TCCR1B.CS12 2 Clock Select 2
|
||
TCCR1B.CS11 1 Clock Select 1
|
||
TCCR1B.CS10 0 Clock Select 0
|
||
TCCR1A 0x002F Timer/Counter 1 Control Register A
|
||
TCCR1A.COM1A1 7 Compare Output Mode for Channel A 1
|
||
TCCR1A.COM1A0 6 Compare Output Mode for Channel A 0
|
||
TCCR1A.COM1B1 5 Compare Output Mode for Channel B 1
|
||
TCCR1A.COM1B0 4 Compare Output Mode for Channel B 0
|
||
TCCR1A.COM1C1 3 Compare Output Mode for Channel C 1
|
||
TCCR1A.COM1C0 2 Compare Output Mode for Channel C 0
|
||
TCCR1A.WGM11 1 Waveform Generation Mode 1
|
||
TCCR1A.WGM10 0 Waveform Generation Mode 0
|
||
ASSR 0x0030 Asynchronous Status Register
|
||
ASSR.AS0 3 Asynchronous Timer/Counter0
|
||
ASSR.TCN0UB 2 Timer/Counter0 Update Busy
|
||
ASSR.OCR0UB 1 Output Compare Register0 Update Busy
|
||
ASSR.TCR0UB 0 Timer/Counter Control Register0 Update Busy
|
||
OCR0 0x0031 Output Compare Register
|
||
OCR0.OCR0_7 7
|
||
OCR0.OCR0_6 6
|
||
OCR0.OCR0_5 5
|
||
OCR0.OCR0_4 4
|
||
OCR0.OCR0_3 3
|
||
OCR0.OCR0_2 2
|
||
OCR0.OCR0_1 1
|
||
OCR0.OCR0_0 0
|
||
TCNT0 0x0032 Timer/Counter Register
|
||
TCNT0.TCNT0_7 7
|
||
TCNT0.TCNT0_6 6
|
||
TCNT0.TCNT0_5 5
|
||
TCNT0.TCNT0_4 4
|
||
TCNT0.TCNT0_3 3
|
||
TCNT0.TCNT0_2 2
|
||
TCNT0.TCNT0_1 1
|
||
TCNT0.TCNT0_0 0
|
||
TCCR0 0x0033 Timer/Counter Control Register
|
||
TCCR0.FOC0 7 Force Output Compare
|
||
TCCR0.WGM00 6 Waveform Generation Mode 0
|
||
TCCR0.COM01 5 Compare Match Output Mode 1
|
||
TCCR0.COM00 4 Compare Match Output Mode 0
|
||
TCCR0.WGM01 3 Waveform Generation Mode 1
|
||
TCCR0.CS02 2 Clock Select 2
|
||
TCCR0.CS01 1 Clock Select 1
|
||
TCCR0.CS00 0 Clock Select 0
|
||
MCUCSR 0x0034 MCU Control and Status Register
|
||
MCUCSR.JTD 7 JTAG interface disable
|
||
MCUCSR.JTRF 4 JTAG Reset Flag
|
||
MCUCSR.WDRF 3 Watchdog Reset Flag
|
||
MCUCSR.BORF 2 Brown-out Reset Flag
|
||
MCUCSR.EXTRF 1 External Reset Flag
|
||
MCUCSR.PORF 0 Power-on Reset Flag
|
||
MCUCR 0x0035 MCU Control Register
|
||
MCUCR.SRE 7 External SRAM/XMEM Enable
|
||
MCUCR.SRW10 6 Wait State Select Bit
|
||
MCUCR.SE 5 Sleep Enable
|
||
MCUCR.SM1 4 Sleep Mode Select Bit 1
|
||
MCUCR.SM0 3 Sleep Mode Select Bit 0
|
||
MCUCR.SM2 2 Sleep Mode Select Bit 2
|
||
MCUCR.IVSEL 1 Interrupt Vector Select
|
||
MCUCR.IVCE 0 Interrupt Vector Change Enable
|
||
TIFR 0x0036 Timer/Counter Interrupt Flag Register
|
||
TIFR.OCF2 7 Output Compare Flag 2
|
||
TIFR.TOV2 6 Timer/Counter2 Overflow Flag
|
||
TIFR.ICF1 5 Timer/Counter1, Input Capture Flag
|
||
TIFR.OCF1A 4 Timer/Counter1, Output Compare A Match Flag
|
||
TIFR.OCF1B 3 Timer/Counter1, Output Compare B Match Flag
|
||
TIFR.TOV1 2 Timer/Counter1, Overflow Flag
|
||
TIFR.OCF0 1 Output Compare Flag 0
|
||
TIFR.TOV0 0 Timer/Counter0 Overflow Flag
|
||
TIMSK 0x0037 Timer/Counter Interrupt Mask Register
|
||
TIMSK.OCIE2 7 Timer/Counter2 Output Compare Match Interrupt Enable
|
||
TIMSK.TOIE2 6 Timer/Counter2 Overflow Interrupt Enable
|
||
TIMSK.TICIE1 5 Timer/Counter1, Input Capture Interrupt Enable
|
||
TIMSK.OCIE1A 4 Timer/Counter1, Output Compare A Match Interrupt Enable
|
||
TIMSK.OCIE1B 3 Timer/Counter1, Output Compare B Match Interrupt Enable
|
||
TIMSK.TOIE1 2 Timer/Counter1, Overflow Interrupt Enable
|
||
TIMSK.OCIE0 1 Timer/Counter0 Output Compare Match Interrupt Enable
|
||
TIMSK.TOIE0 0 Timer/Counter0 Overflow Interrupt Enable
|
||
EIFR 0x0038 External Interrupt Flag Register
|
||
EIFR.INTF7 7 External Interrupt Flag 7
|
||
EIFR.INTF6 6 External Interrupt Flag 6
|
||
EIFR.INTF5 5 External Interrupt Flag 5
|
||
EIFR.INTF4 4 External Interrupt Flag 4
|
||
EIFR.INTF3 3 External Interrupt Flag 3
|
||
EIFR.INTF2 2 External Interrupt Flag 2
|
||
EIFR.INTF1 1 External Interrupt Flag 1
|
||
EIFR.INTF0 0 External Interrupt Flag 0
|
||
EIMSK 0x0039 External Interrupt Mask Register
|
||
EIMSK.INT7 7 External Interrupt Request 7 Enable
|
||
EIMSK.INT6 6 External Interrupt Request 6 Enable
|
||
EIMSK.INT5 5 External Interrupt Request 5 Enable
|
||
EIMSK.INT4 4 External Interrupt Request 4 Enable
|
||
EIMSK.INT3 3 External Interrupt Request 3 Enable
|
||
EIMSK.INT2 2 External Interrupt Request 2 Enable
|
||
EIMSK.INT1 1 External Interrupt Request 1 Enable
|
||
EIMSK.INT0 0 External Interrupt Request 0 Enable
|
||
EICRB 0x003A External Interrupt Control Register B
|
||
EICRB.ISC71 7 External Interrupt 7 Sense Control Bit 1
|
||
EICRB.ISC70 6 External Interrupt 7 Sense Control Bit 0
|
||
EICRB.ISC61 5 External Interrupt 6 Sense Control Bit 1
|
||
EICRB.ISC60 4 External Interrupt 6 Sense Control Bit 0
|
||
EICRB.ISC51 3 External Interrupt 5 Sense Control Bit 1
|
||
EICRB.ISC50 2 External Interrupt 5 Sense Control Bit 0
|
||
EICRB.ISC41 1 External Interrupt 4 Sense Control Bit 1
|
||
EICRB.ISC40 0 External Interrupt 4 Sense Control Bit 0
|
||
RESERVED003B 0x003B RESERVED
|
||
XDIV 0x003C XTAL Divide Control Register
|
||
XDIV.XDIVEN 7 XTAL Divide Enable
|
||
XDIV.XDIV6 6 XTAL Divide Select Bit 6
|
||
XDIV.XDIV5 5 XTAL Divide Select Bit 5
|
||
XDIV.XDIV4 4 XTAL Divide Select Bit 4
|
||
XDIV.XDIV3 3 XTAL Divide Select Bit 3
|
||
XDIV.XDIV2 2 XTAL Divide Select Bit 2
|
||
XDIV.XDIV1 1 XTAL Divide Select Bit 1
|
||
XDIV.XDIV0 0 XTAL Divide Select Bit 0
|
||
SPL 0x003D Stack Pointer Low
|
||
SPL.SP7 7
|
||
SPL.SP6 6
|
||
SPL.SP5 5
|
||
SPL.SP4 4
|
||
SPL.SP3 3
|
||
SPL.SP2 2
|
||
SPL.SP1 1
|
||
SPL.SP0 0
|
||
SPH 0x003E Stack Pointer High
|
||
SPH.SP15 15
|
||
SPH.SP14 14
|
||
SPH.SP13 13
|
||
SPH.SP12 12
|
||
SPH.SP11 11
|
||
SPH.SP10 10
|
||
SPH.SP9 9
|
||
SPH.SP8 8
|
||
SREG 0x003F Status Register
|
||
SREG.I 7 Global Interrupt Enable
|
||
SREG.T 6 Bit Copy Storage
|
||
SREG.H 5 Half Carry Flag
|
||
SREG.S 4 Sign Bit
|
||
SREG.V 3 Two's Complement Overflow Flag
|
||
SREG.N 2 Negative Flag
|
||
SREG.Z 1 Zero Flag
|
||
SREG.C 0 Carry Flag
|
||
|
||
; PINF 0x0020 Port F Input Pins Address
|
||
; PINF.PINF7 7
|
||
; PINF.PINF6 6
|
||
; PINF.PINF5 5
|
||
; PINF.PINF4 4
|
||
; PINF.PINF3 3
|
||
; PINF.PINF2 2
|
||
; PINF.PINF1 1
|
||
; PINF.PINF0 0
|
||
; PINE 0x0021 Port E Input Pins Address
|
||
; PINE.PINE7 7
|
||
; PINE.PINE6 6
|
||
; PINE.PINE5 5
|
||
; PINE.PINE4 4
|
||
; PINE.PINE3 3
|
||
; PINE.PINE2 2
|
||
; PINE.PINE1 1
|
||
; PINE.PINE0 0
|
||
; DDRE 0x0022 Port E Data Direction Register
|
||
; DDRE.DDE7 7 Port E Data Direction Register bit 7
|
||
; DDRE.DDE6 6 Port E Data Direction Register bit 6
|
||
; DDRE.DDE5 5 Port E Data Direction Register bit 5
|
||
; DDRE.DDE4 4 Port E Data Direction Register bit 4
|
||
; DDRE.DDE3 3 Port E Data Direction Register bit 3
|
||
; DDRE.DDE2 2 Port E Data Direction Register bit 2
|
||
; DDRE.DDE1 1 Port E Data Direction Register bit 1
|
||
; DDRE.DDE0 0 Port E Data Direction Register bit 0
|
||
; PORTE 0x0023 Port E Data Register
|
||
; PORTE.PORTE7 7 Port E Data Register bit 7
|
||
; PORTE.PORTE6 6 Port E Data Register bit 6
|
||
; PORTE.PORTE5 5 Port E Data Register bit 5
|
||
; PORTE.PORTE4 4 Port E Data Register bit 4
|
||
; PORTE.PORTE3 3 Port E Data Register bit 3
|
||
; PORTE.PORTE2 2 Port E Data Register bit 2
|
||
; PORTE.PORTE1 1 Port E Data Register bit 1
|
||
; PORTE.PORTE0 0 Port E Data Register bit 0
|
||
; ADCL 0x0024 ADC Data Register Low (ADLAR = 0)
|
||
; ADCL.ADC7 7 ADC Conversion Result 7
|
||
; ADCL.ADC6 6 ADC Conversion Result 6
|
||
; ADCL.ADC5 5 ADC Conversion Result 5
|
||
; ADCL.ADC4 4 ADC Conversion Result 4
|
||
; ADCL.ADC3 3 ADC Conversion Result 3
|
||
; ADCL.ADC2 2 ADC Conversion Result 2
|
||
; ADCL.ADC1 1 ADC Conversion Result 1
|
||
; ADCL.ADC0 0 ADC Conversion Result 0
|
||
; ADCH 0x0025 ADC Data Register High (ADLAR = 0)
|
||
; ADCH.ADC9 9 ADC Conversion Result 9
|
||
; ADCH.ADC8 8 ADC Conversion Result 8
|
||
; ; ADCL 0x0024 ADC Data Register Low (ADLAR = 1)
|
||
; ; ADCL.ADC1 7 ADC Conversion Result 1
|
||
; ; ADCL.ADC0 6 ADC Conversion Result 0
|
||
; ; ADCH 0x0025 ADC Data Register High (ADLAR = 1)
|
||
; ; ADCH.ADC9 15 ADC Conversion Result 9
|
||
; ; ADCH.ADC8 14 ADC Conversion Result 8
|
||
; ; ADCH.ADC7 13 ADC Conversion Result 7
|
||
; ; ADCH.ADC6 12 ADC Conversion Result 6
|
||
; ; ADCH.ADC5 11 ADC Conversion Result 5
|
||
; ; ADCH.ADC4 10 ADC Conversion Result 4
|
||
; ; ADCH.ADC3 9 ADC Conversion Result 3
|
||
; ; ADCH.ADC2 8 ADC Conversion Result 2
|
||
; ADCSRA 0x0026 ADC Control and Status Register A
|
||
; ADCSRA.ADEN 7 ADC Enable
|
||
; ADCSRA.ADSC 6 ADC Start Conversion
|
||
; ADCSRA.ADATE 5 ADC Auto Trigger Enable
|
||
; ADCSRA.ADIF 4 ADC Interrupt Flag
|
||
; ADCSRA.ADIE 3 ADC Interrupt Enable
|
||
; ADCSRA.ADPS2 2 ADC Prescaler Select Bit 2
|
||
; ADCSRA.ADPS1 1 ADC Prescaler Select Bit 1
|
||
; ADCSRA.ADPS0 0 ADC Prescaler Select Bit 0
|
||
; ADMUX 0x0027 ADC Multiplexer Selection Register
|
||
; ADMUX.REFS1 7 Reference Selection Bit 1
|
||
; ADMUX.REFS0 6 Reference Selection Bit 0
|
||
; ADMUX.ADLAR 5 ADC Left Adjust Result
|
||
; ADMUX.MUX4 4 Analog Channel and Gain Selection Bit 4
|
||
; ADMUX.MUX3 3 Analog Channel and Gain Selection Bit 3
|
||
; ADMUX.MUX2 2 Analog Channel and Gain Selection Bit 2
|
||
; ADMUX.MUX1 1 Analog Channel and Gain Selection Bit 1
|
||
; ADMUX.MUX0 0 Analog Channel and Gain Selection Bit 0
|
||
; ACSR 0x0028 Analog Comparator Control and Status Register
|
||
; ACSR.ACD 7 Analog Comparator Disable
|
||
; ACSR.ACBG 6 Analog Comparator Bandgap Select
|
||
; ACSR.ACO 5 Analog Comparator Output
|
||
; ACSR.ACI 4 Analog Comparator Interrupt Flag
|
||
; ACSR.ACIE 3 Analog Comparator Interrupt Enable
|
||
; ACSR.ACIC 2 Analog Comparator Input Capture Enable
|
||
; ACSR.ACIS1 1 Analog Comparator Interrupt Mode Select 1
|
||
; ACSR.ACIS0 0 Analog Comparator Interrupt Mode Select 0
|
||
; UBRR0L 0x0029 USART Baud Rate Register
|
||
; UBRR0L.UBRR7 7 USART Baud Rate Register bit 7
|
||
; UBRR0L.UBRR6 6 USART Baud Rate Register bit 6
|
||
; UBRR0L.UBRR5 5 USART Baud Rate Register bit 5
|
||
; UBRR0L.UBRR4 4 USART Baud Rate Register bit 4
|
||
; UBRR0L.UBRR3 3 USART Baud Rate Register bit 3
|
||
; UBRR0L.UBRR2 2 USART Baud Rate Register bit 2
|
||
; UBRR0L.UBRR1 1 USART Baud Rate Register bit 1
|
||
; UBRR0L.UBRR0 0 USART Baud Rate Register bit 0
|
||
; UCSR0B 0x002A USART Control and Status Register B
|
||
; UCSR0B.RXCIE 7 RX Complete Interrupt Enable
|
||
; UCSR0B.TXCIE 6 TX Complete Interrupt Enable
|
||
; UCSR0B.UDRIE 5 USART Data Register Empty Interrupt Enable
|
||
; UCSR0B.RXEN 4 Receiver Enable
|
||
; UCSR0B.TXEN 3 Transmitter Enable
|
||
; UCSR0B.UCSZ2 2 Character Size
|
||
; UCSR0B.RXB8 1 Receive Data Bit 8
|
||
; UCSR0B.TXB8 0 Transmit Data Bit 8
|
||
; UCSR0A 0x002B USART Control and Status Register A
|
||
; UCSR0A.RXC 7 USART Receive Complete
|
||
; UCSR0A.TXC 6 USART Transmit Complete
|
||
; UCSR0A.UDRE 5 USART Data Register Empty
|
||
; UCSR0A.FE 4 Frame Error
|
||
; UCSR0A.DOR 3 Data OverRun
|
||
; UCSR0A.UPE 2 USART Parity Error
|
||
; UCSR0A.U2X 1 Double the USART Transmission Speed
|
||
; UCSR0A.MPCM 0 Multi-processor Communication Mode
|
||
; UDR0 0x002C USART0 I/O Data Register
|
||
; SPCR 0x002D SPI Control Register
|
||
; SPCR.SPIE 7 SPI Interrupt Enable
|
||
; SPCR.SPE 6 SPI Enable
|
||
; SPCR.DORD 5 Data Order
|
||
; SPCR.MSTR 4 Master/Slave Select
|
||
; SPCR.CPOL 3 Clock Polarity
|
||
; SPCR.CPHA 2 Clock Phase
|
||
; SPCR.SPR1 1 SPI Clock Rate Select 1
|
||
; SPCR.SPR0 0 SPI Clock Rate Select 0
|
||
; SPSR 0x002E SPI Status Register
|
||
; SPSR.SPIF 7 SPI Interrupt Flag
|
||
; SPSR.WCOL 6 Write COLlision Flag
|
||
; SPSR.SPI2X 0 Double SPI Speed Bit
|
||
; SPDR 0x002F SPI Data Register
|
||
; PIND 0x0030 Port D Input Pins Address
|
||
; PIND.PIND7 7
|
||
; PIND.PIND6 6
|
||
; PIND.PIND5 5
|
||
; PIND.PIND4 4
|
||
; PIND.PIND3 3
|
||
; PIND.PIND2 2
|
||
; PIND.PIND1 1
|
||
; PIND.PIND0 0
|
||
; DDRD 0x0031 Port D Data Direction Register
|
||
; DDRD.DDD7 7 Port D Data Direction Register bit 7
|
||
; DDRD.DDD6 6 Port D Data Direction Register bit 6
|
||
; DDRD.DDD5 5 Port D Data Direction Register bit 5
|
||
; DDRD.DDD4 4 Port D Data Direction Register bit 4
|
||
; DDRD.DDD3 3 Port D Data Direction Register bit 3
|
||
; DDRD.DDD2 2 Port D Data Direction Register bit 2
|
||
; DDRD.DDD1 1 Port D Data Direction Register bit 1
|
||
; DDRD.DDD0 0 Port D Data Direction Register bit 0
|
||
; PORTD 0x0032 Port D Data Register
|
||
; PORTD.PORTD7 7 Port D Data Register bit 7
|
||
; PORTD.PORTD6 6 Port D Data Register bit 6
|
||
; PORTD.PORTD5 5 Port D Data Register bit 5
|
||
; PORTD.PORTD4 4 Port D Data Register bit 4
|
||
; PORTD.PORTD3 3 Port D Data Register bit 3
|
||
; PORTD.PORTD2 2 Port D Data Register bit 2
|
||
; PORTD.PORTD1 1 Port D Data Register bit 1
|
||
; PORTD.PORTD0 0 Port D Data Register bit 0
|
||
; PINC 0x0033 Port C Input Pins Address
|
||
; PINC.PINC7 7
|
||
; PINC.PINC6 6
|
||
; PINC.PINC5 5
|
||
; PINC.PINC4 4
|
||
; PINC.PINC3 3
|
||
; PINC.PINC2 2
|
||
; PINC.PINC1 1
|
||
; PINC.PINC0 0
|
||
; DDRC 0x0034 Port C Data Direction Register
|
||
; DDRC.DDC7 7 Port C Data Direction Register bit 7
|
||
; DDRC.DDC6 6 Port C Data Direction Register bit 6
|
||
; DDRC.DDC5 5 Port C Data Direction Register bit 5
|
||
; DDRC.DDC4 4 Port C Data Direction Register bit 4
|
||
; DDRC.DDC3 3 Port C Data Direction Register bit 3
|
||
; DDRC.DDC2 2 Port C Data Direction Register bit 2
|
||
; DDRC.DDC1 1 Port C Data Direction Register bit 1
|
||
; DDRC.DDC0 0 Port C Data Direction Register bit 0
|
||
; PORTC 0x0035 Port C Data Register
|
||
; PORTC.PORTC7 7 Port C Data Register bit 7
|
||
; PORTC.PORTC6 6 Port C Data Register bit 6
|
||
; PORTC.PORTC5 5 Port C Data Register bit 5
|
||
; PORTC.PORTC4 4 Port C Data Register bit 4
|
||
; PORTC.PORTC3 3 Port C Data Register bit 3
|
||
; PORTC.PORTC2 2 Port C Data Register bit 2
|
||
; PORTC.PORTC1 1 Port C Data Register bit 1
|
||
; PORTC.PORTC0 0 Port C Data Register bit 0
|
||
; PINB 0x0036 Port B Input Pins Address
|
||
; PINB.PINB7 7
|
||
; PINB.PINB6 6
|
||
; PINB.PINB5 5
|
||
; PINB.PINB4 4
|
||
; PINB.PINB3 3
|
||
; PINB.PINB2 2
|
||
; PINB.PINB1 1
|
||
; PINB.PINB0 0
|
||
; DDRB 0x0037 Port B Data Direction Register
|
||
; DDRB.DDB7 7 Port B Data Direction Register bit 7
|
||
; DDRB.DDB6 6 Port B Data Direction Register bit 6
|
||
; DDRB.DDB5 5 Port B Data Direction Register bit 5
|
||
; DDRB.DDB4 4 Port B Data Direction Register bit 4
|
||
; DDRB.DDB3 3 Port B Data Direction Register bit 3
|
||
; DDRB.DDB2 2 Port B Data Direction Register bit 2
|
||
; DDRB.DDB1 1 Port B Data Direction Register bit 1
|
||
; DDRB.DDB0 0 Port B Data Direction Register bit 0
|
||
; PORTB 0x0038 Port B Data Register
|
||
; PORTB.PORTB7 7 Port B Data Register bit 7
|
||
; PORTB.PORTB6 6 Port B Data Register bit 6
|
||
; PORTB.PORTB5 5 Port B Data Register bit 5
|
||
; PORTB.PORTB4 4 Port B Data Register bit 4
|
||
; PORTB.PORTB3 3 Port B Data Register bit 3
|
||
; PORTB.PORTB2 2 Port B Data Register bit 2
|
||
; PORTB.PORTB1 1 Port B Data Register bit 1
|
||
; PORTB.PORTB0 0 Port B Data Register bit 0
|
||
; PINA 0x0039 Port A Input Pins Address
|
||
; PINA.PINA7 7
|
||
; PINA.PINA6 6
|
||
; PINA.PINA5 5
|
||
; PINA.PINA4 4
|
||
; PINA.PINA3 3
|
||
; PINA.PINA2 2
|
||
; PINA.PINA1 1
|
||
; PINA.PINA0 0
|
||
; DDRA 0x003A Port A Data Direction Register
|
||
; DDRA.DDA7 7 Port A Data Direction Register bit 7
|
||
; DDRA.DDA6 6 Port A Data Direction Register bit 6
|
||
; DDRA.DDA5 5 Port A Data Direction Register bit 5
|
||
; DDRA.DDA4 4 Port A Data Direction Register bit 4
|
||
; DDRA.DDA3 3 Port A Data Direction Register bit 3
|
||
; DDRA.DDA2 2 Port A Data Direction Register bit 2
|
||
; DDRA.DDA1 1 Port A Data Direction Register bit 1
|
||
; DDRA.DDA0 0 Port A Data Direction Register bit 0
|
||
; PORTA 0x003B Port A Data Register
|
||
; PORTA.PORTA7 7 Port A Data Register bit 7
|
||
; PORTA.PORTA6 6 Port A Data Register bit 6
|
||
; PORTA.PORTA5 5 Port A Data Register bit 5
|
||
; PORTA.PORTA4 4 Port A Data Register bit 4
|
||
; PORTA.PORTA3 3 Port A Data Register bit 3
|
||
; PORTA.PORTA2 2 Port A Data Register bit 2
|
||
; PORTA.PORTA1 1 Port A Data Register bit 1
|
||
; PORTA.PORTA0 0 Port A Data Register bit 0
|
||
; EECR 0x003C EEPROM Control Register
|
||
; EECR.EERIE 3 EEPROM Ready Interrupt Enable
|
||
; EECR.EEMWE 2 EEPROM Master Write Enable
|
||
; EECR.EEWE 1 EEPROM Write Enable
|
||
; EECR.EERE 0 EEPROM Read Enable
|
||
; EEDR 0x003D EEPROM Data Register
|
||
; EEDR.EEDR7 7 EEPROM Data 7
|
||
; EEDR.EEDR6 6 EEPROM Data 6
|
||
; EEDR.EEDR5 5 EEPROM Data 5
|
||
; EEDR.EEDR4 4 EEPROM Data 4
|
||
; EEDR.EEDR3 3 EEPROM Data 3
|
||
; EEDR.EEDR2 2 EEPROM Data 2
|
||
; EEDR.EEDR1 1 EEPROM Data 1
|
||
; EEDR.EEDR0 0 EEPROM Data 0
|
||
; EEARL 0x003E EEPROM Address Register Low
|
||
; EEARL.EEAR7 7 EEPROM Addres 7
|
||
; EEARL.EEAR6 6 EEPROM Addres 6
|
||
; EEARL.EEAR5 5 EEPROM Addres 5
|
||
; EEARL.EEAR4 4 EEPROM Addres 4
|
||
; EEARL.EEAR3 3 EEPROM Addres 3
|
||
; EEARL.EEAR2 2 EEPROM Addres 2
|
||
; EEARL.EEAR1 1 EEPROM Addres 1
|
||
; EEARL.EEAR0 0 EEPROM Addres 0
|
||
; EEARH 0x003F EEPROM Address Register High
|
||
; EEARH.EEAR10 10 EEPROM Addres 10
|
||
; EEARH.EEAR9 9 EEPROM Addres 9
|
||
; EEARH.EEAR8 8 EEPROM Addres 8
|
||
; SFIOR 0x0040 Special Function IO Register
|
||
; SFIOR.TSM 7 Timer/Counter Synchronization Mode
|
||
; SFIOR.ADHSM 4 ADC High Speed Mode
|
||
; SFIOR.ACME 3 Analog Comparator Multiplexer Enable
|
||
; SFIOR.PUD 2 Pull-up disable
|
||
; SFIOR.PSR0 1 Prescaler Reset Timer/Counter0
|
||
; SFIOR.PSR321 0 Prescaler Reset Timer/Counter3, Timer/Counter2, and Timer/Counter1
|
||
; WDTCR 0x0041 Watchdog Timer Control Register
|
||
; WDTCR.WDCE 4 Watchdog Change Enable
|
||
; WDTCR.WDE 3 Watchdog Enable
|
||
; WDTCR.WDP2 2 Watchdog Timer Prescaler 2
|
||
; WDTCR.WDP1 1 Watchdog Timer Prescaler 1
|
||
; WDTCR.WDP0 0 Watchdog Timer Prescaler 0
|
||
; OCDR 0x0042 On-chip Debug Register
|
||
; OCDR.IDRD_OCDR7 7
|
||
; OCDR.OCDR6 6
|
||
; OCDR.OCDR5 5
|
||
; OCDR.OCDR4 4
|
||
; OCDR.OCDR3 3
|
||
; OCDR.OCDR2 2
|
||
; OCDR.OCDR1 1
|
||
; OCDR.OCDR0 0
|
||
; OCR2 0x0043 Output Compare Register
|
||
; OCR2.OCR2_7 7
|
||
; OCR2.OCR2_6 6
|
||
; OCR2.OCR2_5 5
|
||
; OCR2.OCR2_4 4
|
||
; OCR2.OCR2_3 3
|
||
; OCR2.OCR2_2 2
|
||
; OCR2.OCR2_1 1
|
||
; OCR2.OCR2_0 0
|
||
; TCNT2 0x0044 Timer/Counter Register
|
||
; TCNT2.TCNT2_7 7
|
||
; TCNT2.TCNT2_6 6
|
||
; TCNT2.TCNT2_5 5
|
||
; TCNT2.TCNT2_4 4
|
||
; TCNT2.TCNT2_3 3
|
||
; TCNT2.TCNT2_2 2
|
||
; TCNT2.TCNT2_1 1
|
||
; TCNT2.TCNT2_0 0
|
||
; TCCR2 0x0045 Timer/Counter Control Register
|
||
; TCCR2.FOC2 7 Force Output Compare
|
||
; TCCR2.WGM20 6 Waveform Generation Mode 0
|
||
; TCCR2.COM21 5 Compare Match Output Mode 1
|
||
; TCCR2.COM20 4 Compare Match Output Mode 0
|
||
; TCCR2.WGM21 3 Waveform Generation Mode 1
|
||
; TCCR2.CS22 2 Clock Select 2
|
||
; TCCR2.CS21 1 Clock Select 1
|
||
; TCCR2.CS20 0 Clock Select 0
|
||
; ICR1L 0x0046 Input Capture Register 1 Low
|
||
; ICR1L.ICR1_7 7
|
||
; ICR1L.ICR1_6 6
|
||
; ICR1L.ICR1_5 5
|
||
; ICR1L.ICR1_4 4
|
||
; ICR1L.ICR1_3 3
|
||
; ICR1L.ICR1_2 2
|
||
; ICR1L.ICR1_1 1
|
||
; ICR1L.ICR1_0 0
|
||
; ICR1H 0x0047 Input Capture Register 1 High
|
||
; ICR1H.ICR1_15 15
|
||
; ICR1H.ICR1_14 14
|
||
; ICR1H.ICR1_13 13
|
||
; ICR1H.ICR1_12 12
|
||
; ICR1H.ICR1_11 11
|
||
; ICR1H.ICR1_10 10
|
||
; ICR1H.ICR1_9 9
|
||
; ICR1H.ICR1_8 8
|
||
; OCR1BL 0x0048 Output Compare Register 1 B Low
|
||
; OCR1BL.OCR1B_7 7
|
||
; OCR1BL.OCR1B_6 6
|
||
; OCR1BL.OCR1B_5 5
|
||
; OCR1BL.OCR1B_4 4
|
||
; OCR1BL.OCR1B_3 3
|
||
; OCR1BL.OCR1B_2 2
|
||
; OCR1BL.OCR1B_1 1
|
||
; OCR1BL.OCR1B_0 0
|
||
; OCR1BH 0x0049 Output Compare Register 1 B High
|
||
; OCR1BH.OCR1B_15 15
|
||
; OCR1BH.OCR1B_14 14
|
||
; OCR1BH.OCR1B_13 13
|
||
; OCR1BH.OCR1B_12 12
|
||
; OCR1BH.OCR1B_11 11
|
||
; OCR1BH.OCR1B_10 10
|
||
; OCR1BH.OCR1B_9 9
|
||
; OCR1BH.OCR1B_8 8
|
||
; OCR1AL 0x004A Output Compare Register 1 A Low
|
||
; OCR1AL.OCR1A_7 7
|
||
; OCR1AL.OCR1A_6 6
|
||
; OCR1AL.OCR1A_5 5
|
||
; OCR1AL.OCR1A_4 4
|
||
; OCR1AL.OCR1A_3 3
|
||
; OCR1AL.OCR1A_2 2
|
||
; OCR1AL.OCR1A_1 1
|
||
; OCR1AL.OCR1A_0 0
|
||
; OCR1AH 0x004B Output Compare Register 1 A High
|
||
; OCR1AH.OCR1A_15 15
|
||
; OCR1AH.OCR1A_14 14
|
||
; OCR1AH.OCR1A_13 13
|
||
; OCR1AH.OCR1A_12 12
|
||
; OCR1AH.OCR1A_11 11
|
||
; OCR1AH.OCR1A_10 10
|
||
; OCR1AH.OCR1A_9 9
|
||
; OCR1AH.OCR1A_8 8
|
||
; TCNT1L 0x004C Timer/Counter 1 Low
|
||
; TCNT1L.TCNT1_7 7
|
||
; TCNT1L.TCNT1_6 6
|
||
; TCNT1L.TCNT1_5 5
|
||
; TCNT1L.TCNT1_4 4
|
||
; TCNT1L.TCNT1_3 3
|
||
; TCNT1L.TCNT1_2 2
|
||
; TCNT1L.TCNT1_1 1
|
||
; TCNT1L.TCNT1_0 0
|
||
; TCNT1H 0x004D Timer/Counter 1 High
|
||
; TCNT1H.TCNT1_15 15
|
||
; TCNT1H.TCNT1_14 14
|
||
; TCNT1H.TCNT1_13 13
|
||
; TCNT1H.TCNT1_12 12
|
||
; TCNT1H.TCNT1_11 11
|
||
; TCNT1H.TCNT1_10 10
|
||
; TCNT1H.TCNT1_9 9
|
||
; TCNT1H.TCNT1_8 8
|
||
; TCCR1B 0x004E Timer/Counter 1 Control Register B
|
||
; TCCR1B.ICNC1 7 Input Capture Noise Canceler
|
||
; TCCR1B.ICES1 6 Input Capture Edge Select
|
||
; TCCR1B.WGM13 4 Waveform Generation Mode 3
|
||
; TCCR1B.WGM12 3 Waveform Generation Mode 2
|
||
; TCCR1B.CS12 2 Clock Select 2
|
||
; TCCR1B.CS11 1 Clock Select 1
|
||
; TCCR1B.CS10 0 Clock Select 0
|
||
; TCCR1A 0x004F Timer/Counter 1 Control Register A
|
||
; TCCR1A.COM1A1 7 Compare Output Mode for Channel A 1
|
||
; TCCR1A.COM1A0 6 Compare Output Mode for Channel A 0
|
||
; TCCR1A.COM1B1 5 Compare Output Mode for Channel B 1
|
||
; TCCR1A.COM1B0 4 Compare Output Mode for Channel B 0
|
||
; TCCR1A.COM1C1 3 Compare Output Mode for Channel C 1
|
||
; TCCR1A.COM1C0 2 Compare Output Mode for Channel C 0
|
||
; TCCR1A.WGM11 1 Waveform Generation Mode 1
|
||
; TCCR1A.WGM10 0 Waveform Generation Mode 0
|
||
; ASSR 0x0050 Asynchronous Status Register
|
||
; ASSR.AS0 3 Asynchronous Timer/Counter0
|
||
; ASSR.TCN0UB 2 Timer/Counter0 Update Busy
|
||
; ASSR.OCR0UB 1 Output Compare Register0 Update Busy
|
||
; ASSR.TCR0UB 0 Timer/Counter Control Register0 Update Busy
|
||
; OCR0 0x0051 Output Compare Register
|
||
; OCR0.OCR0_7 7
|
||
; OCR0.OCR0_6 6
|
||
; OCR0.OCR0_5 5
|
||
; OCR0.OCR0_4 4
|
||
; OCR0.OCR0_3 3
|
||
; OCR0.OCR0_2 2
|
||
; OCR0.OCR0_1 1
|
||
; OCR0.OCR0_0 0
|
||
; TCNT0 0x0052 Timer/Counter Register
|
||
; TCNT0.TCNT0_7 7
|
||
; TCNT0.TCNT0_6 6
|
||
; TCNT0.TCNT0_5 5
|
||
; TCNT0.TCNT0_4 4
|
||
; TCNT0.TCNT0_3 3
|
||
; TCNT0.TCNT0_2 2
|
||
; TCNT0.TCNT0_1 1
|
||
; TCNT0.TCNT0_0 0
|
||
; TCCR0 0x0053 Timer/Counter Control Register
|
||
; TCCR0.FOC0 7 Force Output Compare
|
||
; TCCR0.WGM00 6 Waveform Generation Mode 0
|
||
; TCCR0.COM01 5 Compare Match Output Mode 1
|
||
; TCCR0.COM00 4 Compare Match Output Mode 0
|
||
; TCCR0.WGM01 3 Waveform Generation Mode 1
|
||
; TCCR0.CS02 2 Clock Select 2
|
||
; TCCR0.CS01 1 Clock Select 1
|
||
; TCCR0.CS00 0 Clock Select 0
|
||
; MCUCSR 0x0054 MCU Control and Status Register
|
||
; MCUCSR.JTD 7 JTAG interface disable
|
||
; MCUCSR.JTRF 4 JTAG Reset Flag
|
||
; MCUCSR.WDRF 3 Watchdog Reset Flag
|
||
; MCUCSR.BORF 2 Brown-out Reset Flag
|
||
; MCUCSR.EXTRF 1 External Reset Flag
|
||
; MCUCSR.PORF 0 Power-on Reset Flag
|
||
; MCUCR 0x0055 MCU Control Register
|
||
; MCUCR.SRE 7 External SRAM/XMEM Enable
|
||
; MCUCR.SRW10 6 Wait State Select Bit
|
||
; MCUCR.SE 5 Sleep Enable
|
||
; MCUCR.SM1 4 Sleep Mode Select Bit 1
|
||
; MCUCR.SM0 3 Sleep Mode Select Bit 0
|
||
; MCUCR.SM2 2 Sleep Mode Select Bit 2
|
||
; MCUCR.IVSEL 1 Interrupt Vector Select
|
||
; MCUCR.IVCE 0 Interrupt Vector Change Enable
|
||
; TIFR 0x0056 Timer/Counter Interrupt Flag Register
|
||
; TIFR.OCF2 7 Output Compare Flag 2
|
||
; TIFR.TOV2 6 Timer/Counter2 Overflow Flag
|
||
; TIFR.ICF1 5 Timer/Counter1, Input Capture Flag
|
||
; TIFR.OCF1A 4 Timer/Counter1, Output Compare A Match Flag
|
||
; TIFR.OCF1B 3 Timer/Counter1, Output Compare B Match Flag
|
||
; TIFR.TOV1 2 Timer/Counter1, Overflow Flag
|
||
; TIFR.OCF0 1 Output Compare Flag 0
|
||
; TIFR.TOV0 0 Timer/Counter0 Overflow Flag
|
||
; TIMSK 0x0057 Timer/Counter Interrupt Mask Register
|
||
; TIMSK.OCIE2 7 Timer/Counter2 Output Compare Match Interrupt Enable
|
||
; TIMSK.TOIE2 6 Timer/Counter2 Overflow Interrupt Enable
|
||
; TIMSK.TICIE1 5 Timer/Counter1, Input Capture Interrupt Enable
|
||
; TIMSK.OCIE1A 4 Timer/Counter1, Output Compare A Match Interrupt Enable
|
||
; TIMSK.OCIE1B 3 Timer/Counter1, Output Compare B Match Interrupt Enable
|
||
; TIMSK.TOIE1 2 Timer/Counter1, Overflow Interrupt Enable
|
||
; TIMSK.OCIE0 1 Timer/Counter0 Output Compare Match Interrupt Enable
|
||
; TIMSK.TOIE0 0 Timer/Counter0 Overflow Interrupt Enable
|
||
; EIFR 0x0058 External Interrupt Flag Register
|
||
; EIFR.INTF7 7 External Interrupt Flag 7
|
||
; EIFR.INTF6 6 External Interrupt Flag 6
|
||
; EIFR.INTF5 5 External Interrupt Flag 5
|
||
; EIFR.INTF4 4 External Interrupt Flag 4
|
||
; EIFR.INTF3 3 External Interrupt Flag 3
|
||
; EIFR.INTF2 2 External Interrupt Flag 2
|
||
; EIFR.INTF1 1 External Interrupt Flag 1
|
||
; EIFR.INTF0 0 External Interrupt Flag 0
|
||
; EIMSK 0x0059 External Interrupt Mask Register
|
||
; EIMSK.INT7 7 External Interrupt Request 7 Enable
|
||
; EIMSK.INT6 6 External Interrupt Request 6 Enable
|
||
; EIMSK.INT5 5 External Interrupt Request 5 Enable
|
||
; EIMSK.INT4 4 External Interrupt Request 4 Enable
|
||
; EIMSK.INT3 3 External Interrupt Request 3 Enable
|
||
; EIMSK.INT2 2 External Interrupt Request 2 Enable
|
||
; EIMSK.INT1 1 External Interrupt Request 1 Enable
|
||
; EIMSK.INT0 0 External Interrupt Request 0 Enable
|
||
; EICRB 0x005A External Interrupt Control Register B
|
||
; EICRB.ISC71 7 External Interrupt 7 Sense Control Bit 1
|
||
; EICRB.ISC70 6 External Interrupt 7 Sense Control Bit 0
|
||
; EICRB.ISC61 5 External Interrupt 6 Sense Control Bit 1
|
||
; EICRB.ISC60 4 External Interrupt 6 Sense Control Bit 0
|
||
; EICRB.ISC51 3 External Interrupt 5 Sense Control Bit 1
|
||
; EICRB.ISC50 2 External Interrupt 5 Sense Control Bit 0
|
||
; EICRB.ISC41 1 External Interrupt 4 Sense Control Bit 1
|
||
; EICRB.ISC40 0 External Interrupt 4 Sense Control Bit 0
|
||
; RESERVED005B 0x005B RESERVED
|
||
; XDIV 0x005C XTAL Divide Control Register
|
||
; XDIV.XDIVEN 7 XTAL Divide Enable
|
||
; XDIV.XDIV6 6 XTAL Divide Select Bit 6
|
||
; XDIV.XDIV5 5 XTAL Divide Select Bit 5
|
||
; XDIV.XDIV4 4 XTAL Divide Select Bit 4
|
||
; XDIV.XDIV3 3 XTAL Divide Select Bit 3
|
||
; XDIV.XDIV2 2 XTAL Divide Select Bit 2
|
||
; XDIV.XDIV1 1 XTAL Divide Select Bit 1
|
||
; XDIV.XDIV0 0 XTAL Divide Select Bit 0
|
||
; SPL 0x005D Stack Pointer Low
|
||
; SPL.SP7 7
|
||
; SPL.SP6 6
|
||
; SPL.SP5 5
|
||
; SPL.SP4 4
|
||
; SPL.SP3 3
|
||
; SPL.SP2 2
|
||
; SPL.SP1 1
|
||
; SPL.SP0 0
|
||
; SPH 0x005E Stack Pointer High
|
||
; SPH.SP15 15
|
||
; SPH.SP14 14
|
||
; SPH.SP13 13
|
||
; SPH.SP12 12
|
||
; SPH.SP11 11
|
||
; SPH.SP10 10
|
||
; SPH.SP9 9
|
||
; SPH.SP8 8
|
||
; SREG 0x005F Status Register
|
||
; SREG.I 7 Global Interrupt Enable
|
||
; SREG.T 6 Bit Copy Storage
|
||
; SREG.H 5 Half Carry Flag
|
||
; SREG.S 4 Sign Bit
|
||
; SREG.V 3 Two's Complement Overflow Flag
|
||
; SREG.N 2 Negative Flag
|
||
; SREG.Z 1 Zero Flag
|
||
; SREG.C 0 Carry Flag
|
||
; RESERVED0060 0x0060 RESERVED
|
||
; DDRF 0x0061 Port F Data Direction Register
|
||
; DDRF.DDF7 7 Port F Data Direction Register bit 7
|
||
; DDRF.DDF6 6 Port F Data Direction Register bit 6
|
||
; DDRF.DDF5 5 Port F Data Direction Register bit 5
|
||
; DDRF.DDF4 4 Port F Data Direction Register bit 4
|
||
; DDRF.DDF3 3 Port F Data Direction Register bit 3
|
||
; DDRF.DDF2 2 Port F Data Direction Register bit 2
|
||
; DDRF.DDF1 1 Port F Data Direction Register bit 1
|
||
; DDRF.DDF0 0 Port F Data Direction Register bit 0
|
||
; PORTF 0x0062 Port F Data Register
|
||
; PORTF.PORTF 7 Port F Data Register bit 7
|
||
; PORTF.PORTF 6 Port F Data Register bit 6
|
||
; PORTF.PORTF 5 Port F Data Register bit 5
|
||
; PORTF.PORTF 4 Port F Data Register bit 4
|
||
; PORTF.PORTF 3 Port F Data Register bit 3
|
||
; PORTF.PORTF 2 Port F Data Register bit 2
|
||
; PORTF.PORTF 1 Port F Data Register bit 1
|
||
; PORTF.PORTF 0 Port F Data Register bit 0
|
||
; PING 0x0063 Port G Input Pins Address
|
||
; PING.PING4 4
|
||
; PING.PING3 3
|
||
; PING.PING2 2
|
||
; PING.PING1 1
|
||
; PING.PING0 0
|
||
; DDRG 0x0064 Port G Data Direction Register
|
||
; DDRG.DDG4 4 Port G Data Direction Register bit 4
|
||
; DDRG.DDG3 3 Port G Data Direction Register bit 3
|
||
; DDRG.DDG2 2 Port G Data Direction Register bit 2
|
||
; DDRG.DDG1 1 Port G Data Direction Register bit 1
|
||
; DDRG.DDG0 0 Port G Data Direction Register bit 0
|
||
; PORTG 0x0065 Port G Data Register
|
||
; PORTG.PORTG4 4 Port G Data Register bit 4
|
||
; PORTG.PORTG3 3 Port G Data Register bit 3
|
||
; PORTG.PORTG2 2 Port G Data Register bit 2
|
||
; PORTG.PORTG1 1 Port G Data Register bit 1
|
||
; PORTG.PORTG0 0 Port G Data Register bit 0
|
||
; RESERVED0066 0x0066 RESERVED
|
||
; RESERVED0067 0x0067 RESERVED
|
||
; SPMCR 0x0068 Store Program Memory Control Register
|
||
; SPMCR.SPMIE 7 SPM Interrupt Enable
|
||
; SPMCR.RWWSB 6 Read-While-Write Section Busy
|
||
; SPMCR.RWWSRE 4 Read-While-Write Section Read Enable
|
||
; SPMCR.BLBSET 3 Boot Lock Bit Set
|
||
; SPMCR.PGWRT 2 Page Write
|
||
; SPMCR.PGERS 1 Page Erase
|
||
; SPMCR.SPMEN 0 Store Program Memory Enable
|
||
; RESERVED0069 0x0069 RESERVED
|
||
; EICRA 0x006A External Interrupt Control Register A
|
||
; EICRA.ISC31 7 External Interrupt 3 Sense Control Bit 1
|
||
; EICRA.ISC30 6 External Interrupt 3 Sense Control Bit 0
|
||
; EICRA.ISC21 5 External Interrupt 2 Sense Control Bit 1
|
||
; EICRA.ISC20 4 External Interrupt 2 Sense Control Bit 0
|
||
; EICRA.ISC11 3 External Interrupt 1 Sense Control Bit 1
|
||
; EICRA.ISC10 2 External Interrupt 1 Sense Control Bit 0
|
||
; EICRA.ISC01 1 External Interrupt 0 Sense Control Bit 1
|
||
; EICRA.ISC00 0 External Interrupt 0 Sense Control Bit 0
|
||
; RESERVED006B 0x006B RESERVED
|
||
; XMCRB 0x006C External Memory Control Register B
|
||
; XMCRB.XMBK 7 External Memory Bus-keeper Enable
|
||
; XMCRB.XMM2 2 External Memory High Mask 2
|
||
; XMCRB.XMM1 1 External Memory High Mask 1
|
||
; XMCRB.XMM0 0 External Memory High Mask 0
|
||
; XMCRA 0x006D External Memory Control Register A
|
||
; XMCRA.SRL2 6 Wait State Sector Limit 2
|
||
; XMCRA.SRL1 5 Wait State Sector Limit 1
|
||
; XMCRA.SRL0 4 Wait State Sector Limit 0
|
||
; XMCRA.SRW01 3 Wait State Select Bits for Lower Sector
|
||
; XMCRA.SRW00 2 Wait State Select Bits for Lower Sector
|
||
; XMCRA.SRW11 1 Wait State Select Bits for Upper Sector
|
||
; RESERVED006E 0x006E RESERVED
|
||
; OSCCAL 0x006F Oscillator Calibration Register
|
||
; OSCCAL.CAL7 7 Oscillator Calibration Value 7
|
||
; OSCCAL.CAL6 6 Oscillator Calibration Value 6
|
||
; OSCCAL.CAL5 5 Oscillator Calibration Value 5
|
||
; OSCCAL.CAL4 4 Oscillator Calibration Value 4
|
||
; OSCCAL.CAL3 3 Oscillator Calibration Value 3
|
||
; OSCCAL.CAL2 2 Oscillator Calibration Value 2
|
||
; OSCCAL.CAL1 1 Oscillator Calibration Value 1
|
||
; OSCCAL.CAL0 0 Oscillator Calibration Value 0
|
||
; TWBR 0x0070 TWI Bit Rate Register
|
||
; TWBR.TWBR7 7 TWI Bit Rate Register bit 7
|
||
; TWBR.TWBR6 6 TWI Bit Rate Register bit 6
|
||
; TWBR.TWBR5 5 TWI Bit Rate Register bit 5
|
||
; TWBR.TWBR4 4 TWI Bit Rate Register bit 4
|
||
; TWBR.TWBR3 3 TWI Bit Rate Register bit 3
|
||
; TWBR.TWBR2 2 TWI Bit Rate Register bit 2
|
||
; TWBR.TWBR1 1 TWI Bit Rate Register bit 1
|
||
; TWBR.TWBR0 0 TWI Bit Rate Register bit 0
|
||
; TWSR 0x0071 TWI Status Register
|
||
; TWSR.TWS7 7 TWI Status bit 7
|
||
; TWSR.TWS6 6 TWI Status bit 6
|
||
; TWSR.TWS5 5 TWI Status bit 5
|
||
; TWSR.TWS4 4 TWI Status bit 4
|
||
; TWSR.TWS3 3 TWI Status bit 3
|
||
; TWSR.TWS1 1 TWI Status bit 1
|
||
; TWSR.TWS0 0 TWI Status bit 0
|
||
; TWAR 0x0072 TWI (Slave) Address Register
|
||
; TWAR.TWA6 7 TWI (Slave) Address Register bit 6
|
||
; TWAR.TWA5 6 TWI (Slave) Address Register bit 5
|
||
; TWAR.TWA4 5 TWI (Slave) Address Register bit 4
|
||
; TWAR.TWA3 4 TWI (Slave) Address Register bit 3
|
||
; TWAR.TWA2 3 TWI (Slave) Address Register bit 2
|
||
; TWAR.TWA1 2 TWI (Slave) Address Register bit 1
|
||
; TWAR.TWA0 1 TWI (Slave) Address Register bit 0
|
||
; TWAR.TWGCE 0 TWI General Call Recognition Enable Bit
|
||
; TWDR 0x0073 TWI Data Register
|
||
; TWDR.TWD7 7 TWI Data Register bit 7
|
||
; TWDR.TWD6 6 TWI Data Register bit 6
|
||
; TWDR.TWD5 5 TWI Data Register bit 5
|
||
; TWDR.TWD4 4 TWI Data Register bit 4
|
||
; TWDR.TWD3 3 TWI Data Register bit 3
|
||
; TWDR.TWD2 2 TWI Data Register bit 2
|
||
; TWDR.TWD1 1 TWI Data Register bit 1
|
||
; TWDR.TWD0 0 TWI Data Register bit 0
|
||
; TWCR 0x0074 TWI Control Register
|
||
; TWCR.TWINT 7 TWI Interrupt Flag
|
||
; TWCR.TWEA 6 TWI Enable Acknowledge Bit
|
||
; TWCR.TWSTA 5 TWI START Condition Bit
|
||
; TWCR.TWSTO 4 TWI STOP Condition Bit
|
||
; TWCR.TWWC 3 TWI Write Collision Flag
|
||
; TWCR.TWEN 2 TWI Enable Bit
|
||
; TWCR.TWIE 0 TWI Interrupt Enable
|
||
; RESERVED0075 0x0075 RESERVED
|
||
; RESERVED0076 0x0076 RESERVED
|
||
; RESERVED0077 0x0077 RESERVED
|
||
; OCR1CL 0x0078 Output Compare Register 1 C Low
|
||
; OCR1CL.OCR1C7 7
|
||
; OCR1CL.OCR1C6 6
|
||
; OCR1CL.OCR1C5 5
|
||
; OCR1CL.OCR1C4 4
|
||
; OCR1CL.OCR1C3 3
|
||
; OCR1CL.OCR1C2 2
|
||
; OCR1CL.OCR1C1 1
|
||
; OCR1CL.OCR1C0 0
|
||
; OCR1CH 0x0079 Output Compare Register 1 C High
|
||
; OCR1CH.OCR1C15 15
|
||
; OCR1CH.OCR1C14 14
|
||
; OCR1CH.OCR1C13 13
|
||
; OCR1CH.OCR1C12 12
|
||
; OCR1CH.OCR1C11 11
|
||
; OCR1CH.OCR1C10 10
|
||
; OCR1CH.OCR1C9 9
|
||
; OCR1CH.OCR1C8 8
|
||
; TCCR1C 0x007A Timer/Counter 1 Control Register C
|
||
; TCCR1C.FOC1A 7 Force Output Compare for Channel A
|
||
; TCCR1C.FOC1B 6 Force Output Compare for Channel B
|
||
; TCCR1C.FOC1C 5 Force Output Compare for Channel C
|
||
; RESERVED007B 0x007B RESERVED
|
||
; ETIFR 0x007C Extended Timer/Counter Interrupt Flag Register
|
||
; ETIFR.ICF3 5 Timer/Counter3, Input Capture Flag
|
||
; ETIFR.OCF3A 4 Timer/Counter3, Output Compare A Match Flag
|
||
; ETIFR.OCF3B 3 Timer/Counter3, Output Compare B Match Flag
|
||
; ETIFR.TOV3 2 Timer/Counter3, Overflow Flag
|
||
; ETIFR.OCF3C 1 Timer/Counter3, Output Compare C Match Flag
|
||
; ETIFR.OCF1C 0 Timer/Counter1, Output Compare C Match Flag
|
||
; ETIMSK 0x007D Extended Timer/Counter Interrupt Mask Register
|
||
; ETIMSK.TICIE3 5 Timer/Counter3, Input Capture Interrupt Enable
|
||
; ETIMSK.OCIE3A 4 Timer/Counter3, Output Compare A Match Interrupt Enable
|
||
; ETIMSK.OCIE3B 3 Timer/Counter3, Output Compare B Match Interrupt Enable
|
||
; ETIMSK.TOIE3 2 Timer/Counter3, Overflow Interrupt Enable
|
||
; ETIMSK.OCIE3C 1 Timer/Counter3, Output Compare C Match Interrupt Enable
|
||
; ETIMSK.OCIE1C 0 Timer/Counter1, Output Compare C Match Interrupt Enable
|
||
; RESERVED007E 0x007E RESERVED
|
||
; RESERVED007F 0x007F RESERVED
|
||
; ICR3L 0x0080 Input Capture Register 3 Low
|
||
; ICR3L.ICR3_7 7
|
||
; ICR3L.ICR3_6 6
|
||
; ICR3L.ICR3_5 5
|
||
; ICR3L.ICR3_4 4
|
||
; ICR3L.ICR3_3 3
|
||
; ICR3L.ICR3_2 2
|
||
; ICR3L.ICR3_1 1
|
||
; ICR3L.ICR3_0 0
|
||
; ICR3H 0x0081 Input Capture Register 3 High
|
||
; ICR3H.ICR3_15 15
|
||
; ICR3H.ICR3_14 14
|
||
; ICR3H.ICR3_13 13
|
||
; ICR3H.ICR3_12 12
|
||
; ICR3H.ICR3_11 11
|
||
; ICR3H.ICR3_10 10
|
||
; ICR3H.ICR3_9 9
|
||
; ICR3H.ICR3_8 8
|
||
; OCR3CL 0x0082 Output Compare Register 3 C Low
|
||
; OCR3CL.OCR3C_7 7
|
||
; OCR3CL.OCR3C_6 6
|
||
; OCR3CL.OCR3C_5 5
|
||
; OCR3CL.OCR3C_4 4
|
||
; OCR3CL.OCR3C_3 3
|
||
; OCR3CL.OCR3C_2 2
|
||
; OCR3CL.OCR3C_1 1
|
||
; OCR3CL.OCR3C_0 0
|
||
; OCR3CH 0x0083 Output Compare Register 3 C High
|
||
; OCR3CH.OCR3C_15 15
|
||
; OCR3CH.OCR3C_14 14
|
||
; OCR3CH.OCR3C_13 13
|
||
; OCR3CH.OCR3C_12 12
|
||
; OCR3CH.OCR3C_11 11
|
||
; OCR3CH.OCR3C_10 10
|
||
; OCR3CH.OCR3C_9 9
|
||
; OCR3CH.OCR3C_8 8
|
||
; OCR3BL 0x0084 Output Compare Register 3 B Low
|
||
; OCR3BL.OCR3B_7 7
|
||
; OCR3BL.OCR3B_6 6
|
||
; OCR3BL.OCR3B_5 5
|
||
; OCR3BL.OCR3B_4 4
|
||
; OCR3BL.OCR3B_3 3
|
||
; OCR3BL.OCR3B_2 2
|
||
; OCR3BL.OCR3B_1 1
|
||
; OCR3BL.OCR3B_0 0
|
||
; OCR3BH 0x0085 Output Compare Register 3 B High
|
||
; OCR3BH.OCR3B_15 15
|
||
; OCR3BH.OCR3B_14 14
|
||
; OCR3BH.OCR3B_13 13
|
||
; OCR3BH.OCR3B_12 12
|
||
; OCR3BH.OCR3B_11 11
|
||
; OCR3BH.OCR3B_10 10
|
||
; OCR3BH.OCR3B_9 9
|
||
; OCR3BH.OCR3B_8 8
|
||
; OCR3AL 0x0086 Output Compare Register 3 A Low
|
||
; OCR3AL.OCR3A_7 7
|
||
; OCR3AL.OCR3A_6 6
|
||
; OCR3AL.OCR3A_5 5
|
||
; OCR3AL.OCR3A_4 4
|
||
; OCR3AL.OCR3A_3 3
|
||
; OCR3AL.OCR3A_2 2
|
||
; OCR3AL.OCR3A_1 1
|
||
; OCR3AL.OCR3A_0 0
|
||
; OCR3AH 0x0087 Output Compare Register 3 A High
|
||
; OCR3AH.OCR3A_15 15
|
||
; OCR3AH.OCR3A_14 14
|
||
; OCR3AH.OCR3A_13 13
|
||
; OCR3AH.OCR3A_12 12
|
||
; OCR3AH.OCR3A_11 11
|
||
; OCR3AH.OCR3A_10 10
|
||
; OCR3AH.OCR3A_9 9
|
||
; OCR3AH.OCR3A_8 8
|
||
; TCNT3L 0x0088 Timer/Counter 3 Low
|
||
; TCNT3L.TCNT3_7 7
|
||
; TCNT3L.TCNT3_6 6
|
||
; TCNT3L.TCNT3_5 5
|
||
; TCNT3L.TCNT3_4 4
|
||
; TCNT3L.TCNT3_3 3
|
||
; TCNT3L.TCNT3_2 2
|
||
; TCNT3L.TCNT3_1 1
|
||
; TCNT3L.TCNT3_0 0
|
||
; TCNT3H 0x0089 Timer/Counter 3 High
|
||
; TCNT3H.TCNT3_15 15
|
||
; TCNT3H.TCNT3_14 14
|
||
; TCNT3H.TCNT3_13 13
|
||
; TCNT3H.TCNT3_12 12
|
||
; TCNT3H.TCNT3_11 11
|
||
; TCNT3H.TCNT3_10 10
|
||
; TCNT3H.TCNT3_9 9
|
||
; TCNT3H.TCNT3_8 8
|
||
; TCCR3B 0x008A Timer/Counter 3 Control Register B
|
||
; TCCR3B.ICNC3 7 Input Capture Noise Canceler
|
||
; TCCR3B.ICES3 6 Input Capture Edge Select
|
||
; TCCR3B.WGM33 4 Waveform Generation Mode 3
|
||
; TCCR3B.WGM32 3 Waveform Generation Mode 2
|
||
; TCCR3B.CS32 2 Clock Select 2
|
||
; TCCR3B.CS31 1 Clock Select 1
|
||
; TCCR3B.CS30 0 Clock Select 0
|
||
; TCCR3A 0x008B Timer/Counter 3 Control Register A
|
||
; TCCR3A.COM3A1 7 Compare Output Mode for Channel A 1
|
||
; TCCR3A.COM3A0 6 Compare Output Mode for Channel A 0
|
||
; TCCR3A.COM3B1 5 Compare Output Mode for Channel B 1
|
||
; TCCR3A.COM3B0 4 Compare Output Mode for Channel B 0
|
||
; TCCR3A.COM3C1 3 Compare Output Mode for Channel C 1
|
||
; TCCR3A.COM3C0 2 Compare Output Mode for Channel C 0
|
||
; TCCR3A.WGM31 1 Waveform Generation Mode 1
|
||
; TCCR3A.WGM30 0 Waveform Generation Mode 0
|
||
; TCCR3C 0x008C Timer/Counter 3 Control Register C
|
||
; TCCR3C.FOC3A 7 Force Output Compare for Channel A
|
||
; TCCR3C.FOC3B 6 Force Output Compare for Channel B
|
||
; TCCR3C.FOC3C 5 Force Output Compare for Channel C
|
||
; RESERVED008D 0x008D RESERVED
|
||
; ADCSRB 0x008E ADC Control and Status Register B
|
||
; ADCSRB.ADTS2 2 ADC Auto Trigger Source 2
|
||
; ADCSRB.ADTS1 1 ADC Auto Trigger Source 1
|
||
; ADCSRB.ADTS0 0 ADC Auto Trigger Source 0
|
||
; RESERVED008F 0x008F RESERVED
|
||
; UBRR0H 0x0090 USART Baud Rate Register High
|
||
; UBRR0H.UBRR11 11 USART Baud Rate Register bit 11
|
||
; UBRR0H.UBRR10 10 USART Baud Rate Register bit 10
|
||
; UBRR0H.UBRR9 9 USART Baud Rate Register bit 9
|
||
; UBRR0H.UBRR8 8 USART Baud Rate Register bit 8
|
||
; RESERVED0091 0x0091 RESERVED
|
||
; RESERVED0092 0x0092 RESERVED
|
||
; RESERVED0093 0x0093 RESERVED
|
||
; RESERVED0094 0x0094 RESERVED
|
||
; UCSR0C 0x0095 USART Control and Status Register C
|
||
; UCSR0C.UMSEL 6 USART Mode Select
|
||
; UCSR0C.UPM1 5 Parity Mode 1
|
||
; UCSR0C.UPM0 4 Parity Mode 0
|
||
; UCSR0C.USBS 3 Stop Bit Select
|
||
; UCSR0C.UCSZ1 2 Character Size 1
|
||
; UCSR0C.UCSZ0 1 Character Size 0
|
||
; UCSR0C.UCPOL 0 Clock Polarity
|
||
; RESERVED0096 0x0096 RESERVED
|
||
; RESERVED0097 0x0097 RESERVED
|
||
; UBRR1H 0x0098 USART Baud Rate Register High
|
||
; UBRR1H.UBRR11 11 USART Baud Rate Register bit 11
|
||
; UBRR1H.UBRR10 10 USART Baud Rate Register bit 10
|
||
; UBRR1H.UBRR9 9 USART Baud Rate Register bit 9
|
||
; UBRR1H.UBRR8 8 USART Baud Rate Register bit 8
|
||
; UBRR1L 0x0099 USART Baud Rate Register Low
|
||
; UBRR1L.UBRR7 7 USART Baud Rate Register bit 7
|
||
; UBRR1L.UBRR6 6 USART Baud Rate Register bit 6
|
||
; UBRR1L.UBRR5 5 USART Baud Rate Register bit 5
|
||
; UBRR1L.UBRR4 4 USART Baud Rate Register bit 4
|
||
; UBRR1L.UBRR3 3 USART Baud Rate Register bit 3
|
||
; UBRR1L.UBRR2 2 USART Baud Rate Register bit 2
|
||
; UBRR1L.UBRR1 1 USART Baud Rate Register bit 1
|
||
; UBRR1L.UBRR0 0 USART Baud Rate Register bit 0
|
||
; UCSR1B 0x009A USART Control and Status Register B
|
||
; UCSR1B.RXCIE 7 RX Complete Interrupt Enable
|
||
; UCSR1B.TXCIE 6 TX Complete Interrupt Enable
|
||
; UCSR1B.UDRIE 5 USART Data Register Empty Interrupt Enable
|
||
; UCSR1B.RXEN 4 Receiver Enable
|
||
; UCSR1B.TXEN 3 Transmitter Enable
|
||
; UCSR1B.UCSZ2 2 Character Size
|
||
; UCSR1B.RXB8 1 Receive Data Bit 8
|
||
; UCSR1B.TXB8 0 Transmit Data Bit 8
|
||
; UCSR1A 0x009B USART Control and Status Register A
|
||
; UCSR1A.RXC 7 USART Receive Complete
|
||
; UCSR1A.TXC 6 USART Transmit Complete
|
||
; UCSR1A.UDRE 5 USART Data Register Empty
|
||
; UCSR1A.FE 4 Frame Error
|
||
; UCSR1A.DOR 3 Data OverRun
|
||
; UCSR1A.UPE 2 USART Parity Error
|
||
; UCSR1A.U2X 1 Double the USART Transmission Speed
|
||
; UCSR1A.MPCM 0 Multi-processor Communication Mode
|
||
; UDR1 0x009C USART1 I/O Data Register
|
||
; UCSR1C 0x009D USART Control and Status Register C
|
||
; UCSR1C.UMSEL 6 USART Mode Select
|
||
; UCSR1C.UPM1 5 Parity Mode 1
|
||
; UCSR1C.UPM0 4 Parity Mode 0
|
||
; UCSR1C.USBS 3 Stop Bit Select
|
||
; UCSR1C.UCSZ1 2 Character Size 1
|
||
; UCSR1C.UCSZ0 1 Character Size 0
|
||
; UCSR1C.UCPOL 0 Clock Polarity
|
||
|
||
.ATmega644P
|
||
SUBARCH=5
|
||
|
||
RAM=4096
|
||
ROM=65536
|
||
EEPROM=2048
|
||
|
||
; MEMORY MAP
|
||
area DATA GPWR_ 0x0000:0x0020 32 General Purpose Working Registers
|
||
area DATA FSR1 0x0020:0x0060 64 I/O registers
|
||
area DATA FSR2 0x0060:0x0100 160 Ext I/O Reg.
|
||
area DATA I_SRAM 0x0100:0x1100 Internal SRAM
|
||
|
||
; Interrupt and reset vector assignments
|
||
entry __RESET 0x0000 External Pin, Power-on Reset, Brown-out Reset, Watchdog Reset, and JTAG AVR Reset
|
||
entry INT0_ 0x0002 External Interrupt Request 0
|
||
entry INT1_ 0x0004 External Interrupt Request 1
|
||
entry INT2_ 0x0006 External Interrupt Request 2
|
||
entry PCINT0 0x0008 Pin Change Interrupt Request 0
|
||
entry PCINT1 0x000A Pin Change Interrupt Request 1
|
||
entry PCINT2 0x000C Pin Change Interrupt Request 2
|
||
entry PCINT3 0x000E Pin Change Interrupt Request 3
|
||
entry WDT 0x0010 Watchdog Time-out Interrupt
|
||
entry TIMER2_COMPA 0x0012 Timer/Counter2 Comapare Match A
|
||
entry TIMER2_COMPB 0x0014 Timer/Counter2 Comapare Match B
|
||
entry TIMER2_OVF 0x0016 Timer/Counter2 Overflow
|
||
entry TIMER1_CAPT 0x0018 Timer/Counter1 Capture Event
|
||
entry TIMER1_COMPA 0x001A Timer/Counter1 Comapare Match A
|
||
entry TIMER1_COMPB 0x001C Timer/Counter1 Comapare Match B
|
||
entry TIMER1_OVF 0x001E Timer/Counter1 Overflow
|
||
entry TIMER0_COMPA 0x0020 Timer/Counter0 Comapare Match A
|
||
entry TIMER0_COMPB 0x0022 Timer/Counter0 Comapare Match B
|
||
entry TIMER0_OVF 0x0024 Timer/Counter0 Overflow
|
||
entry SPI_STC 0x0026 SPI Serial Transfer Complete
|
||
entry USART0_RX 0x0028 USART0 RX Complete
|
||
entry USART0_UDRE 0x002A USART0 Data register empty
|
||
entry USART0_TX 0x002C USART0 TX Complete
|
||
entry ANALOG_COMP 0x002E Analog Comparator
|
||
entry ADC_ 0x0030 ADC Conversion Complete
|
||
entry EEREADY 0x0032 EEPROM Ready
|
||
entry TWI_ 0x0034 2-wire Serial Interface
|
||
entry SPM_READY 0x0036 Store Program Memory Ready
|
||
entry USART1_RX 0x0038 USART1 RX Complete
|
||
entry USART1_UDRE 0x003A USART1 Data register empty
|
||
entry USART1_TX 0x003C USART1 TX Complete
|
||
|
||
|
||
; INPUT/OUTPUT PORTS
|
||
; CHECK ALL REGISTERS FROM REGISTERS SUMMARY
|
||
|
||
UDR1 0x00AE USART1 I/O Data Register
|
||
UBRR1H 0x00AD USART1 Baud Rate Register High Byte
|
||
UBRR1L 0x00AC USART1 Baud Rate Register Low Byte
|
||
|
||
UCSR1C 0x00AA
|
||
UCSR1C.UMSEL11 7
|
||
UCSR1C.UMSEL10 6
|
||
UCSR1C.UCORD1 2
|
||
UCSR1C.UCPHA1 1
|
||
UCSR1C.UCPOL1 0
|
||
|
||
UCSR1B 0x00A9
|
||
UCSR1B.RXCIE1 7
|
||
UCSR1B.TXCIE1 6
|
||
UCSR1B.UDRIE1 5
|
||
UCSR1B.RXEN1 4
|
||
UCSR1B.TXEN1 3
|
||
UCSR1B.UCSZ12 2
|
||
UCSR1B.RXB81 1
|
||
UCSR1B.TXB81 0
|
||
|
||
UCSR1A 0x00A8
|
||
UCSR1A.RXC1 7
|
||
UCSR1A.TXC1 6
|
||
UCSR1A.UDRE1 5
|
||
UCSR1A.FE1 4
|
||
UCSR1A.DOR1 3
|
||
UCSR1A.UPE1 2
|
||
UCSR1A.U2X1 1
|
||
UCSR1A.MPCM1 0
|
||
|
||
UDR0 0x00A6 USART0 I/O Data Register
|
||
UBRR0H 0x00A5 USART0 Baud Rate Register High Byte
|
||
UBRR0L 0x00A4 USART0 Baud Rate Register Low Byte
|
||
|
||
UCSR0C 0x00A2
|
||
UCSR0C.UMSEL01 7
|
||
UCSR0C.UMSEL00 6
|
||
UCSR0C.UDORD0 2
|
||
UCSR0C.UCPHA0 1
|
||
UCSR0C.UCPOL0 0
|
||
|
||
UCSR0B 0x00A1
|
||
UCSR0B.RXCIE0 7
|
||
UCSR0B.TXCIE0 6
|
||
UCSR0B.UDRIE0 5
|
||
UCSR0B.RXEN0 4
|
||
UCSR0B.TXEN0 3
|
||
UCSR0B.UCSZ02 2
|
||
UCSR0B.RXB80 1
|
||
UCSR0B.TXB80 0
|
||
|
||
UCSR0A 0x00A0
|
||
UCSR0A.RXC0 7
|
||
UCSR0A.TXC0 6
|
||
UCSR0A.UDRE0 5
|
||
UCSR0A.FE0 4
|
||
UCSR0A.DOR0 3
|
||
UCSR0A.UPE0 2
|
||
UCSR0A.U2X0 1
|
||
UCSR0A.MPCM0 0
|
||
|
||
TWAMR 0x009D TWI (Slave) Address Mask Register
|
||
TWAMR.TWAM6 7 TWAM: TWI Address Mask bit 6
|
||
TWAMR.TWAM5 6 TWAM: TWI Address Mask bit 5
|
||
TWAMR.TWAM4 5 TWAM: TWI Address Mask bit 4
|
||
TWAMR.TWAM3 4 TWAM: TWI Address Mask bit 3
|
||
TWAMR.TWAM2 3 TWAM: TWI Address Mask bit 2
|
||
TWAMR.TWAM1 2 TWAM: TWI Address Mask bit 1
|
||
TWAMR.TWAM0 1 TWAM: TWI Address Mask bit 0
|
||
|
||
TWCR 0x009C TWI Control Register
|
||
TWCR.TWINT 7 TWINT: TWI Interrupt Flag
|
||
TWCR.TWEA 6 TWEA: TWI Enable Acknowledge Bit
|
||
TWCR.TWSTA 5 TWSTA: TWI START Condition Bit
|
||
TWCR.TWSTO 4 TWSTO: TWI STOP Condition Bit
|
||
TWCR.TWWC 3 TWWC: TWI Write Collision Flag
|
||
TWCR.TWEN 2 TWEN: TWI Enable Bit
|
||
TWCR.TWIE 0 TWIE: TWI Interrupt Enable
|
||
|
||
TWDR 0x009B 2-wire Serial Interface Data Register
|
||
|
||
TWAR 0x009A TWI (Slave) Address Register
|
||
TWAR.TWA6 7 TWA: TWI (Slave) Address Register bit 6
|
||
TWAR.TWA5 6 TWA: TWI (Slave) Address Register bit 5
|
||
TWAR.TWA4 5 TWA: TWI (Slave) Address Register bit 4
|
||
TWAR.TWA3 4 TWA: TWI (Slave) Address Register bit 3
|
||
TWAR.TWA2 3 TWA: TWI (Slave) Address Register bit 2
|
||
TWAR.TWA1 2 TWA: TWI (Slave) Address Register bit 1
|
||
TWAR.TWA0 1 TWA: TWI (Slave) Address Register bit 0
|
||
TWAR.TWGCE 0 TWGCE: TWI General Call Recognition Enable Bit
|
||
|
||
TWSR 0x0099 TWI Status Register
|
||
TWSR.TWS7 7 TWS: TWI Status bit 4
|
||
TWSR.TWS6 6 TWS: TWI Status bit 3
|
||
TWSR.TWS5 5 TWS: TWI Status bit 2
|
||
TWSR.TWS4 4 TWS: TWI Status bit 1
|
||
TWSR.TWS3 3 TWS: TWI Status bit 0
|
||
TWSR.TWPS1 1 TWPS: TWI Prescaler bit 1
|
||
TWSR.TWPS0 0 TWPS: TWI Prescaler bit 0
|
||
|
||
TWBR 0x0098 2-wire Serial Interface Bit Rate Register
|
||
|
||
ASSR 0x0096 Asynchronous Status Register
|
||
ASSR.EXCLK 6 EXCLK: Enable External Clock Input
|
||
ASSR.AS2 5 AS2: Asynchronous Timer/Counter2
|
||
ASSR.TCN2UB 4 TCN2UB: Timer/Counter2 Update Busy
|
||
ASSR.OCR2AUB 3 OCR2AUB: Output Compare Register2 Update Busy
|
||
ASSR.OCR2BUB 2 OCR2BUB: Output Compare Register2 Update Busy
|
||
ASSR.TCR2AUB 1 TCR2AUB: Timer/Counter Control Register2 Update Busy
|
||
ASSR.TCR2BUB 0 TCR2BUB: Timer/Counter Control Register2 Update Busy
|
||
|
||
OCR2B 0x0094 Timer/Counter2 Output Compare Register B
|
||
|
||
OCR2A 0x0093 Timer/Counter2 Output Compare Register A
|
||
|
||
TCNT2 0x0092 Timer/Counter2 (8 Bit)
|
||
|
||
TCCR2B 0x0091 Timer/Counter Control Register B
|
||
TCCR2B.FOC2A 7 FOC2A: Force Output Compare A
|
||
TCCR2B.FOC2B 6 FOC2B: Force Output Compare B
|
||
TCCR2B.WGM22 3 WGM22: Waveform Generation Mode
|
||
TCCR2B.CS22 2 CS22 Clock Select
|
||
TCCR2B.CS21 1 CS21 Clock Select
|
||
TCCR2B.CS20 0 CS20 Clock Select
|
||
|
||
TCCR2A 0x0090 Timer/Counter Control Register A
|
||
TCCR2A.COM2A1 7 COM2A1 Compare Match Output A Mode
|
||
TCCR2A.COM2A0 6 COM2A0 Compare Match Output A Mode
|
||
TCCR2A.COM2B1 5 COM2B1 Compare Match Output B Mode
|
||
TCCR2A.COM2B0 4 COM2B0 Compare Match Output B Mode
|
||
TCCR2A.WGM21 1 WGM21 Waveform Generation Mode
|
||
TCCR2A.WGM20 0 WGM20 Waveform Generation Mode
|
||
|
||
OCR1BH 0x006B Timer/Counter1 - Output Compare Register B High Byte
|
||
OCR1BH.Timer_Counter1 7
|
||
OCR1BH.Output 5
|
||
OCR1BH.Compare 4
|
||
OCR1BH.Register 3
|
||
OCR1BH.B 2
|
||
OCR1BH.High 1
|
||
OCR1BH.Byte 0
|
||
|
||
OCR1BL 0x006A Timer/Counter1 - Output Compare Register B Low Byte
|
||
OCR1BL.Timer_Counter1 7
|
||
OCR1BL.Output 5
|
||
OCR1BL.Compare 4
|
||
OCR1BL.Register 3
|
||
OCR1BL.B 2
|
||
OCR1BL.Low 1
|
||
OCR1BL.Byte 0
|
||
|
||
OCR1AH 0x0069 Timer/Counter1 - Output Compare Register A High Byte
|
||
OCR1AH.Timer_Counter1 7
|
||
OCR1AH.Output 5
|
||
OCR1AH.Compare 4
|
||
OCR1AH.Register 3
|
||
OCR1AH.A 2
|
||
OCR1AH.High 1
|
||
OCR1AH.Byte 0
|
||
|
||
OCR1AL 0x0068 Timer/Counter1 - Output Compare Register A Low Byte
|
||
OCR1AL.Timer_Counter1 7
|
||
OCR1AL.Output 5
|
||
OCR1AL.Compare 4
|
||
OCR1AL.Register 3
|
||
OCR1AL.A 2
|
||
OCR1AL.Low 1
|
||
OCR1AL.Byte 0
|
||
|
||
ICR1H 0x0067 Timer/Counter1 - Input Capture Register High Byte
|
||
ICR1H.Timer_Counter1 7
|
||
ICR1H.Input 5
|
||
ICR1H.Capture 4
|
||
ICR1H.Register 3
|
||
ICR1H.High 2
|
||
ICR1H.Byte 1
|
||
ICR1H.136 0
|
||
|
||
ICR1L 0x0066 Timer/Counter1 - Input Capture Register Low Byte
|
||
ICR1L.Timer_Counter1 7
|
||
ICR1L.Input 5
|
||
ICR1L.Capture 4
|
||
ICR1L.Register 3
|
||
ICR1L.Low 2
|
||
ICR1L.Byte 1
|
||
ICR1L.136 0
|
||
|
||
TCNT1H 0x0065 Timer/Counter1 - Counter Register High Byte
|
||
|
||
TCNT1L 0x0064 Timer/Counter1 - Counter Register Low Byte
|
||
|
||
TCCR1C 0x0062 Timer/Counter1 Control Register C
|
||
TCCR1C.FOC1A 7 FOC1A: Force Output Compare for Channel A
|
||
TCCR1C.FOC1B 6 FOC1B: Force Output Compare for Channel B
|
||
|
||
TCCR1B 0x0061 Timer/Counter1 Control Register B
|
||
TCCR1B.ICNC1 7 ICNC1: Input Capture Noise Canceler
|
||
TCCR1B.ICES1 6 ICES1: Input Capture Edge Select
|
||
TCCR1B.WGM13 4 WGM13 Waveform Generation Mode
|
||
TCCR1B.WGM12 3 WGM12 Waveform Generation Mode
|
||
TCCR1B.CS12 2 CS12 Clock Select
|
||
TCCR1B.CS11 1 CS11 Clock Select
|
||
TCCR1B.CS10 0 CS10 Clock Select
|
||
|
||
TCCR1A 0x0060 Timer/Counter1 Control Register A
|
||
TCCR1A.COM1A1 7 COM1A1 Compare Output Mode for Channel A
|
||
TCCR1A.COM1A0 6 COM1A0 Compare Output Mode for Channel A
|
||
TCCR1A.COM1B1 5 COM1B1 Compare Output Mode for Channel B
|
||
TCCR1A.COM1B0 4 COM1B0 Compare Output Mode for Channel B
|
||
TCCR1A.WGM11 1 WGM11 Waveform Generation Mode
|
||
TCCR1A.WGM10 0 WGM10 Waveform Generation Mode
|
||
|
||
DIDR1 0x005F Digital Input Disable Register 1
|
||
DIDR1.AIN1D 1 AIN1D: AIN1 Digital Input Disable
|
||
DIDR1.AIN0D 0 AIN0D: AIN0 Digital Input Disable
|
||
|
||
DIDR0 0x005E Digital Input Disable Register 0
|
||
DIDR0.ADC7D 7 ADC7D: ADC7 Digital Input Disable
|
||
DIDR0.ADC6D 6 ADC6D: ADC6 Digital Input Disable
|
||
DIDR0.ADC5D 5 ADC5D: ADC5 Digital Input Disable
|
||
DIDR0.ADC4D 4 ADC4D: ADC4 Digital Input Disable
|
||
DIDR0.ADC3D 3 ADC3D: ADC3 Digital Input Disable
|
||
DIDR0.ADC2D 2 ADC2D: ADC2 Digital Input Disable
|
||
DIDR0.ADC1D 1 ADC1D: ADC1 Digital Input Disable
|
||
DIDR0.ADC0D 0 ADC0D: ADC0 Digital Input Disable
|
||
|
||
ADMUX 0x005C ADC Multiplexer Selection Register
|
||
ADMUX.REFS1 7 REFS1 Reference Selection Bits
|
||
ADMUX.REFS0 6 REFS0 Reference Selection Bits
|
||
ADMUX.ADLAR 5 ADLAR: ADC Left Adjust Result
|
||
ADMUX.MUX4 4 MUX4 Analog Channel and Gain Selection bit 4
|
||
ADMUX.MUX3 3 MUX3 Analog Channel and Gain Selection bit 3
|
||
ADMUX.MUX2 2 MUX2 Analog Channel and Gain Selection bit 2
|
||
ADMUX.MUX1 1 MUX1 Analog Channel and Gain Selection bit 1
|
||
ADMUX.MUX0 0 MUX0 Analog Channel and Gain Selection bit 0
|
||
|
||
ADCSRB 0x005B ADC Control and Status Register B
|
||
ADCSRB.ACME 6
|
||
ADCSRB.ADTS2 2
|
||
ADCSRB.ADTS1 1
|
||
ADCSRB.ADTS0 0
|
||
|
||
ADCSRA 0x005A ADC Control and Status Register A
|
||
ADCSRA.ADEN 7 ADEN: ADC Enable
|
||
ADCSRA.ADSC 6 ADSC: ADC Start Conversion
|
||
ADCSRA.ADATE 5 ADATE: ADC Auto Trigger Enable
|
||
ADCSRA.ADIF 4 ADIF: ADC Interrupt Flag
|
||
ADCSRA.ADIE 3 ADIE: ADC Interrupt Enable
|
||
ADCSRA.ADPS2 2 ADPS2 ADC Prescaler Select bit 2
|
||
ADCSRA.ADPS1 1 ADPS1 ADC Prescaler Select bit 1
|
||
ADCSRA.ADPS0 0 ADPS0 ADC Prescaler Select bit 0
|
||
|
||
ADCH 0x0059 ADC Data Register High byte
|
||
|
||
ADCL 0x0058 ADC Data Register Low byte
|
||
|
||
PCMSK3 0x0053 Pin Change Mask Register 3
|
||
PCMSK3.PCINT31 7 PCINT31 Pin Change Enable Mask
|
||
PCMSK3.PCINT30 6 PCINT30 Pin Change Enable Mask
|
||
PCMSK3.PCINT29 5 PCINT29 Pin Change Enable Mask
|
||
PCMSK3.PCINT28 4 PCINT28 Pin Change Enable Mask
|
||
PCMSK3.PCINT27 3 PCINT27 Pin Change Enable Mask
|
||
PCMSK3.PCINT26 2 PCINT26 Pin Change Enable Mask
|
||
PCMSK3.PCINT25 1 PCINT25 Pin Change Enable Mask
|
||
PCMSK3.PCINT24 0 PCINT24 Pin Change Enable Mask
|
||
|
||
TIMSK2 0x0050 Timer/Counter2 Interrupt Mask Register
|
||
TIMSK2.OCIE2B 2 OCIE2B: Timer/Counter2 Output Compare Match B Interrupt Enable
|
||
TIMSK2.OCIE2A 1 OCIE2A: Timer/Counter2 Output Compare Match A Interrupt Enable
|
||
TIMSK2.TOIE2 0 TOIE2: Timer/Counter2 Overflow Interrupt Enable
|
||
|
||
TIMSK1 0x004F Timer/Counter1 Interrupt Mask Register
|
||
TIMSK1.ICIE1 5 ICIE1: Timer/Counter1, Input Capture Interrupt Enable
|
||
TIMSK1.OCIE1B 2 OCIE1B: Timer/Counter1, Output Compare B Match Interrupt Enable
|
||
TIMSK1.OCIE1A 1 OCIE1A: Timer/Counter1, Output Compare A Match Interrupt Enable
|
||
TIMSK1.TOIE1 0 TOIE1: Timer/Counter1, Overflow Interrupt Enable
|
||
|
||
TIMSK0 0x004E Timer/Counter Interrupt Mask Register
|
||
TIMSK0.OCIE0B 2 OCIE0B: Timer/Counter Output Compare Match B Interrupt Enable
|
||
TIMSK0.OCIE0A 1 OCIE0A: Timer/Counter0 Output Compare Match A Interrupt Enable
|
||
TIMSK0.TOIE0 0 TOIE0: Timer/Counter0 Overflow Interrupt Enable
|
||
|
||
PCMSK2 0x004D Pin Change Mask Register 2
|
||
PCMSK2.PCINT23 7 PCINT23 Pin Change Enable Mask
|
||
PCMSK2.PCINT22 6 PCINT22 Pin Change Enable Mask
|
||
PCMSK2.PCINT21 5 PCINT21 Pin Change Enable Mask
|
||
PCMSK2.PCINT20 4 PCINT20 Pin Change Enable Mask
|
||
PCMSK2.PCINT19 3 PCINT19 Pin Change Enable Mask
|
||
PCMSK2.PCINT18 2 PCINT18 Pin Change Enable Mask
|
||
PCMSK2.PCINT17 1 PCINT17 Pin Change Enable Mask
|
||
PCMSK2.PCINT16 0 PCINT16 Pin Change Enable Mask
|
||
|
||
PCMSK1 0x004C Pin Change Mask Register 1
|
||
PCMSK1.PCINT15 7 PCINT15 Pin Change Enable Mask
|
||
PCMSK1.PCINT14 6 PCINT14 Pin Change Enable Mask
|
||
PCMSK1.PCINT13 5 PCINT13 Pin Change Enable Mask
|
||
PCMSK1.PCINT12 4 PCINT12 Pin Change Enable Mask
|
||
PCMSK1.PCINT11 3 PCINT11 Pin Change Enable Mask
|
||
PCMSK1.PCINT10 2 PCINT10 Pin Change Enable Mask
|
||
PCMSK1.PCINT9 1 PCINT9 Pin Change Enable Mask
|
||
PCMSK1.PCINT8 0 PCINT8 Pin Change Enable Mask
|
||
|
||
PCMSK0 0x004B Pin Change Mask Register 0
|
||
PCMSK0.PCINT7 7 PCINT7 Pin Change Enable Mask
|
||
PCMSK0.PCINT6 6 PCINT6 Pin Change Enable Mask
|
||
PCMSK0.PCINT5 5 PCINT5 Pin Change Enable Mask
|
||
PCMSK0.PCINT4 4 PCINT4 Pin Change Enable Mask
|
||
PCMSK0.PCINT3 3 PCINT3 Pin Change Enable Mask
|
||
PCMSK0.PCINT2 2 PCINT2 Pin Change Enable Mask
|
||
PCMSK0.PCINT1 1 PCINT1 Pin Change Enable Mask
|
||
PCMSK0.PCINT0 0 PCINT0 Pin Change Enable Mask
|
||
|
||
EICRA 0x0049 External Interrupt Control Register A
|
||
EICRA.ISC21 5 ISC21: External Interrupt Sense Control Bits
|
||
EICRA.ISC20 4 ISC20: External Interrupt Sense Control Bits
|
||
EICRA.ISC11 3 ISC11: External Interrupt Sense Control Bits
|
||
EICRA.ISC10 2 ISC10: External Interrupt Sense Control Bits
|
||
EICRA.ISC01 1 ISC01: External Interrupt Sense Control Bits
|
||
EICRA.ISC00 0 ISC00: External Interrupt Sense Control Bits
|
||
|
||
PCICR 0x0048 Pin Change Interrupt Control Register
|
||
PCICR.PCIE3 3 PCIE3: Pin Change Interrupt Enable 3
|
||
PCICR.PCIE2 2 PCIE2: Pin Change Interrupt Enable 2
|
||
PCICR.PCIE1 1 PCIE1: Pin Change Interrupt Enable 1
|
||
PCICR.PCIE0 0 PCIE0: Pin Change Interrupt Enable 0
|
||
|
||
OSCCAL 0x0046 Oscillator Calibration Register
|
||
|
||
PRR 0x0044 Power Reduction Register
|
||
PRR.PRTWI 7 PRTWI: Power Reduction TWI
|
||
PRR.PRTIM2 6 PRTIM2: Power Reduction Timer/Counter2
|
||
PRR.PRTIM0 5 PRTIM0: Power Reduction Timer/Counter0
|
||
PRR.PRUSART1 4 PRUSART1: Power Reduction USART1
|
||
PRR.PRTIM1 3 PRTIM1: Power Reduction Timer/Counter1
|
||
PRR.PRSPI 2 PRSPI: Power Reduction Serial Peripheral Interface
|
||
PRR.PRUSART0 1 PRUSART0: Power Reduction USART0
|
||
PRR.PRADC 0 PRADC: Power Reduction ADC
|
||
|
||
CLKPR 0x0041 Clock Prescale Register
|
||
CLKPR.CLKPCE 7 CLKPCE: Clock Prescaler Change Enable
|
||
CLKPR.CLKPS3 3 CLKPS3 Clock Prescaler Select bit 3
|
||
CLKPR.CLKPS2 2 CLKPS2 Clock Prescaler Select bit 2
|
||
CLKPR.CLKPS1 1 CLKPS1 Clock Prescaler Select bit 1
|
||
CLKPR.CLKPS0 0 CLKPS0 Clock Prescaler Select bit 0
|
||
|
||
WDTCSR 0x0040 Watchdog Timer Control Register
|
||
WDTCSR.WDIF 7 WDIF: Watchdog Interrupt Flag
|
||
WDTCSR.WDIE 6 WDIE: Watchdog Interrupt Enable
|
||
WDTCSR.WDP3 5 WDP3: Watchdog Timer Prescaler 3
|
||
WDTCSR.WDCE 4 WDCE: Watchdog Change Enable
|
||
WDTCSR.WDE 3 WDCE: Watchdog Change Enable
|
||
WDTCSR.WDP2 2 WDP2: Watchdog Timer Prescaler 3
|
||
WDTCSR.WDP1 1 WDP1: Watchdog Timer Prescaler 3
|
||
WDTCSR.WDP0 0 WDP0: Watchdog Timer Prescaler 3
|
||
|
||
SREG 0x003F Status Register
|
||
SREG.I 7 I: Global Interrupt Enable
|
||
SREG.T 6 T: Bit Copy Storage
|
||
SREG.H 5 H: Half Carry Flag
|
||
SREG.S 4 S: Sign Bit
|
||
SREG.V 3 V: Two’s Complement Overflow Flag
|
||
SREG.N 2 N: Negative Flag
|
||
SREG.Z 1 Z: Zero Flag
|
||
SREG.C 0 C: Carry Flag
|
||
|
||
SPH 0x003E Stack Pointer High
|
||
SPH.SP12 12
|
||
SPH.SP11 11
|
||
SPH.SP10 10
|
||
SPH.SP9 9
|
||
SPH.SP8 8
|
||
|
||
SPL 0x003D Stack pointer Low
|
||
SPL.SP7 7
|
||
SPL.SP6 6
|
||
SPL.SP5 5
|
||
SPL.SP4 4
|
||
SPL.SP3 3
|
||
SPL.SP2 2
|
||
SPL.SP1 1
|
||
SPL.SP0 0
|
||
|
||
SPMCSR 0x0037 Store Program Memory Control and Status Register
|
||
SPMCSR.SPMIE 7 SPMIE: SPM Interrupt Enable
|
||
SPMCSR.RWWSB 6 RWWSB: Read-While-Write Section Busy
|
||
SPMCSR.SIGRD 5 SIGRD: Signature Row Read
|
||
SPMCSR.RWWSRE 4 RWWSRE: Read-While-Write Section Read Enable
|
||
SPMCSR.BLBSET 3 BLBSET: Boot Lock Bit Set
|
||
SPMCSR.PGWRT 2 PGWRT: Page Write
|
||
SPMCSR.PGERS 1 PGERS: Page Erase
|
||
SPMCSR.SPMEN 0 SPMEN: Store Program Memory Enable
|
||
|
||
MCUCR 0x0035 MCU Control Register
|
||
MCUCR.JTD 7
|
||
MCUCR.BODS 6 BODS: BOD Sleep
|
||
MCUCR.BODSE 5 BODSE: BOD Sleep Enable
|
||
MCUCR.PUD 4
|
||
MCUCR.IVSEL 1
|
||
MCUCR.IVCE 0
|
||
|
||
MCUSR 0x0034 MCU Status Register
|
||
MCUSR.JTRF 4 JTRF: JTAG Reset Flag
|
||
MCUSR.WDRF 3 WDRF: Watchdog Reset Flag
|
||
MCUSR.BORF 2 BORF: Brown-out Reset Flag
|
||
MCUSR.EXTRF 1 EXTRF: External Reset Flag
|
||
MCUSR.PORF 0 PORF: Power-on Reset Flag
|
||
|
||
SMCR 0x0033 Sleep Mode Control Register
|
||
SMCR.SM2 3 SM2 Sleep Mode Select bit 2
|
||
SMCR.SM1 2 SM1 Sleep Mode Select bit 1
|
||
SMCR.SM0 1 SM0 Sleep Mode Select bit 0
|
||
SMCR.SE 0 SE: Sleep Enable
|
||
|
||
OCDR 0x0031 On-Chip Debug Register
|
||
|
||
ACSR 0x0030 Analog Comparator Control and Status Register
|
||
ACSR.ACD 7 ACD: Analog Comparator Disable
|
||
ACSR.ACBG 6 ACBG: Analog Comparator Bandgap Select
|
||
ACSR.ACO 5 ACO: Analog Comparator Output
|
||
ACSR.ACI 4 ACI: Analog Comparator Interrupt Flag
|
||
ACSR.ACIE 3 ACIE: Analog Comparator Interrupt Enable
|
||
ACSR.ACIC 2 ACIC: Analog Comparator Input Capture Enable
|
||
ACSR.ACIS1 1 ACIS1: Analog Comparator Interrupt Mode Select
|
||
ACSR.ACIS0 0 ACIS0: Analog Comparator Interrupt Mode Select
|
||
|
||
SPDR 0x002E SPI Data Register
|
||
|
||
SPSR 0x002D SPI Status Register
|
||
SPSR.SPIF 7 SPIF: SPI Interrupt Flag
|
||
SPSR.WCOL 6 WCOL: Write COLlision Flag
|
||
SPSR.SPI2X 0 SPI2X: Double SPI Speed Bit
|
||
|
||
SPCR 0x002C SPI Control Register
|
||
SPCR.SPIE 7 SPIE: SPI Interrupt Enable
|
||
SPCR.SPE 6 SPE: SPI Enable
|
||
SPCR.DORD 5 DORD: Data Order
|
||
SPCR.MSTR 4 MSTR: Master/Slave Select
|
||
SPCR.CPOL 3 CPOL: Clock Polarity
|
||
SPCR.CPHA 2 CPHA: Clock Phase
|
||
SPCR.SPR1 1 SPR1: SPI Clock Rate Select 1
|
||
SPCR.SPR0 0 SPR0: SPI Clock Rate Select 0
|
||
|
||
GPIOR2 0x002B General Purpose I/O Register 2
|
||
|
||
GPIOR1 0x002A General Purpose I/O Register 1
|
||
|
||
OCR0B 0x0028 Timer/Counter0 Output Compare Register B
|
||
|
||
OCR0A 0x0027 Timer/Counter0 Output Compare Register A
|
||
|
||
TCNT0 0x0026 Timer/Counter0 (8 Bit)
|
||
|
||
TCCR0B 0x0025 Timer/Counter Control Register B
|
||
TCCR0B.FOC0A 7 FOC0A: Force Output Compare A
|
||
TCCR0B.FOC0B 6 FOC0B: Force Output Compare B
|
||
TCCR0B.WGM02 3 WGM02: Waveform Generation Mode
|
||
TCCR0B.CS02 2 CS02: Clock Select
|
||
TCCR0B.CS01 1 CS01: Clock Select
|
||
TCCR0B.CS00 0 CS00: Clock Select
|
||
|
||
TCCR0A 0x0024 Timer/Counter Control Register A
|
||
TCCR0A.COM0A1 7 COM0A1: Compare Match Output A Mode
|
||
TCCR0A.COM0A0 6 COM0A0: Compare Match Output A Mode
|
||
TCCR0A.COM0B1 5 COM0B1: Compare Match Output B Mode
|
||
TCCR0A.COM0B0 4 COM0B0: Compare Match Output B Mode
|
||
TCCR0A.WGM01 1 WGM01: Waveform Generation Mode
|
||
TCCR0A.WGM00 0 WGM00: Waveform Generation Mode
|
||
|
||
GTCCR 0x0023 General Timer/Counter Control Register
|
||
GTCCR.TSM 7 TSM: Timer/Counter Synchronization mode
|
||
GTCCR.PSRASY 1 PSRASY: Prescaler Reset Timer/Counter2
|
||
GTCCR.PSRSYNC 0 PSRSYNC: Prescaler Reset
|
||
|
||
EEARH 0x0022 EEPROM Address Register High Byte
|
||
EEARL 0x0021 EEPROM Address Register Low Byte
|
||
EEDR 0x0020 EEPROM Data Register
|
||
|
||
EECR 0x001F The EEPROM Control Register
|
||
EECR.EEPM1 5 EEPM1: EEPROM Programming Mode Bits
|
||
EECR.EEPM0 4 EEPM0: EEPROM Programming Mode Bits
|
||
EECR.EERIE 3 EERIE: EEPROM Ready Interrupt Enable
|
||
EECR.EEMPE 2 EEMPE: EEPROM Master Programming Enable
|
||
EECR.EEPE 1 EEPE: EEPROM Programming Enable
|
||
EECR.EERE 0 EERE: EEPROM Read Enable
|
||
|
||
GPIOR0 0x001E General Purpose I/O Register 0
|
||
|
||
EIMSK 0x001D External Interrupt Mask Register
|
||
EIMSK.INT2 2 INT2 External Interrupt Request 2
|
||
EIMSK.INT1 1 INT1 External Interrupt Request 1
|
||
EIMSK.INT0 0 INT0 External Interrupt Request 0
|
||
|
||
EIFR 0x001C External Interrupt Flag Register
|
||
EIFR.INTF2 2 INTF2 External Interrupt Flags 2
|
||
EIFR.INTF1 1 INTF1 External Interrupt Flags 1
|
||
EIFR.INTF0 0 INTF0 External Interrupt Flags 0
|
||
|
||
PCIFR 0x001B Pin Change Interrupt Flag Register
|
||
PCIFR.PCIF3 3 PCIF3: Pin Change Interrupt Flag 3
|
||
PCIFR.PCIF2 2 PCIF2: Pin Change Interrupt Flag 2
|
||
PCIFR.PCIF1 1 PCIF1: Pin Change Interrupt Flag 1
|
||
PCIFR.PCIF0 0 PCIF0: Pin Change Interrupt Flag 0
|
||
|
||
TIFR2 0x0017 Timer/Counter2 Interrupt Flag Register
|
||
TIFR2.OCF2B 2 OCF2B: Output Compare Flag 2 B
|
||
TIFR2.OCF2A 1 OCF2A: Output Compare Flag 2 A
|
||
TIFR2.TOV2 0 TOV2: Timer/Counter2 Overflow Flag
|
||
|
||
TIFR1 0x0016 Timer/Counter1 Interrupt Flag Register
|
||
TIFR1.ICF1 5 ICF1: Timer/Counter1, Input Capture Flag
|
||
TIFR1.OCF1B 2 OCF1B: Timer/Counter1, Output Compare B Match Flag
|
||
TIFR1.OCF1A 1 OCF1A: Timer/Counter1, Output Compare A Match Flag
|
||
TIFR1.TOV1 0 TOV1: Timer/Counter1, Overflow Flag
|
||
|
||
TIFR0 0x0015 Timer/Counter 0 Interrupt Flag Register
|
||
TIFR0.OCF0B 2 OCF0B: Timer/Counter 0 Output Compare B Match Flag
|
||
TIFR0.OCF0A 1 OCF0A: Timer/Counter 0 Output Compare A Match Flag
|
||
TIFR0.TOV0 0 TOV0: Timer/Counter0 Overflow Flag
|
||
|
||
PORTD 0x000B Port D Data Register
|
||
PORTD.PORTD7 7 PORT D7
|
||
PORTD.PORTD6 6 PORT D6
|
||
PORTD.PORTD5 5 PORT D5
|
||
PORTD.PORTD4 4 PORT D4
|
||
PORTD.PORTD3 3 PORT D3
|
||
PORTD.PORTD2 2 PORT D2
|
||
PORTD.PORTD1 1 PORT D1
|
||
PORTD.PORTD0 0 PORT D0
|
||
|
||
DDRD 0x000A Port D Data Direction Register
|
||
DDRD.DDD7 7
|
||
DDRD.DDD6 6
|
||
DDRD.DDD5 5
|
||
DDRD.DDD4 4
|
||
DDRD.DDD3 3
|
||
DDRD.DDD2 2
|
||
DDRD.DDD1 1
|
||
DDRD.DDD0 0
|
||
|
||
PIND 0x0009 Port D Input Pins Address
|
||
PIND.PIND7 7
|
||
PIND.PIND6 6
|
||
PIND.PIND5 5
|
||
PIND.PIND4 4
|
||
PIND.PIND3 3
|
||
PIND.PIND2 2
|
||
PIND.PIND1 1
|
||
PIND.PIND0 0
|
||
|
||
PORTC 0x0008 Port C Data Register
|
||
PORTC.PORTC7 7
|
||
PORTC.PORTC6 6
|
||
PORTC.PORTC5 5
|
||
PORTC.PORTC4 4
|
||
PORTC.PORTC3 3
|
||
PORTC.PORTC2 2
|
||
PORTC.PORTC1 1
|
||
PORTC.PORTC0 0
|
||
|
||
DDRC 0x0007 Port C Data Direction Register
|
||
DDRC.DDC7 7
|
||
DDRC.DDC6 6
|
||
DDRC.DDC5 5
|
||
DDRC.DDC4 4
|
||
DDRC.DDC3 3
|
||
DDRC.DDC2 2
|
||
DDRC.DDC1 1
|
||
DDRC.DDC0 0
|
||
|
||
PINC 0x0006 Port C Input Pins Address
|
||
PINC.PINC6 7
|
||
PINC.PINC6 6
|
||
PINC.PINC5 5
|
||
PINC.PINC4 4
|
||
PINC.PINC3 3
|
||
PINC.PINC2 2
|
||
PINC.PINC1 1
|
||
PINC.PINC0 0
|
||
|
||
PORTB 0x0005 Port B Data Register
|
||
PORTB.PORTB7 7
|
||
PORTB.PORTB6 6
|
||
PORTB.PORTB5 5
|
||
PORTB.PORTB4 4
|
||
PORTB.PORTB3 3
|
||
PORTB.PORTB2 2
|
||
PORTB.PORTB1 1
|
||
PORTB.PORTB0 0
|
||
|
||
DDRB 0x0004 Port B Data Direction Register
|
||
DDRB.DDB7 7
|
||
DDRB.DDB6 6
|
||
DDRB.DDB5 5
|
||
DDRB.DDB4 4
|
||
DDRB.DDB3 3
|
||
DDRB.DDB2 2
|
||
DDRB.DDB1 1
|
||
DDRB.DDB0 0
|
||
|
||
PINB 0x0003 Port B Input Pins Address
|
||
PINB.PINB7 7
|
||
PINB.PINB6 6
|
||
PINB.PINB5 5
|
||
PINB.PINB4 4
|
||
PINB.PINB3 3
|
||
PINB.PINB2 2
|
||
PINB.PINB1 1
|
||
PINB.PINB0 0
|
||
|
||
PORTA 0x0002 Port A Data Register
|
||
PORTA.PORTA7 7 Port A Data Register bit 7
|
||
PORTA.PORTA6 6 Port A Data Register bit 6
|
||
PORTA.PORTA5 5 Port A Data Register bit 5
|
||
PORTA.PORTA4 4 Port A Data Register bit 4
|
||
PORTA.PORTA3 3 Port A Data Register bit 3
|
||
PORTA.PORTA2 2 Port A Data Register bit 2
|
||
PORTA.PORTA1 1 Port A Data Register bit 1
|
||
PORTA.PORTA0 0 Port A Data Register bit 0
|
||
|
||
DDRA 0x0001 Port A Data Direction Register
|
||
DDRA.DDA7 7 Port A Data Direction Register bit 7
|
||
DDRA.DDA6 6 Port A Data Direction Register bit 6
|
||
DDRA.DDA5 5 Port A Data Direction Register bit 5
|
||
DDRA.DDA4 4 Port A Data Direction Register bit 4
|
||
DDRA.DDA3 3 Port A Data Direction Register bit 3
|
||
DDRA.DDA2 2 Port A Data Direction Register bit 2
|
||
DDRA.DDA1 1 Port A Data Direction Register bit 1
|
||
DDRA.DDA0 0 Port A Data Direction Register bit 0
|
||
|
||
PINA 0x0000 Port A Input Pins Address
|
||
PINA.PINA7 7
|
||
PINA.PINA6 6
|
||
PINA.PINA5 5
|
||
PINA.PINA4 4
|
||
PINA.PINA3 3
|
||
PINA.PINA2 2
|
||
PINA.PINA1 1
|
||
PINA.PINA0 0
|
||
|
||
.ATmega8515_L
|
||
SUBARCH=2
|
||
; doc2512.pdf
|
||
;
|
||
|
||
RAM=512
|
||
ROM=8192
|
||
EEPROM=512
|
||
|
||
; MEMORY MAP
|
||
area DATA FSR_ 0x0000:0x0060
|
||
area DATA I_SRAM 0x0060:0x0260 Internal SRAM
|
||
area DATA E_SRAM 0x0260:0x10000 External SRAM
|
||
|
||
|
||
; Interrupt and reset vector assignments
|
||
entry __RESET 0x0000 External Pin, Power-on Reset,Brown-out Reset and Watchdog Reset
|
||
entry INT0_ 0x0001 External Interrupt Request 0
|
||
entry INT1_ 0x0002 External Interrupt Request 1
|
||
entry TIMER1_CAPT 0x0003 Timer/Counter1 Capture Event
|
||
entry TIMER1_COMPA 0x0004 Timer/Counter1 Compare Match A
|
||
entry TIMER1_COMPB 0x0005 Timer/Counter1 Compare Match B
|
||
entry TIMER1_OVF 0x0006 Timer/Counter1 Overflow
|
||
entry TIMER0_OVF 0x0007 Timer/Counter0 Overflow
|
||
entry SPI_STC 0x0008 Serial Transfer Complete
|
||
entry USART_RXC 0x0009 USART, Rx Complete
|
||
entry USART_UDRE 0x000A USART Data Register Empty
|
||
entry USART_TXC 0x000B USART, Tx Complete
|
||
entry ANA_COMP 0x000C Analog Comparator
|
||
entry INT2_ 0x000D External Interrupt Request 2
|
||
entry TIMER0_COMP 0x000E Timer/Counter0 Compare Match
|
||
entry EE_RDY 0x000F EEPROM Ready
|
||
entry SPM_RDY 0x0010 Store Program Memory Ready
|
||
|
||
|
||
; INPUT/OUTPUT PORTS
|
||
OSCCAL 0x0004 Oscillator Calibration Register
|
||
OSCCAL.CAL7 7 Oscillator Calibration Value 7
|
||
OSCCAL.CAL6 6 Oscillator Calibration Value 6
|
||
OSCCAL.CAL5 5 Oscillator Calibration Value 5
|
||
OSCCAL.CAL4 4 Oscillator Calibration Value 4
|
||
OSCCAL.CAL3 3 Oscillator Calibration Value 3
|
||
OSCCAL.CAL2 2 Oscillator Calibration Value 2
|
||
OSCCAL.CAL1 1 Oscillator Calibration Value 1
|
||
OSCCAL.CAL0 0 Oscillator Calibration Value 0
|
||
PINE 0x0005 Port E Input Pins Address
|
||
PINE.PINE2 2
|
||
PINE.PINE1 1
|
||
PINE.PINE0 0
|
||
DDRE 0x0006 Port E Data Direction Register
|
||
DDRE.DDE2 2 Port E Data Direction Register bit 2
|
||
DDRE.DDE1 1 Port E Data Direction Register bit 1
|
||
DDRE.DDE0 0 Port E Data Direction Register bit 0
|
||
PORTE 0x0007 Port E Data Register
|
||
PORTE.PORTE2 2 Port E Data Register bit 2
|
||
PORTE.PORTE1 1 Port E Data Register bit 1
|
||
PORTE.PORTE0 0 Port E Data Register bit 0
|
||
ACSR 0x0008 Analog Comparator Control and Status Register
|
||
ACSR.ACD 7 Analog Comparator Disable
|
||
ACSR.ACBG 6 Analog Comparator Bandgap Select
|
||
ACSR.ACO 5 Analog Comparator Output
|
||
ACSR.ACI 4 Analog Comparator Interrupt Flag
|
||
ACSR.ACIE 3 Analog Comparator Interrupt Enable
|
||
ACSR.ACIC 2 Analog Comparator Input Capture Enable
|
||
ACSR.ACIS1 1 Analog Comparator Interrupt Mode Select 1
|
||
ACSR.ACIS0 0 Analog Comparator Interrupt Mode Select 0
|
||
UBRRL 0x0009 USART Baud Rate Register Low
|
||
UBRRL.UBRR7 7 USART Baud Rate Register bit 7
|
||
UBRRL.UBRR6 6 USART Baud Rate Register bit 6
|
||
UBRRL.UBRR5 5 USART Baud Rate Register bit 5
|
||
UBRRL.UBRR4 4 USART Baud Rate Register bit 4
|
||
UBRRL.UBRR3 3 USART Baud Rate Register bit 3
|
||
UBRRL.UBRR2 2 USART Baud Rate Register bit 2
|
||
UBRRL.UBRR1 1 USART Baud Rate Register bit 1
|
||
UBRRL.UBRR0 0 USART Baud Rate Register bit 0
|
||
UCSRB 0x000A USART Control and Status Register B
|
||
UCSRB.RXCIE 7 RX Complete Interrupt Enable
|
||
UCSRB.TXCIE 6 TX Complete Interrupt Enable
|
||
UCSRB.UDRIE 5 USART Data Register Empty Interrupt Enable
|
||
UCSRB.RXEN 4 Receiver Enable
|
||
UCSRB.TXEN 3 Transmitter Enable
|
||
UCSRB.UCSZ2 2 Character Size
|
||
UCSRB.RXB8 1 Receive Data Bit 8
|
||
UCSRB.TXB8 0 Transmit Data Bit8
|
||
UCSRA 0x000B USART Control and Status Register A
|
||
UCSRA.RXC 7 USART Receive Complete
|
||
UCSRA.TXC 6 USART Transmit Complete
|
||
UCSRA.UDRE 5 USART Data Register Empty
|
||
UCSRA.FE 4 Frame Error
|
||
UCSRA.DOR 3 Data OverRun
|
||
UCSRA.PE 2 ParityError
|
||
UCSRA.U2X 1 Double the USART Transmission Speed
|
||
UCSRA.MPCM 0 Multi-processor Communication Mode
|
||
UDR 0x000C USART I/O Data Register
|
||
SPCR 0x000D SPI Control Register
|
||
SPCR.SPIE 7 SPI Interrupt Enable
|
||
SPCR.SPE 6 SPI Enable
|
||
SPCR.DORD 5 Data Order
|
||
SPCR.MSTR 4 Master/Slave Select
|
||
SPCR.CPOL 3 Clock Polarity
|
||
SPCR.CPHA 2 Clock Phase
|
||
SPCR.SPR1 1 SPI Clock Rate Select 1
|
||
SPCR.SPR0 0 SPI Clock Rate Select 0
|
||
SPSR 0x000E SPI Status Register
|
||
SPSR.SPIF 7 SPI Interrupt Flag
|
||
SPSR.WCOL 6 Write COLlision Flag
|
||
SPSR.SPI2X 0 Double SPI Speed Bit
|
||
SPDR 0x000F SPI Data Register
|
||
PIND 0x0010 Port D Input Pins Address
|
||
PIND.PIND7 7
|
||
PIND.PIND6 6
|
||
PIND.PIND5 5
|
||
PIND.PIND4 4
|
||
PIND.PIND3 3
|
||
PIND.PIND2 2
|
||
PIND.PIND1 1
|
||
PIND.PIND0 0
|
||
DDRD 0x0011 Port D Data Direction Register
|
||
DDRD.DDD7 7 Port D Data Direction Register bit 7
|
||
DDRD.DDD6 6 Port D Data Direction Register bit 6
|
||
DDRD.DDD5 5 Port D Data Direction Register bit 5
|
||
DDRD.DDD4 4 Port D Data Direction Register bit 4
|
||
DDRD.DDD3 3 Port D Data Direction Register bit 3
|
||
DDRD.DDD2 2 Port D Data Direction Register bit 2
|
||
DDRD.DDD1 1 Port D Data Direction Register bit 1
|
||
DDRD.DDD0 0 Port D Data Direction Register bit 0
|
||
PORTD 0x0012 Port D Data Register
|
||
PORTD.PORTD7 7 Port D Data Register bit 7
|
||
PORTD.PORTD6 6 Port D Data Register bit 6
|
||
PORTD.PORTD5 5 Port D Data Register bit 5
|
||
PORTD.PORTD4 4 Port D Data Register bit 4
|
||
PORTD.PORTD3 3 Port D Data Register bit 3
|
||
PORTD.PORTD2 2 Port D Data Register bit 2
|
||
PORTD.PORTD1 1 Port D Data Register bit 1
|
||
PORTD.PORTD0 0 Port D Data Register bit 0
|
||
PINC 0x0013 Port C Input Pins Address
|
||
PINC.PINC7 7
|
||
PINC.PINC6 6
|
||
PINC.PINC5 5
|
||
PINC.PINC4 4
|
||
PINC.PINC3 3
|
||
PINC.PINC2 2
|
||
PINC.PINC1 1
|
||
PINC.PINC0 0
|
||
DDRC 0x0014 Port C Data Direction Register
|
||
DDRC.DDC7 7 Port C Data Direction Register bit 7
|
||
DDRC.DDC6 6 Port C Data Direction Register bit 6
|
||
DDRC.DDC5 5 Port C Data Direction Register bit 5
|
||
DDRC.DDC4 4 Port C Data Direction Register bit 4
|
||
DDRC.DDC3 3 Port C Data Direction Register bit 3
|
||
DDRC.DDC2 2 Port C Data Direction Register bit 2
|
||
DDRC.DDC1 1 Port C Data Direction Register bit 1
|
||
DDRC.DDC0 0 Port C Data Direction Register bit 0
|
||
PORTC 0x0015 Port C Data Register
|
||
PORTC.PORTC7 7 Port C Data Register bit 7
|
||
PORTC.PORTC6 6 Port C Data Register bit 6
|
||
PORTC.PORTC5 5 Port C Data Register bit 5
|
||
PORTC.PORTC4 4 Port C Data Register bit 4
|
||
PORTC.PORTC3 3 Port C Data Register bit 3
|
||
PORTC.PORTC2 2 Port C Data Register bit 2
|
||
PORTC.PORTC1 1 Port C Data Register bit 1
|
||
PORTC.PORTC0 0 Port C Data Register bit 0
|
||
PINB 0x0016 Port B Input Pins Address
|
||
PINB.PINB7 7
|
||
PINB.PINB6 6
|
||
PINB.PINB5 5
|
||
PINB.PINB4 4
|
||
PINB.PINB3 3
|
||
PINB.PINB2 2
|
||
PINB.PINB1 1
|
||
PINB.PINB0 0
|
||
DDRB 0x0017 Port B Data Direction Register
|
||
DDRB.DDB7 7 Port B Data Direction Register bit 7
|
||
DDRB.DDB6 6 Port B Data Direction Register bit 6
|
||
DDRB.DDB5 5 Port B Data Direction Register bit 5
|
||
DDRB.DDB4 4 Port B Data Direction Register bit 4
|
||
DDRB.DDB3 3 Port B Data Direction Register bit 3
|
||
DDRB.DDB2 2 Port B Data Direction Register bit 2
|
||
DDRB.DDB1 1 Port B Data Direction Register bit 1
|
||
DDRB.DDB0 0 Port B Data Direction Register bit 0
|
||
PORTB 0x0018 Port B Data Register
|
||
PORTB.PORTB7 7 Port B Data Register bit 7
|
||
PORTB.PORTB6 6 Port B Data Register bit 6
|
||
PORTB.PORTB5 5 Port B Data Register bit 5
|
||
PORTB.PORTB4 4 Port B Data Register bit 4
|
||
PORTB.PORTB3 3 Port B Data Register bit 3
|
||
PORTB.PORTB2 2 Port B Data Register bit 2
|
||
PORTB.PORTB1 1 Port B Data Register bit 1
|
||
PORTB.PORTB0 0 Port B Data Register bit 0
|
||
PINA 0x0019 Port A Input Pins Address
|
||
PINA.PINA7 7
|
||
PINA.PINA6 6
|
||
PINA.PINA5 5
|
||
PINA.PINA4 4
|
||
PINA.PINA3 3
|
||
PINA.PINA2 2
|
||
PINA.PINA1 1
|
||
PINA.PINA0 0
|
||
DDRA 0x001A Port A Data Direction Register
|
||
DDRA.DDA7 7 Port A Data Direction Register bit 7
|
||
DDRA.DDA6 6 Port A Data Direction Register bit 6
|
||
DDRA.DDA5 5 Port A Data Direction Register bit 5
|
||
DDRA.DDA4 4 Port A Data Direction Register bit 4
|
||
DDRA.DDA3 3 Port A Data Direction Register bit 3
|
||
DDRA.DDA2 2 Port A Data Direction Register bit 2
|
||
DDRA.DDA1 1 Port A Data Direction Register bit 1
|
||
DDRA.DDA0 0 Port A Data Direction Register bit 0
|
||
PORTA 0x001B Port A Data Register
|
||
PORTA.PORTA7 7 Port A Data Register bit 7
|
||
PORTA.PORTA6 6 Port A Data Register bit 6
|
||
PORTA.PORTA5 5 Port A Data Register bit 5
|
||
PORTA.PORTA4 4 Port A Data Register bit 4
|
||
PORTA.PORTA3 3 Port A Data Register bit 3
|
||
PORTA.PORTA2 2 Port A Data Register bit 2
|
||
PORTA.PORTA1 1 Port A Data Register bit 1
|
||
PORTA.PORTA0 0 Port A Data Register bit 0
|
||
EECR 0x001C EEPROM Control Register
|
||
EECR.EERIE 3 EEPROM Ready Interrupt Enable
|
||
EECR.EEMWE 2 EEPROM Master Write Enable
|
||
EECR.EEWE 1 EEPROM Write Enable
|
||
EECR.EERE 0 EEPROM Read Enable
|
||
EEDR 0x001D EEPROM Data Register
|
||
EEDR.EEDR7 7 EEPROM Data 7
|
||
EEDR.EEDR6 6 EEPROM Data 6
|
||
EEDR.EEDR5 5 EEPROM Data 5
|
||
EEDR.EEDR4 4 EEPROM Data 4
|
||
EEDR.EEDR3 3 EEPROM Data 3
|
||
EEDR.EEDR2 2 EEPROM Data 2
|
||
EEDR.EEDR1 1 EEPROM Data 1
|
||
EEDR.EEDR0 0 EEPROM Data 0
|
||
EEARL 0x001E EEPROM Address Register Low
|
||
EEARL.EEAR7 7 EEPROM Addres 7
|
||
EEARL.EEAR6 6 EEPROM Addres 6
|
||
EEARL.EEAR5 5 EEPROM Addres 5
|
||
EEARL.EEAR4 4 EEPROM Addres 4
|
||
EEARL.EEAR3 3 EEPROM Addres 3
|
||
EEARL.EEAR2 2 EEPROM Addres 2
|
||
EEARL.EEAR1 1 EEPROM Addres 1
|
||
EEARL.EEAR0 0 EEPROM Addres 0
|
||
EEARH 0x001F EEPROM Address Register High
|
||
EEARH.EEAR9 9 EEPROM Addres 9
|
||
UCSRC 0x0020 USART Control and Status Register C
|
||
UCSRC.URSEL 7 Register Select
|
||
UCSRC.UMSEL 6 USART Mode Select
|
||
UCSRC.UPM1 5 Parity Mode 1
|
||
UCSRC.UPM0 4 Parity Mode 0
|
||
UCSRC.USBS 3 Stop Bit Select
|
||
UCSRC.UCSZ1 2 Character Size 1
|
||
UCSRC.UCSZ0 1 Character Size 0
|
||
UCSRC.UCPOL 0 Clock Polarity
|
||
; UBRRH 0x0020 USART Baud Rate Register High
|
||
; UBRRH.URSEL 15 Register Select
|
||
; UBRRH.UBRR11 11 USART Baud Rate Register bit 11
|
||
; UBRRH.UBRR10 10 USART Baud Rate Register bit 10
|
||
; UBRRH.UBRR9 9 USART Baud Rate Register bit 9
|
||
; UBRRH.UBRR8 8 USART Baud Rate Register bit 8
|
||
WDTCR 0x0021 Watchdog Timer Control Register
|
||
WDTCR.WDCE 4 Watchdog Change Enable
|
||
WDTCR.WDE 3 Watchdog Enable
|
||
WDTCR.WDP2 2 Watchdog Timer Prescaler 2
|
||
WDTCR.WDP1 1 Watchdog Timer Prescaler 1
|
||
WDTCR.WDP0 0 Watchdog Timer Prescaler 0
|
||
RESERVED0022 0x0022 RESERVED
|
||
RESERVED0023 0x0023 RESERVED
|
||
ICR1L 0x0024 Input Capture Register 1 Low
|
||
ICR1L.ICR1_7 7
|
||
ICR1L.ICR1_6 6
|
||
ICR1L.ICR1_5 5
|
||
ICR1L.ICR1_4 4
|
||
ICR1L.ICR1_3 3
|
||
ICR1L.ICR1_2 2
|
||
ICR1L.ICR1_1 1
|
||
ICR1L.ICR1_0 0
|
||
ICR1H 0x0025 Input Capture Register 1 High
|
||
ICR1H.ICR1_15 15
|
||
ICR1H.ICR1_14 14
|
||
ICR1H.ICR1_13 13
|
||
ICR1H.ICR1_12 12
|
||
ICR1H.ICR1_11 11
|
||
ICR1H.ICR1_10 10
|
||
ICR1H.ICR1_9 9
|
||
ICR1H.ICR1_8 8
|
||
RESERVED0026 0x0026 RESERVED
|
||
RESERVED0027 0x0027 RESERVED
|
||
OCR1BL 0x0028 Output Compare Register 1 B Low
|
||
OCR1BL.OCR1B_7 7
|
||
OCR1BL.OCR1B_6 6
|
||
OCR1BL.OCR1B_5 5
|
||
OCR1BL.OCR1B_4 4
|
||
OCR1BL.OCR1B_3 3
|
||
OCR1BL.OCR1B_2 2
|
||
OCR1BL.OCR1B_1 1
|
||
OCR1BL.OCR1B_0 0
|
||
OCR1BH 0x0029 Output Compare Register 1 B High
|
||
OCR1BH.OCR1B_15 15
|
||
OCR1BH.OCR1B_14 14
|
||
OCR1BH.OCR1B_13 13
|
||
OCR1BH.OCR1B_12 12
|
||
OCR1BH.OCR1B_11 11
|
||
OCR1BH.OCR1B_10 10
|
||
OCR1BH.OCR1B_9 9
|
||
OCR1BH.OCR1B_8 8
|
||
OCR1AL 0x002A Output Compare Register 1 A Low
|
||
OCR1AL.OCR1A_7 7
|
||
OCR1AL.OCR1A_6 6
|
||
OCR1AL.OCR1A_5 5
|
||
OCR1AL.OCR1A_4 4
|
||
OCR1AL.OCR1A_3 3
|
||
OCR1AL.OCR1A_2 2
|
||
OCR1AL.OCR1A_1 1
|
||
OCR1AL.OCR1A_0 0
|
||
OCR1AH 0x002B Output Compare Register 1 A High
|
||
OCR1AH.OCR1A_15 15
|
||
OCR1AH.OCR1A_14 14
|
||
OCR1AH.OCR1A_13 13
|
||
OCR1AH.OCR1A_12 12
|
||
OCR1AH.OCR1A_11 11
|
||
OCR1AH.OCR1A_10 10
|
||
OCR1AH.OCR1A_9 9
|
||
OCR1AH.OCR1A_8 8
|
||
TCNT1L 0x002C Timer/Counter 1 Low
|
||
TCNT1L.TCNT1_7 7
|
||
TCNT1L.TCNT1_6 6
|
||
TCNT1L.TCNT1_5 5
|
||
TCNT1L.TCNT1_4 4
|
||
TCNT1L.TCNT1_3 3
|
||
TCNT1L.TCNT1_2 2
|
||
TCNT1L.TCNT1_1 1
|
||
TCNT1L.TCNT1_0 0
|
||
TCNT1H 0x002D Timer/Counter 1 High
|
||
TCNT1H.TCNT1_15 15
|
||
TCNT1H.TCNT1_14 14
|
||
TCNT1H.TCNT1_13 13
|
||
TCNT1H.TCNT1_12 12
|
||
TCNT1H.TCNT1_11 11
|
||
TCNT1H.TCNT1_10 10
|
||
TCNT1H.TCNT1_9 9
|
||
TCNT1H.TCNT1_8 8
|
||
TCCR1B 0x002E Timer/Counter 1 Control Register B
|
||
TCCR1B.ICNC1 7 Input Capture Noise Canceler
|
||
TCCR1B.ICES1 6 Input Capture Edge Select
|
||
TCCR1B.WGM13 4 Waveform Generation Mode 3
|
||
TCCR1B.WGM12 3 Waveform Generation Mode 2
|
||
TCCR1B.CS12 2 Clock Select 2
|
||
TCCR1B.CS11 1 Clock Select 1
|
||
TCCR1B.CS10 0 Clock Select 0
|
||
TCCR1A 0x002F Timer/Counter 1 Control Register A
|
||
TCCR1A.COM1A1 7 Compare Output Mode for channel A 1
|
||
TCCR1A.COM1A0 6 Compare Output Mode for channel A 0
|
||
TCCR1A.COM1B1 5 Compare Output Mode for channel B 1
|
||
TCCR1A.COM1B0 4 Compare Output Mode for channel B 0
|
||
TCCR1A.FOC1A 3 Force Output Compare for channel A
|
||
TCCR1A.FOC1B 2 Force Output Compare for channel B
|
||
TCCR1A.WGM11 1 Waveform Generation Mode 1
|
||
TCCR1A.WGM10 0 Waveform Generation Mode 0
|
||
SFIOR 0x0030 Special Function IO Register
|
||
SFIOR.XMBK 6 External Memory Bus Keeper Enable
|
||
SFIOR.XMM2 5 External Memory High Mask 2
|
||
SFIOR.XMM1 4 External Memory High Mask 1
|
||
SFIOR.XMM0 3 External Memory High Mask 0
|
||
SFIOR.PUD 2 Pull-up Disable
|
||
SFIOR.PSR10 0 Prescaler Reset Timer/Counter1 and Timer/Counter0
|
||
OCR0 0x0031 Output Compare Register
|
||
OCR0.OCR0_7 7
|
||
OCR0.OCR0_6 6
|
||
OCR0.OCR0_5 5
|
||
OCR0.OCR0_4 4
|
||
OCR0.OCR0_3 3
|
||
OCR0.OCR0_2 2
|
||
OCR0.OCR0_1 1
|
||
OCR0.OCR0_0 0
|
||
TCNT0 0x0032 Timer/Counter Register
|
||
TCNT0.TCNT0_7 7
|
||
TCNT0.TCNT0_6 6
|
||
TCNT0.TCNT0_5 5
|
||
TCNT0.TCNT0_4 4
|
||
TCNT0.TCNT0_3 3
|
||
TCNT0.TCNT0_2 2
|
||
TCNT0.TCNT0_1 1
|
||
TCNT0.TCNT0_0 0
|
||
TCCR0 0x0033 Timer/Counter Control Register
|
||
TCCR0.FOC0 7 Force Output Compare
|
||
TCCR0.WGM00 6 Waveform Generation Mode 0
|
||
TCCR0.COM01 5 Compare Match Output Mode 1
|
||
TCCR0.COM00 4 Compare Match Output Mode 0
|
||
TCCR0.WGM01 3 Waveform Generation Mode 1
|
||
TCCR0.CS02 2 Clock Select 2
|
||
TCCR0.CS01 1 Clock Select 1
|
||
TCCR0.CS00 0 Clock Select 0
|
||
MCUCSR 0x0034 MCU Control and Status Register
|
||
MCUCSR.SM2 5 Sleep Mode Select Bit 2
|
||
MCUCSR.WDRF 3 Watchdog Reset Flag
|
||
MCUCSR.BORF 2 Brown-out Reset Flag
|
||
MCUCSR.EXTRF 1 External Reset Flag
|
||
MCUCSR.PORF 0 Power-on Reset Flag
|
||
MCUCR 0x0035 MCU Control Register
|
||
MCUCR.SRE 7 External SRAM/XMEM Enable
|
||
MCUCR.SRW10 6 Wait State Select Bit
|
||
MCUCR.SE 5 SleepEnable
|
||
MCUCR.SM1 4 Sleep Mode Select Bit 1
|
||
MCUCR.ISC11 3 Interrupt Sense Control 1 Bit 1
|
||
MCUCR.ISC10 2 Interrupt Sense Control 1 Bit 0
|
||
MCUCR.ISC01 1 Interrupt Sense Control 0 Bit 1
|
||
MCUCR.ISC00 0 Interrupt Sense Control 0 Bit 0
|
||
EMCUCR 0x0036 Extended MCU Control Register
|
||
EMCUCR.SM0 7 Sleep Mode Select Bit 0
|
||
EMCUCR.SRL2 6 Wait State Sector Limit 2
|
||
EMCUCR.SRL1 5 Wait State Sector Limit 1
|
||
EMCUCR.SRL0 4 Wait State Sector Limit 0
|
||
EMCUCR.SRW01 3 Wait State Select Bits for Lower Sector 1
|
||
EMCUCR.SRW00 2 Wait State Select Bits for Lower Sector 0
|
||
EMCUCR.SRW11 1 Wait State Select Bits for Upper 1
|
||
EMCUCR.ISC2 0 Interrupt Sense Control 2
|
||
SPMCR 0x0037 Store Program Memory Control Register
|
||
SPMCR.SPMIE 7 SPM Interrupt Enable
|
||
SPMCR.RWWSB 6 Read-While-Write Section Busy
|
||
SPMCR.RWWSRE 4 Read-While-Write Section Read Enable
|
||
SPMCR.BLBSET 3 Boot Lock BitSet
|
||
SPMCR.PGWRT 2 Page Write
|
||
SPMCR.PGERS 1 Page Erase
|
||
SPMCR.SPMEN 0 Store Program Memory Enable
|
||
TIFR 0x0038 Timer/Counter Interrupt Flag Register
|
||
TIFR.TOV1 7 Timer/Counter1, Overflow Flag
|
||
TIFR.OCF1A 6 Timer/Counter1, Output Compare A Match Flag
|
||
TIFR.OCF1B 5 Timer/Counter1, Output Compare B Match Flag
|
||
TIFR.ICF1 3 Timer/Counter1, Input Capture Flag
|
||
TIFR.TOV0 1 Timer/Counter0 Overflow Flag
|
||
TIFR.OCF0 0 OutputCompare Flag0
|
||
TIMSK 0x0039 Timer/Counter Interrupt Mask Register
|
||
TIMSK.TOIE1 7 Timer/Counter1, Overflow Interrupt Enable
|
||
TIMSK.OCIE1A 6 Timer/Counter1, Output Compare A Match Interrupt Enable
|
||
TIMSK.OCIE1B 5 Timer/Counter1, Output Compare B Match Interrupt Enable
|
||
TIMSK.TICIE1 3 Timer/Counter1, Input Capture Interrupt Enable
|
||
TIMSK.TOIE0 1 Timer/Counter0 Overflow Interrupt Enable
|
||
TIMSK.OCIE0 0 Timer/Counter0 Output Compare Match Interrupt Enable
|
||
GIFR 0x003A General Interrupt Flag Register
|
||
GIFR.INTF1 7 External Interrupt Flag 1
|
||
GIFR.INTF0 6 External Interrupt Flag 0
|
||
GIFR.INTF2 5 External Interrupt Flag 2
|
||
GICR 0x003B General Interrupt Control Register
|
||
GICR.INT1 7 External Interrupt Request 1 Enable
|
||
GICR.INT0 6 External Interrupt Request 0 Enable
|
||
GICR.INT2 5 External Interrupt Request 2 Enable
|
||
GICR.IVSEL 1 Interrupt Vector Select
|
||
GICR.IVCE 0 Interrupt Vector Change Enable
|
||
RESERVED003C 0x003C RESERVED
|
||
SPL 0x003D Stack Pointer Low
|
||
SPL.SP7 7
|
||
SPL.SP6 6
|
||
SPL.SP5 5
|
||
SPL.SP4 4
|
||
SPL.SP3 3
|
||
SPL.SP2 2
|
||
SPL.SP1 1
|
||
SPL.SP0 0
|
||
SPH 0x003E Stack Pointer High
|
||
SPH.SP15 15
|
||
SPH.SP14 14
|
||
SPH.SP13 13
|
||
SPH.SP12 12
|
||
SPH.SP11 11
|
||
SPH.SP10 10
|
||
SPH.SP9 9
|
||
SPH.SP8 8
|
||
SREG 0x003F Status Register
|
||
SREG.I 7 Global Interrupt Enable
|
||
SREG.T 6 Bit Copy Storage
|
||
SREG.H 5 Half Carry Flag
|
||
SREG.S 4 Sign Bit
|
||
SREG.V 3 Two's Complement Overflow Flag
|
||
SREG.N 2 Negative Flag
|
||
SREG.Z 1 Zero Flag
|
||
SREG.C 0 Carry Flag
|
||
|
||
; OSCCAL 0x0024 Oscillator Calibration Register
|
||
; OSCCAL.CAL7 7 Oscillator Calibration Value 7
|
||
; OSCCAL.CAL6 6 Oscillator Calibration Value 6
|
||
; OSCCAL.CAL5 5 Oscillator Calibration Value 5
|
||
; OSCCAL.CAL4 4 Oscillator Calibration Value 4
|
||
; OSCCAL.CAL3 3 Oscillator Calibration Value 3
|
||
; OSCCAL.CAL2 2 Oscillator Calibration Value 2
|
||
; OSCCAL.CAL1 1 Oscillator Calibration Value 1
|
||
; OSCCAL.CAL0 0 Oscillator Calibration Value 0
|
||
; PINE 0x0025 Port E Input Pins Address
|
||
; PINE.PINE2 2
|
||
; PINE.PINE1 1
|
||
; PINE.PINE0 0
|
||
; DDRE 0x0026 Port E Data Direction Register
|
||
; DDRE.DDE2 2 Port E Data Direction Register bit 2
|
||
; DDRE.DDE1 1 Port E Data Direction Register bit 1
|
||
; DDRE.DDE0 0 Port E Data Direction Register bit 0
|
||
; PORTE 0x0027 Port E Data Register
|
||
; PORTE.PORTE2 2 Port E Data Register bit 2
|
||
; PORTE.PORTE1 1 Port E Data Register bit 1
|
||
; PORTE.PORTE0 0 Port E Data Register bit 0
|
||
; ACSR 0x0028 Analog Comparator Control and Status Register
|
||
; ACSR.ACD 7 Analog Comparator Disable
|
||
; ACSR.ACBG 6 Analog Comparator Bandgap Select
|
||
; ACSR.ACO 5 Analog Comparator Output
|
||
; ACSR.ACI 4 Analog Comparator Interrupt Flag
|
||
; ACSR.ACIE 3 Analog Comparator Interrupt Enable
|
||
; ACSR.ACIC 2 Analog Comparator Input Capture Enable
|
||
; ACSR.ACIS1 1 Analog Comparator Interrupt Mode Select 1
|
||
; ACSR.ACIS0 0 Analog Comparator Interrupt Mode Select 0
|
||
; UBRRL 0x0029 USART Baud Rate Register Low
|
||
; UBRRL.UBRR7 7 USART Baud Rate Register bit 7
|
||
; UBRRL.UBRR6 6 USART Baud Rate Register bit 6
|
||
; UBRRL.UBRR5 5 USART Baud Rate Register bit 5
|
||
; UBRRL.UBRR4 4 USART Baud Rate Register bit 4
|
||
; UBRRL.UBRR3 3 USART Baud Rate Register bit 3
|
||
; UBRRL.UBRR2 2 USART Baud Rate Register bit 2
|
||
; UBRRL.UBRR1 1 USART Baud Rate Register bit 1
|
||
; UBRRL.UBRR0 0 USART Baud Rate Register bit 0
|
||
; UCSRB 0x002A USART Control and Status Register B
|
||
; UCSRB.RXCIE 7 RX Complete Interrupt Enable
|
||
; UCSRB.TXCIE 6 TX Complete Interrupt Enable
|
||
; UCSRB.UDRIE 5 USART Data Register Empty Interrupt Enable
|
||
; UCSRB.RXEN 4 Receiver Enable
|
||
; UCSRB.TXEN 3 Transmitter Enable
|
||
; UCSRB.UCSZ2 2 Character Size
|
||
; UCSRB.RXB8 1 Receive Data Bit 8
|
||
; UCSRB.TXB8 0 Transmit Data Bit8
|
||
; UCSRA 0x002B USART Control and Status Register A
|
||
; UCSRA.RXC 7 USART Receive Complete
|
||
; UCSRA.TXC 6 USART Transmit Complete
|
||
; UCSRA.UDRE 5 USART Data Register Empty
|
||
; UCSRA.FE 4 Frame Error
|
||
; UCSRA.DOR 3 Data OverRun
|
||
; UCSRA.PE 2 ParityError
|
||
; UCSRA.U2X 1 Double the USART Transmission Speed
|
||
; UCSRA.MPCM 0 Multi-processor Communication Mode
|
||
; UDR 0x002C USART I/O Data Register
|
||
; SPCR 0x002D SPI Control Register
|
||
; SPCR.SPIE 7 SPI Interrupt Enable
|
||
; SPCR.SPE 6 SPI Enable
|
||
; SPCR.DORD 5 Data Order
|
||
; SPCR.MSTR 4 Master/Slave Select
|
||
; SPCR.CPOL 3 Clock Polarity
|
||
; SPCR.CPHA 2 Clock Phase
|
||
; SPCR.SPR1 1 SPI Clock Rate Select 1
|
||
; SPCR.SPR0 0 SPI Clock Rate Select 0
|
||
; SPSR 0x002E SPI Status Register
|
||
; SPSR.SPIF 7 SPI Interrupt Flag
|
||
; SPSR.WCOL 6 Write COLlision Flag
|
||
; SPSR.SPI2X 0 Double SPI Speed Bit
|
||
; SPDR 0x002F SPI Data Register
|
||
; PIND 0x0030 Port D Input Pins Address
|
||
; PIND.PIND7 7
|
||
; PIND.PIND6 6
|
||
; PIND.PIND5 5
|
||
; PIND.PIND4 4
|
||
; PIND.PIND3 3
|
||
; PIND.PIND2 2
|
||
; PIND.PIND1 1
|
||
; PIND.PIND0 0
|
||
; DDRD 0x0031 Port D Data Direction Register
|
||
; DDRD.DDD7 7 Port D Data Direction Register bit 7
|
||
; DDRD.DDD6 6 Port D Data Direction Register bit 6
|
||
; DDRD.DDD5 5 Port D Data Direction Register bit 5
|
||
; DDRD.DDD4 4 Port D Data Direction Register bit 4
|
||
; DDRD.DDD3 3 Port D Data Direction Register bit 3
|
||
; DDRD.DDD2 2 Port D Data Direction Register bit 2
|
||
; DDRD.DDD1 1 Port D Data Direction Register bit 1
|
||
; DDRD.DDD0 0 Port D Data Direction Register bit 0
|
||
; PORTD 0x0032 Port D Data Register
|
||
; PORTD.PORTD7 7 Port D Data Register bit 7
|
||
; PORTD.PORTD6 6 Port D Data Register bit 6
|
||
; PORTD.PORTD5 5 Port D Data Register bit 5
|
||
; PORTD.PORTD4 4 Port D Data Register bit 4
|
||
; PORTD.PORTD3 3 Port D Data Register bit 3
|
||
; PORTD.PORTD2 2 Port D Data Register bit 2
|
||
; PORTD.PORTD1 1 Port D Data Register bit 1
|
||
; PORTD.PORTD0 0 Port D Data Register bit 0
|
||
; PINC 0x0033 Port C Input Pins Address
|
||
; PINC.PINC7 7
|
||
; PINC.PINC6 6
|
||
; PINC.PINC5 5
|
||
; PINC.PINC4 4
|
||
; PINC.PINC3 3
|
||
; PINC.PINC2 2
|
||
; PINC.PINC1 1
|
||
; PINC.PINC0 0
|
||
; DDRC 0x0034 Port C Data Direction Register
|
||
; DDRC.DDC7 7 Port C Data Direction Register bit 7
|
||
; DDRC.DDC6 6 Port C Data Direction Register bit 6
|
||
; DDRC.DDC5 5 Port C Data Direction Register bit 5
|
||
; DDRC.DDC4 4 Port C Data Direction Register bit 4
|
||
; DDRC.DDC3 3 Port C Data Direction Register bit 3
|
||
; DDRC.DDC2 2 Port C Data Direction Register bit 2
|
||
; DDRC.DDC1 1 Port C Data Direction Register bit 1
|
||
; DDRC.DDC0 0 Port C Data Direction Register bit 0
|
||
; PORTC 0x0035 Port C Data Register
|
||
; PORTC.PORTC7 7 Port C Data Register bit 7
|
||
; PORTC.PORTC6 6 Port C Data Register bit 6
|
||
; PORTC.PORTC5 5 Port C Data Register bit 5
|
||
; PORTC.PORTC4 4 Port C Data Register bit 4
|
||
; PORTC.PORTC3 3 Port C Data Register bit 3
|
||
; PORTC.PORTC2 2 Port C Data Register bit 2
|
||
; PORTC.PORTC1 1 Port C Data Register bit 1
|
||
; PORTC.PORTC0 0 Port C Data Register bit 0
|
||
; PINB 0x0036 Port B Input Pins Address
|
||
; PINB.PINB7 7
|
||
; PINB.PINB6 6
|
||
; PINB.PINB5 5
|
||
; PINB.PINB4 4
|
||
; PINB.PINB3 3
|
||
; PINB.PINB2 2
|
||
; PINB.PINB1 1
|
||
; PINB.PINB0 0
|
||
; DDRB 0x0037 Port B Data Direction Register
|
||
; DDRB.DDB7 7 Port B Data Direction Register bit 7
|
||
; DDRB.DDB6 6 Port B Data Direction Register bit 6
|
||
; DDRB.DDB5 5 Port B Data Direction Register bit 5
|
||
; DDRB.DDB4 4 Port B Data Direction Register bit 4
|
||
; DDRB.DDB3 3 Port B Data Direction Register bit 3
|
||
; DDRB.DDB2 2 Port B Data Direction Register bit 2
|
||
; DDRB.DDB1 1 Port B Data Direction Register bit 1
|
||
; DDRB.DDB0 0 Port B Data Direction Register bit 0
|
||
; PORTB 0x0038 Port B Data Register
|
||
; PORTB.PORTB7 7 Port B Data Register bit 7
|
||
; PORTB.PORTB6 6 Port B Data Register bit 6
|
||
; PORTB.PORTB5 5 Port B Data Register bit 5
|
||
; PORTB.PORTB4 4 Port B Data Register bit 4
|
||
; PORTB.PORTB3 3 Port B Data Register bit 3
|
||
; PORTB.PORTB2 2 Port B Data Register bit 2
|
||
; PORTB.PORTB1 1 Port B Data Register bit 1
|
||
; PORTB.PORTB0 0 Port B Data Register bit 0
|
||
; PINA 0x0039 Port A Input Pins Address
|
||
; PINA.PINA7 7
|
||
; PINA.PINA6 6
|
||
; PINA.PINA5 5
|
||
; PINA.PINA4 4
|
||
; PINA.PINA3 3
|
||
; PINA.PINA2 2
|
||
; PINA.PINA1 1
|
||
; PINA.PINA0 0
|
||
; DDRA 0x003A Port A Data Direction Register
|
||
; DDRA.DDA7 7 Port A Data Direction Register bit 7
|
||
; DDRA.DDA6 6 Port A Data Direction Register bit 6
|
||
; DDRA.DDA5 5 Port A Data Direction Register bit 5
|
||
; DDRA.DDA4 4 Port A Data Direction Register bit 4
|
||
; DDRA.DDA3 3 Port A Data Direction Register bit 3
|
||
; DDRA.DDA2 2 Port A Data Direction Register bit 2
|
||
; DDRA.DDA1 1 Port A Data Direction Register bit 1
|
||
; DDRA.DDA0 0 Port A Data Direction Register bit 0
|
||
; PORTA 0x003B Port A Data Register
|
||
; PORTA.PORTA7 7 Port A Data Register bit 7
|
||
; PORTA.PORTA6 6 Port A Data Register bit 6
|
||
; PORTA.PORTA5 5 Port A Data Register bit 5
|
||
; PORTA.PORTA4 4 Port A Data Register bit 4
|
||
; PORTA.PORTA3 3 Port A Data Register bit 3
|
||
; PORTA.PORTA2 2 Port A Data Register bit 2
|
||
; PORTA.PORTA1 1 Port A Data Register bit 1
|
||
; PORTA.PORTA0 0 Port A Data Register bit 0
|
||
; EECR 0x003C EEPROM Control Register
|
||
; EECR.EERIE 3 EEPROM Ready Interrupt Enable
|
||
; EECR.EEMWE 2 EEPROM Master Write Enable
|
||
; EECR.EEWE 1 EEPROM Write Enable
|
||
; EECR.EERE 0 EEPROM Read Enable
|
||
; EEDR 0x003D EEPROM Data Register
|
||
; EEDR.EEDR7 7 EEPROM Data 7
|
||
; EEDR.EEDR6 6 EEPROM Data 6
|
||
; EEDR.EEDR5 5 EEPROM Data 5
|
||
; EEDR.EEDR4 4 EEPROM Data 4
|
||
; EEDR.EEDR3 3 EEPROM Data 3
|
||
; EEDR.EEDR2 2 EEPROM Data 2
|
||
; EEDR.EEDR1 1 EEPROM Data 1
|
||
; EEDR.EEDR0 0 EEPROM Data 0
|
||
; EEARL 0x003E EEPROM Address Register Low
|
||
; EEARL.EEAR7 7 EEPROM Addres 7
|
||
; EEARL.EEAR6 6 EEPROM Addres 6
|
||
; EEARL.EEAR5 5 EEPROM Addres 5
|
||
; EEARL.EEAR4 4 EEPROM Addres 4
|
||
; EEARL.EEAR3 3 EEPROM Addres 3
|
||
; EEARL.EEAR2 2 EEPROM Addres 2
|
||
; EEARL.EEAR1 1 EEPROM Addres 1
|
||
; EEARL.EEAR0 0 EEPROM Addres 0
|
||
; EEARH 0x003F EEPROM Address Register High
|
||
; EEARH.EEAR9 9 EEPROM Addres 9
|
||
; UCSRC 0x0040 USART Control and Status Register C
|
||
; UCSRC.URSEL 7 Register Select
|
||
; UCSRC.UMSEL 6 USART Mode Select
|
||
; UCSRC.UPM1 5 Parity Mode 1
|
||
; UCSRC.UPM0 4 Parity Mode 0
|
||
; UCSRC.USBS 3 Stop Bit Select
|
||
; UCSRC.UCSZ1 2 Character Size 1
|
||
; UCSRC.UCSZ0 1 Character Size 0
|
||
; UCSRC.UCPOL 0 Clock Polarity
|
||
; ; UBRRH 0x0040 USART Baud Rate Register High
|
||
; ; UBRRH.URSEL 15 Register Select
|
||
; ; UBRRH.UBRR11 11 USART Baud Rate Register bit 11
|
||
; ; UBRRH.UBRR10 10 USART Baud Rate Register bit 10
|
||
; ; UBRRH.UBRR9 9 USART Baud Rate Register bit 9
|
||
; ; UBRRH.UBRR8 8 USART Baud Rate Register bit 8
|
||
; WDTCR 0x0041 Watchdog Timer Control Register
|
||
; WDTCR.WDCE 4 Watchdog Change Enable
|
||
; WDTCR.WDE 3 Watchdog Enable
|
||
; WDTCR.WDP2 2 Watchdog Timer Prescaler 2
|
||
; WDTCR.WDP1 1 Watchdog Timer Prescaler 1
|
||
; WDTCR.WDP0 0 Watchdog Timer Prescaler 0
|
||
; RESERVED0042 0x0042 RESERVED
|
||
; RESERVED0043 0x0043 RESERVED
|
||
; ICR1L 0x0044 Input Capture Register 1 Low
|
||
; ICR1L.ICR1_7 7
|
||
; ICR1L.ICR1_6 6
|
||
; ICR1L.ICR1_5 5
|
||
; ICR1L.ICR1_4 4
|
||
; ICR1L.ICR1_3 3
|
||
; ICR1L.ICR1_2 2
|
||
; ICR1L.ICR1_1 1
|
||
; ICR1L.ICR1_0 0
|
||
; ICR1H 0x0045 Input Capture Register 1 High
|
||
; ICR1H.ICR1_15 15
|
||
; ICR1H.ICR1_14 14
|
||
; ICR1H.ICR1_13 13
|
||
; ICR1H.ICR1_12 12
|
||
; ICR1H.ICR1_11 11
|
||
; ICR1H.ICR1_10 10
|
||
; ICR1H.ICR1_9 9
|
||
; ICR1H.ICR1_8 8
|
||
; RESERVED0046 0x0046 RESERVED
|
||
; RESERVED0047 0x0047 RESERVED
|
||
; OCR1BL 0x0048 Output Compare Register 1 B Low
|
||
; OCR1BL.OCR1B_7 7
|
||
; OCR1BL.OCR1B_6 6
|
||
; OCR1BL.OCR1B_5 5
|
||
; OCR1BL.OCR1B_4 4
|
||
; OCR1BL.OCR1B_3 3
|
||
; OCR1BL.OCR1B_2 2
|
||
; OCR1BL.OCR1B_1 1
|
||
; OCR1BL.OCR1B_0 0
|
||
; OCR1BH 0x0049 Output Compare Register 1 B High
|
||
; OCR1BH.OCR1B_15 15
|
||
; OCR1BH.OCR1B_14 14
|
||
; OCR1BH.OCR1B_13 13
|
||
; OCR1BH.OCR1B_12 12
|
||
; OCR1BH.OCR1B_11 11
|
||
; OCR1BH.OCR1B_10 10
|
||
; OCR1BH.OCR1B_9 9
|
||
; OCR1BH.OCR1B_8 8
|
||
; OCR1AL 0x004A Output Compare Register 1 A Low
|
||
; OCR1AL.OCR1A_7 7
|
||
; OCR1AL.OCR1A_6 6
|
||
; OCR1AL.OCR1A_5 5
|
||
; OCR1AL.OCR1A_4 4
|
||
; OCR1AL.OCR1A_3 3
|
||
; OCR1AL.OCR1A_2 2
|
||
; OCR1AL.OCR1A_1 1
|
||
; OCR1AL.OCR1A_0 0
|
||
; OCR1AH 0x004B Output Compare Register 1 A High
|
||
; OCR1AH.OCR1A_15 15
|
||
; OCR1AH.OCR1A_14 14
|
||
; OCR1AH.OCR1A_13 13
|
||
; OCR1AH.OCR1A_12 12
|
||
; OCR1AH.OCR1A_11 11
|
||
; OCR1AH.OCR1A_10 10
|
||
; OCR1AH.OCR1A_9 9
|
||
; OCR1AH.OCR1A_8 8
|
||
; TCNT1L 0x004C Timer/Counter 1 Low
|
||
; TCNT1L.TCNT1_7 7
|
||
; TCNT1L.TCNT1_6 6
|
||
; TCNT1L.TCNT1_5 5
|
||
; TCNT1L.TCNT1_4 4
|
||
; TCNT1L.TCNT1_3 3
|
||
; TCNT1L.TCNT1_2 2
|
||
; TCNT1L.TCNT1_1 1
|
||
; TCNT1L.TCNT1_0 0
|
||
; TCNT1H 0x004D Timer/Counter 1 High
|
||
; TCNT1H.TCNT1_15 15
|
||
; TCNT1H.TCNT1_14 14
|
||
; TCNT1H.TCNT1_13 13
|
||
; TCNT1H.TCNT1_12 12
|
||
; TCNT1H.TCNT1_11 11
|
||
; TCNT1H.TCNT1_10 10
|
||
; TCNT1H.TCNT1_9 9
|
||
; TCNT1H.TCNT1_8 8
|
||
; TCCR1B 0x004E Timer/Counter 1 Control Register B
|
||
; TCCR1B.ICNC1 7 Input Capture Noise Canceler
|
||
; TCCR1B.ICES1 6 Input Capture Edge Select
|
||
; TCCR1B.WGM13 4 Waveform Generation Mode 3
|
||
; TCCR1B.WGM12 3 Waveform Generation Mode 2
|
||
; TCCR1B.CS12 2 Clock Select 2
|
||
; TCCR1B.CS11 1 Clock Select 1
|
||
; TCCR1B.CS10 0 Clock Select 0
|
||
; TCCR1A 0x004F Timer/Counter 1 Control Register A
|
||
; TCCR1A.COM1A1 7 Compare Output Mode for channel A 1
|
||
; TCCR1A.COM1A0 6 Compare Output Mode for channel A 0
|
||
; TCCR1A.COM1B1 5 Compare Output Mode for channel B 1
|
||
; TCCR1A.COM1B0 4 Compare Output Mode for channel B 0
|
||
; TCCR1A.FOC1A 3 Force Output Compare for channel A
|
||
; TCCR1A.FOC1B 2 Force Output Compare for channel B
|
||
; TCCR1A.WGM11 1 Waveform Generation Mode 1
|
||
; TCCR1A.WGM10 0 Waveform Generation Mode 0
|
||
; SFIOR 0x0050 Special Function IO Register
|
||
; SFIOR.XMBK 6 External Memory Bus Keeper Enable
|
||
; SFIOR.XMM2 5 External Memory High Mask 2
|
||
; SFIOR.XMM1 4 External Memory High Mask 1
|
||
; SFIOR.XMM0 3 External Memory High Mask 0
|
||
; SFIOR.PUD 2 Pull-up Disable
|
||
; SFIOR.PSR10 0 Prescaler Reset Timer/Counter1 and Timer/Counter0
|
||
; OCR0 0x0051 Output Compare Register
|
||
; OCR0.OCR0_7 7
|
||
; OCR0.OCR0_6 6
|
||
; OCR0.OCR0_5 5
|
||
; OCR0.OCR0_4 4
|
||
; OCR0.OCR0_3 3
|
||
; OCR0.OCR0_2 2
|
||
; OCR0.OCR0_1 1
|
||
; OCR0.OCR0_0 0
|
||
; TCNT0 0x0052 Timer/Counter Register
|
||
; TCNT0.TCNT0_7 7
|
||
; TCNT0.TCNT0_6 6
|
||
; TCNT0.TCNT0_5 5
|
||
; TCNT0.TCNT0_4 4
|
||
; TCNT0.TCNT0_3 3
|
||
; TCNT0.TCNT0_2 2
|
||
; TCNT0.TCNT0_1 1
|
||
; TCNT0.TCNT0_0 0
|
||
; TCCR0 0x0053 Timer/Counter Control Register
|
||
; TCCR0.FOC0 7 Force Output Compare
|
||
; TCCR0.WGM00 6 Waveform Generation Mode 0
|
||
; TCCR0.COM01 5 Compare Match Output Mode 1
|
||
; TCCR0.COM00 4 Compare Match Output Mode 0
|
||
; TCCR0.WGM01 3 Waveform Generation Mode 1
|
||
; TCCR0.CS02 2 Clock Select 2
|
||
; TCCR0.CS01 1 Clock Select 1
|
||
; TCCR0.CS00 0 Clock Select 0
|
||
; MCUCSR 0x0054 MCU Control and Status Register
|
||
; MCUCSR.SM2 5 Sleep Mode Select Bit 2
|
||
; MCUCSR.WDRF 3 Watchdog Reset Flag
|
||
; MCUCSR.BORF 2 Brown-out Reset Flag
|
||
; MCUCSR.EXTRF 1 External Reset Flag
|
||
; MCUCSR.PORF 0 Power-on Reset Flag
|
||
; MCUCR 0x0055 MCU Control Register
|
||
; MCUCR.SRE 7 External SRAM/XMEM Enable
|
||
; MCUCR.SRW10 6 Wait State Select Bit
|
||
; MCUCR.SE 5 SleepEnable
|
||
; MCUCR.SM1 4 Sleep Mode Select Bit 1
|
||
; MCUCR.ISC11 3 Interrupt Sense Control 1 Bit 1
|
||
; MCUCR.ISC10 2 Interrupt Sense Control 1 Bit 0
|
||
; MCUCR.ISC01 1 Interrupt Sense Control 0 Bit 1
|
||
; MCUCR.ISC00 0 Interrupt Sense Control 0 Bit 0
|
||
; EMCUCR 0x0056 Extended MCU Control Register
|
||
; EMCUCR.SM0 7 Sleep Mode Select Bit 0
|
||
; EMCUCR.SRL2 6 Wait State Sector Limit 2
|
||
; EMCUCR.SRL1 5 Wait State Sector Limit 1
|
||
; EMCUCR.SRL0 4 Wait State Sector Limit 0
|
||
; EMCUCR.SRW01 3 Wait State Select Bits for Lower Sector 1
|
||
; EMCUCR.SRW00 2 Wait State Select Bits for Lower Sector 0
|
||
; EMCUCR.SRW11 1 Wait State Select Bits for Upper 1
|
||
; EMCUCR.ISC2 0 Interrupt Sense Control 2
|
||
; SPMCR 0x0057 Store Program Memory Control Register
|
||
; SPMCR.SPMIE 7 SPM Interrupt Enable
|
||
; SPMCR.RWWSB 6 Read-While-Write Section Busy
|
||
; SPMCR.RWWSRE 4 Read-While-Write Section Read Enable
|
||
; SPMCR.BLBSET 3 Boot Lock BitSet
|
||
; SPMCR.PGWRT 2 Page Write
|
||
; SPMCR.PGERS 1 Page Erase
|
||
; SPMCR.SPMEN 0 Store Program Memory Enable
|
||
; TIFR 0x0058 Timer/Counter Interrupt Flag Register
|
||
; TIFR.TOV1 7 Timer/Counter1, Overflow Flag
|
||
; TIFR.OCF1A 6 Timer/Counter1, Output Compare A Match Flag
|
||
; TIFR.OCF1B 5 Timer/Counter1, Output Compare B Match Flag
|
||
; TIFR.ICF1 3 Timer/Counter1, Input Capture Flag
|
||
; TIFR.TOV0 1 Timer/Counter0 Overflow Flag
|
||
; TIFR.OCF0 0 OutputCompare Flag0
|
||
; TIMSK 0x0059 Timer/Counter Interrupt Mask Register
|
||
; TIMSK.TOIE1 7 Timer/Counter1, Overflow Interrupt Enable
|
||
; TIMSK.OCIE1A 6 Timer/Counter1, Output Compare A Match Interrupt Enable
|
||
; TIMSK.OCIE1B 5 Timer/Counter1, Output Compare B Match Interrupt Enable
|
||
; TIMSK.TICIE1 3 Timer/Counter1, Input Capture Interrupt Enable
|
||
; TIMSK.TOIE0 1 Timer/Counter0 Overflow Interrupt Enable
|
||
; TIMSK.OCIE0 0 Timer/Counter0 Output Compare Match Interrupt Enable
|
||
; GIFR 0x005A General Interrupt Flag Register
|
||
; GIFR.INTF1 7 External Interrupt Flag 1
|
||
; GIFR.INTF0 6 External Interrupt Flag 0
|
||
; GIFR.INTF2 5 External Interrupt Flag 2
|
||
; GICR 0x005B General Interrupt Control Register
|
||
; GICR.INT1 7 External Interrupt Request 1 Enable
|
||
; GICR.INT0 6 External Interrupt Request 0 Enable
|
||
; GICR.INT2 5 External Interrupt Request 2 Enable
|
||
; GICR.IVSEL 1 Interrupt Vector Select
|
||
; GICR.IVCE 0 Interrupt Vector Change Enable
|
||
; RESERVED005C 0x005C RESERVED
|
||
; SPL 0x005D Stack Pointer Low
|
||
; SPL.SP7 7
|
||
; SPL.SP6 6
|
||
; SPL.SP5 5
|
||
; SPL.SP4 4
|
||
; SPL.SP3 3
|
||
; SPL.SP2 2
|
||
; SPL.SP1 1
|
||
; SPL.SP0 0
|
||
; SPH 0x005E Stack Pointer High
|
||
; SPH.SP15 15
|
||
; SPH.SP14 14
|
||
; SPH.SP13 13
|
||
; SPH.SP12 12
|
||
; SPH.SP11 11
|
||
; SPH.SP10 10
|
||
; SPH.SP9 9
|
||
; SPH.SP8 8
|
||
; SREG 0x005F Status Register
|
||
; SREG.I 7 Global Interrupt Enable
|
||
; SREG.T 6 Bit Copy Storage
|
||
; SREG.H 5 Half Carry Flag
|
||
; SREG.S 4 Sign Bit
|
||
; SREG.V 3 Two's Complement Overflow Flag
|
||
; SREG.N 2 Negative Flag
|
||
; SREG.Z 1 Zero Flag
|
||
; SREG.C 0 Carry Flag
|
||
|
||
|
||
.ATmega8535_L
|
||
SUBARCH=2
|
||
; doc2502.pdf
|
||
;
|
||
|
||
RAM=512
|
||
ROM=8192
|
||
EEPROM=512
|
||
|
||
; MEMORY MAP
|
||
area DATA FSR 0x0000:0x0060
|
||
area DATA I_SRAM 0x0060:0x0260 Internal SRAM
|
||
|
||
|
||
; Interrupt and reset vector assignments
|
||
entry __RESET 0x0000 External Pin, Power-on Reset, Brown-out Reset and Watchdog Reset
|
||
entry INT0_ 0x0001 External Interrupt Request 0
|
||
entry INT1_ 0x0002 External Interrupt Request 1
|
||
entry TIMER2_COMP 0x0003 Timer/Counter2 Compare Match
|
||
entry TIMER2_OVF 0x0004 Timer/Counter2 Overflow
|
||
entry TIMER1_CAPT 0x0005 Timer/Counter1 Capture Event
|
||
entry TIMER1_COMPA 0x0006 Timer/Counter1 Compare Match A
|
||
entry TIMER1_COMPB 0x0007 Timer/Counter1 Compare Match B
|
||
entry TIMER1_OVF 0x0008 Timer/Counter1 Overflow
|
||
entry TIMER0_OVF 0x0009 Timer/Counter0 Overflow
|
||
entry SPI_STC 0x000A Serial Transfer Complete
|
||
entry USART_RXC 0x000B USART, Rx Complete
|
||
entry USART_UDRE 0x000C USART Data Register Empty
|
||
entry USART_TXC 0x000D USART, Tx Complete
|
||
entry ADC_ 0x000E ADC Conversion Complete
|
||
entry EE_RDY 0x000F EEPROM Ready
|
||
entry ANA_COMP 0x0010 Analog Comparator
|
||
entry TWI_ 0x0011 Two-wire Serial Interface
|
||
entry INT2_ 0x0012 External Interrupt Request 2
|
||
entry TIMER0_COMP 0x0013 Timer/Counter0 Compare Match
|
||
entry SPM_RDY 0x0014 Store Program Memory Ready
|
||
|
||
|
||
; INPUT/OUTPUT PORTS
|
||
TWBR 0x0000 TWI Bit Rate Register
|
||
TWBR.TWBR7 7 TWI Bit Rate Register bit 7
|
||
TWBR.TWBR6 6 TWI Bit Rate Register bit 6
|
||
TWBR.TWBR5 5 TWI Bit Rate Register bit 5
|
||
TWBR.TWBR4 4 TWI Bit Rate Register bit 4
|
||
TWBR.TWBR3 3 TWI Bit Rate Register bit 3
|
||
TWBR.TWBR2 2 TWI Bit Rate Register bit 2
|
||
TWBR.TWBR1 1 TWI Bit Rate Register bit 1
|
||
TWBR.TWBR0 0 TWI Bit Rate Register bit 0
|
||
TWSR 0x0001 TWI Status Register
|
||
TWSR.TWS7 7 TWI Status
|
||
TWSR.TWS6 6 TWI Status
|
||
TWSR.TWS5 5 TWI Status
|
||
TWSR.TWS4 4 TWI Status
|
||
TWSR.TWS3 3 TWI Status
|
||
TWSR.TWPS1 1 TWI Prescaler Bit 1
|
||
TWSR.TWPS0 0 TWI Prescaler Bit 0
|
||
TWAR 0x0002 TWI (Slave) Address Register
|
||
TWAR.TWA6 7 TWI (Slave) Address Register bit 6
|
||
TWAR.TWA5 6 TWI (Slave) Address Register bit 5
|
||
TWAR.TWA4 5 TWI (Slave) Address Register bit 4
|
||
TWAR.TWA3 4 TWI (Slave) Address Register bit 3
|
||
TWAR.TWA2 3 TWI (Slave) Address Register bit 2
|
||
TWAR.TWA1 2 TWI (Slave) Address Register bit 1
|
||
TWAR.TWA0 1 TWI (Slave) Address Register bit 0
|
||
TWAR.TWGCE 0 TWI General Call Recognition Enable Bit
|
||
TWDR 0x0003 TWI Data Register
|
||
TWDR.TWD7 7 TWI Data Register bit 7
|
||
TWDR.TWD6 6 TWI Data Register bit 6
|
||
TWDR.TWD5 5 TWI Data Register bit 5
|
||
TWDR.TWD4 4 TWI Data Register bit 4
|
||
TWDR.TWD3 3 TWI Data Register bit 3
|
||
TWDR.TWD2 2 TWI Data Register bit 2
|
||
TWDR.TWD1 1 TWI Data Register bit 1
|
||
TWDR.TWD0 0 TWI Data Register bit 0
|
||
ADCL 0x0004 ADC Data Register Low (ADLAR = 0)
|
||
ADCL.ADC7 7 ADC Conversion Result 7
|
||
ADCL.ADC6 6 ADC Conversion Result 6
|
||
ADCL.ADC5 5 ADC Conversion Result 5
|
||
ADCL.ADC4 4 ADC Conversion Result 4
|
||
ADCL.ADC3 3 ADC Conversion Result 3
|
||
ADCL.ADC2 2 ADC Conversion Result 2
|
||
ADCL.ADC1 1 ADC Conversion Result 1
|
||
ADCL.ADC0 0 ADC Conversion Result 0
|
||
ADCH 0x0005 ADC Data Register High (ADLAR = 0)
|
||
ADCH.ADC9 9 ADC Conversion Result 9
|
||
ADCH.ADC8 8 ADC Conversion Result 8
|
||
; ADCL 0x0004 ADC Data Register Low (ADLAR = 1)
|
||
; ADCL.ADC1 7 ADC Conversion Result 1
|
||
; ADCL.ADC0 6 ADC Conversion Result 0
|
||
; ADCH 0x0005 ADC Data Register High (ADLAR = 1)
|
||
; ADCH.ADC9 15 ADC Conversion Result 9
|
||
; ADCH.ADC8 14 ADC Conversion Result 8
|
||
; ADCH.ADC7 13 ADC Conversion Result 7
|
||
; ADCH.ADC6 12 ADC Conversion Result 6
|
||
; ADCH.ADC5 11 ADC Conversion Result 5
|
||
; ADCH.ADC4 10 ADC Conversion Result 4
|
||
; ADCH.ADC3 9 ADC Conversion Result 3
|
||
; ADCH.ADC2 8 ADC Conversion Result 2
|
||
ADCSRA 0x0006 ADC Control and Status Register A
|
||
ADCSRA.ADEN 7 ADC Enable
|
||
ADCSRA.ADSC 6 ADC Start Conversion
|
||
ADCSRA.ADATE 5 ADC Auto Trigger Enable
|
||
ADCSRA.ADIF 4 ADC Interrupt Flag
|
||
ADCSRA.ADIE 3 ADC Interrupt Enable
|
||
ADCSRA.ADPS2 2 ADC Prescaler Select Bit 2
|
||
ADCSRA.ADPS1 1 ADC Prescaler Select Bit 1
|
||
ADCSRA.ADPS0 0 ADC Prescaler Select Bit 0
|
||
ADMUX 0x0007 ADC Multiplexer Selection Register
|
||
ADMUX.REFS1 7 Reference Selection Bit 1
|
||
ADMUX.REFS0 6 Reference Selection Bit 0
|
||
ADMUX.ADLAR 5 ADC Left Adjust Result
|
||
ADMUX.MUX4 4 Analog Channel and Gain Selection Bit 4
|
||
ADMUX.MUX3 3 Analog Channel and Gain Selection Bit 3
|
||
ADMUX.MUX2 2 Analog Channel and Gain Selection Bit 2
|
||
ADMUX.MUX1 1 Analog Channel and Gain Selection Bit 1
|
||
ADMUX.MUX0 0 Analog Channel and Gain Selection Bit 0
|
||
ACSR 0x0008 Analog Comparator Control and Status Register
|
||
ACSR.ACD 7 Analog Comparator Disable
|
||
ACSR.ACBG 6 Analog Comparator Bandgap Select
|
||
ACSR.ACO 5 Analog Comparator Output
|
||
ACSR.ACI 4 Analog Comparator Interrupt Flag
|
||
ACSR.ACIE 3 Analog Comparator Interrupt Enable
|
||
ACSR.ACIC 2 Analog Comparator Input Capture Enable
|
||
ACSR.ACIS1 1 Analog Comparator Interrupt Mode Select 1
|
||
ACSR.ACIS0 0 Analog Comparator Interrupt Mode Select 0
|
||
UBRRL 0x0009 USART Baud Rate Register Low
|
||
UBRRL.UBRR7 7 USART Baud Rate Register bit 7
|
||
UBRRL.UBRR6 6 USART Baud Rate Register bit 6
|
||
UBRRL.UBRR5 5 USART Baud Rate Register bit 5
|
||
UBRRL.UBRR4 4 USART Baud Rate Register bit 4
|
||
UBRRL.UBRR3 3 USART Baud Rate Register bit 3
|
||
UBRRL.UBRR2 2 USART Baud Rate Register bit 2
|
||
UBRRL.UBRR1 1 USART Baud Rate Register bit 1
|
||
UBRRL.UBRR0 0 USART Baud Rate Register bit 0
|
||
UCSRB 0x000A USART Control and Status Register B
|
||
UCSRB.RXCIE 7 RX Complete Interrupt Enable
|
||
UCSRB.TXCIE 6 TX Complete Interrupt Enable
|
||
UCSRB.UDRIE 5 USART Data Register Empty Interrupt Enable
|
||
UCSRB.RXEN 4 Receiver Enable
|
||
UCSRB.TXEN 3 Transmitter Enable
|
||
UCSRB.UCSZ2 2 Character Size
|
||
UCSRB.RXB8 1 Receive Data Bit 8
|
||
UCSRB.TXB8 0 Transmit Data Bit 8
|
||
UCSRA 0x000B USART Control and Status Register A
|
||
UCSRA.RXC 7 USART Receive Complete
|
||
UCSRA.TXC 6 USART Transmit Complete
|
||
UCSRA.UDRE 5 USART Data Register Empty
|
||
UCSRA.FE 4 Frame Error
|
||
UCSRA.DOR 3 Data OverRun
|
||
UCSRA.PE 2 Parity Error
|
||
UCSRA.U2X 1 Double the USART Transmission Speed
|
||
UCSRA.MPCM 0 Multi-processor Communication Mode
|
||
UDR 0x000C USART I/O Data Register
|
||
SPCR 0x000D SPI Control Register
|
||
SPCR.SPIE 7 SPI Interrupt Enable
|
||
SPCR.SPE 6 SPI Enable
|
||
SPCR.DORD 5 Data Order
|
||
SPCR.MSTR 4 Master/Slave Select
|
||
SPCR.CPOL 3 Clock Polarity
|
||
SPCR.CPHA 2 Clock Phase
|
||
SPCR.SPR1 1 SPI Clock Rate Select 1
|
||
SPCR.SPR0 0 SPI Clock Rate Select 0
|
||
SPSR 0x000E SPI Status Register
|
||
SPSR.SPIF 7 SPI Interrupt Flag
|
||
SPSR.WCOL 6 Write COLlision flag
|
||
SPSR.SPI2X 0 Double SPI Speed Bit
|
||
SPDR 0x000F SPI Data Register
|
||
PIND 0x0010 Port D Input Pins Address
|
||
PIND.PIND7 7
|
||
PIND.PIND6 6
|
||
PIND.PIND5 5
|
||
PIND.PIND4 4
|
||
PIND.PIND3 3
|
||
PIND.PIND2 2
|
||
PIND.PIND1 1
|
||
PIND.PIND0 0
|
||
DDRD 0x0011 Port D Data Direction Register
|
||
DDRD.DDD7 7 Port D Data Direction Register bit 7
|
||
DDRD.DDD6 6 Port D Data Direction Register bit 6
|
||
DDRD.DDD5 5 Port D Data Direction Register bit 5
|
||
DDRD.DDD4 4 Port D Data Direction Register bit 4
|
||
DDRD.DDD3 3 Port D Data Direction Register bit 3
|
||
DDRD.DDD2 2 Port D Data Direction Register bit 2
|
||
DDRD.DDD1 1 Port D Data Direction Register bit 1
|
||
DDRD.DDD0 0 Port D Data Direction Register bit 0
|
||
PORTD 0x0012 Port D Data Register
|
||
PORTD.PORTD7 7 Port D Data Register bit 7
|
||
PORTD.PORTD6 6 Port D Data Register bit 6
|
||
PORTD.PORTD5 5 Port D Data Register bit 5
|
||
PORTD.PORTD4 4 Port D Data Register bit 4
|
||
PORTD.PORTD3 3 Port D Data Register bit 3
|
||
PORTD.PORTD2 2 Port D Data Register bit 2
|
||
PORTD.PORTD1 1 Port D Data Register bit 1
|
||
PORTD.PORTD0 0 Port D Data Register bit 0
|
||
PINC 0x0013 Port C Input Pins Address
|
||
PINC.PINC7 7
|
||
PINC.PINC6 6
|
||
PINC.PINC5 5
|
||
PINC.PINC4 4
|
||
PINC.PINC3 3
|
||
PINC.PINC2 2
|
||
PINC.PINC1 1
|
||
PINC.PINC0 0
|
||
DDRC 0x0014 Port C Data Direction Register
|
||
DDRC.DDC7 7 Port C Data Direction Register bit 7
|
||
DDRC.DDC6 6 Port C Data Direction Register bit 6
|
||
DDRC.DDC5 5 Port C Data Direction Register bit 5
|
||
DDRC.DDC4 4 Port C Data Direction Register bit 4
|
||
DDRC.DDC3 3 Port C Data Direction Register bit 3
|
||
DDRC.DDC2 2 Port C Data Direction Register bit 2
|
||
DDRC.DDC1 1 Port C Data Direction Register bit 1
|
||
DDRC.DDC0 0 Port C Data Direction Register bit 0
|
||
PORTC 0x0015 Port C Data Register
|
||
PORTC.PORTC7 7 Port C Data Register bit 7
|
||
PORTC.PORTC6 6 Port C Data Register bit 6
|
||
PORTC.PORTC5 5 Port C Data Register bit 5
|
||
PORTC.PORTC4 4 Port C Data Register bit 4
|
||
PORTC.PORTC3 3 Port C Data Register bit 3
|
||
PORTC.PORTC2 2 Port C Data Register bit 2
|
||
PORTC.PORTC1 1 Port C Data Register bit 1
|
||
PORTC.PORTC0 0 Port C Data Register bit 0
|
||
PINB 0x0016 Port B Input Pins Address
|
||
PINB.PINB7 7
|
||
PINB.PINB6 6
|
||
PINB.PINB5 5
|
||
PINB.PINB4 4
|
||
PINB.PINB3 3
|
||
PINB.PINB2 2
|
||
PINB.PINB1 1
|
||
PINB.PINB0 0
|
||
DDRB 0x0017 Port B Data Direction Register
|
||
DDRB.DDB7 7 Port B Data Direction Register bit 7
|
||
DDRB.DDB6 6 Port B Data Direction Register bit 6
|
||
DDRB.DDB5 5 Port B Data Direction Register bit 5
|
||
DDRB.DDB4 4 Port B Data Direction Register bit 4
|
||
DDRB.DDB3 3 Port B Data Direction Register bit 3
|
||
DDRB.DDB2 2 Port B Data Direction Register bit 2
|
||
DDRB.DDB1 1 Port B Data Direction Register bit 1
|
||
DDRB.DDB0 0 Port B Data Direction Register bit 0
|
||
PORTB 0x0018 Port B Data Register
|
||
PORTB.PORTB7 7 Port B Data Register bit 7
|
||
PORTB.PORTB6 6 Port B Data Register bit 6
|
||
PORTB.PORTB5 5 Port B Data Register bit 5
|
||
PORTB.PORTB4 4 Port B Data Register bit 4
|
||
PORTB.PORTB3 3 Port B Data Register bit 3
|
||
PORTB.PORTB2 2 Port B Data Register bit 2
|
||
PORTB.PORTB1 1 Port B Data Register bit 1
|
||
PORTB.PORTB0 0 Port B Data Register bit 0
|
||
PINA 0x0019 Port A Input Pins Address
|
||
PINA.PINA7 7
|
||
PINA.PINA6 6
|
||
PINA.PINA5 5
|
||
PINA.PINA4 4
|
||
PINA.PINA3 3
|
||
PINA.PINA2 2
|
||
PINA.PINA1 1
|
||
PINA.PINA0 0
|
||
DDRA 0x001A Port A Data Direction Register
|
||
DDRA.DDA7 7 Port A Data Direction Register bit 7
|
||
DDRA.DDA6 6 Port A Data Direction Register bit 6
|
||
DDRA.DDA5 5 Port A Data Direction Register bit 5
|
||
DDRA.DDA4 4 Port A Data Direction Register bit 4
|
||
DDRA.DDA3 3 Port A Data Direction Register bit 3
|
||
DDRA.DDA2 2 Port A Data Direction Register bit 2
|
||
DDRA.DDA1 1 Port A Data Direction Register bit 1
|
||
DDRA.DDA0 0 Port A Data Direction Register bit 0
|
||
PORTA 0x001B Port A Data Register
|
||
PORTA.PORTA7 7 Port A Data Register bit 7
|
||
PORTA.PORTA6 6 Port A Data Register bit 6
|
||
PORTA.PORTA5 5 Port A Data Register bit 5
|
||
PORTA.PORTA4 4 Port A Data Register bit 4
|
||
PORTA.PORTA3 3 Port A Data Register bit 3
|
||
PORTA.PORTA2 2 Port A Data Register bit 2
|
||
PORTA.PORTA1 1 Port A Data Register bit 1
|
||
PORTA.PORTA0 0 Port A Data Register bit 0
|
||
EECR 0x001C EEPROM Control Register
|
||
EECR.EERIE 3 EEPROM Ready Interrupt Enable
|
||
EECR.EEMWE 2 EEPROM Master Write Enable
|
||
EECR.EEWE 1 EEPROM Write Enable
|
||
EECR.EERE 0 EEPROM Read Enable
|
||
EEDR 0x001D EEPROM Data Register
|
||
EEDR.EEDR7 7 EEPROM Data 7
|
||
EEDR.EEDR6 6 EEPROM Data 6
|
||
EEDR.EEDR5 5 EEPROM Data 5
|
||
EEDR.EEDR4 4 EEPROM Data 4
|
||
EEDR.EEDR3 3 EEPROM Data 3
|
||
EEDR.EEDR2 2 EEPROM Data 2
|
||
EEDR.EEDR1 1 EEPROM Data 1
|
||
EEDR.EEDR0 0 EEPROM Data 0
|
||
EEARL 0x001E EEPROM Address Register Low
|
||
EEARL.EEAR7 7 EEPROM Addres 7
|
||
EEARL.EEAR6 6 EEPROM Addres 6
|
||
EEARL.EEAR5 5 EEPROM Addres 5
|
||
EEARL.EEAR4 4 EEPROM Addres 4
|
||
EEARL.EEAR3 3 EEPROM Addres 3
|
||
EEARL.EEAR2 2 EEPROM Addres 2
|
||
EEARL.EEAR1 1 EEPROM Addres 1
|
||
EEARL.EEAR0 0 EEPROM Addres 0
|
||
EEARH 0x001F EEPROM Address Register High
|
||
EEARH.EEAR8 8 EEPROM Addres 8
|
||
UCSRC 0x0020 USART Control and Status Register (page 159)
|
||
UCSRC.URSEL 7 Register Select
|
||
UCSRC.UMSEL 6 USART Mode Select
|
||
UCSRC.UPM1 5 Parity Mode 1
|
||
UCSRC.UPM0 4 Parity Mode 0
|
||
UCSRC.USBS 3 Stop Bit Select
|
||
UCSRC.UCSZ1 2 Character Size 1
|
||
UCSRC.UCSZ0 1 Character Size 0
|
||
UCSRC.UCPOL 0 Clock Polarity
|
||
; UBRRH 0x0020 USART Baud Rate Register High (page 159)
|
||
; UBRRH.URSEL 15 Register Select
|
||
; UBRRH.UBRR11 11 USART Baud Rate Register bit 11
|
||
; UBRRH.UBRR10 10 USART Baud Rate Register bit 10
|
||
; UBRRH.UBRR9 9 USART Baud Rate Register bit 9
|
||
; UBRRH.UBRR8 8 USART Baud Rate Register bit 8
|
||
WDTCR 0x0021 Watchdog Timer Control Register
|
||
WDTCR.WDCE 4 Watchdog Change Enable
|
||
WDTCR.WDE 3 Watchdog Enable
|
||
WDTCR.WDP2 2 Watchdog Timer Prescaler 2
|
||
WDTCR.WDP1 1 Watchdog Timer Prescaler 1
|
||
WDTCR.WDP0 0 Watchdog Timer Prescaler 0
|
||
ASSR 0x0022 Asynchronous Status Register
|
||
ASSR.AS2 3 Asynchronous Timer/Counter2
|
||
ASSR.TCN2UB 2 Timer/Counter2 Update Busy
|
||
ASSR.OCR2UB 1 Output Compare Register 2 Update Busy
|
||
ASSR.TCR2UB 0 Timer/Counter Control Register 2 Update Busy
|
||
OCR2 0x0023 Output Compare Register
|
||
OCR2.OCR2_7 7
|
||
OCR2.OCR2_6 6
|
||
OCR2.OCR2_5 5
|
||
OCR2.OCR2_4 4
|
||
OCR2.OCR2_3 3
|
||
OCR2.OCR2_2 2
|
||
OCR2.OCR2_1 1
|
||
OCR2.OCR2_0 0
|
||
TCNT2 0x0024 Timer/Counter Register
|
||
TCNT2.TCNT2_7 7
|
||
TCNT2.TCNT2_6 6
|
||
TCNT2.TCNT2_5 5
|
||
TCNT2.TCNT2_4 4
|
||
TCNT2.TCNT2_3 3
|
||
TCNT2.TCNT2_2 2
|
||
TCNT2.TCNT2_1 1
|
||
TCNT2.TCNT2_0 0
|
||
TCCR2 0x0025 Timer/Counter Control Register
|
||
TCCR2.FOC2 7 Force Output Compare
|
||
TCCR2.WGM20 6 Waveform Generation Mode 0
|
||
TCCR2.COM21 5 Compare Match Output Mode 1
|
||
TCCR2.COM20 4 Compare Match Output Mode 0
|
||
TCCR2.WGM21 3 Waveform Generation Mode 1
|
||
TCCR2.CS22 2 Clock Select 2
|
||
TCCR2.CS21 1 Clock Select 1
|
||
TCCR2.CS20 0 Clock Select 0
|
||
ICR1L 0x0026 Input Capture Register 1 Low
|
||
ICR1L.ICR1_7 7
|
||
ICR1L.ICR1_6 6
|
||
ICR1L.ICR1_5 5
|
||
ICR1L.ICR1_4 4
|
||
ICR1L.ICR1_3 3
|
||
ICR1L.ICR1_2 2
|
||
ICR1L.ICR1_1 1
|
||
ICR1L.ICR1_0 0
|
||
ICR1H 0x0027 Input Capture Register 1 High
|
||
ICR1H.ICR1_15 15
|
||
ICR1H.ICR1_14 14
|
||
ICR1H.ICR1_13 13
|
||
ICR1H.ICR1_12 12
|
||
ICR1H.ICR1_11 11
|
||
ICR1H.ICR1_10 10
|
||
ICR1H.ICR1_9 9
|
||
ICR1H.ICR1_8 8
|
||
OCR1BL 0x0028 Output Compare Register 1 B Low
|
||
OCR1BL.OCR1B_7 7
|
||
OCR1BL.OCR1B_6 6
|
||
OCR1BL.OCR1B_5 5
|
||
OCR1BL.OCR1B_4 4
|
||
OCR1BL.OCR1B_3 3
|
||
OCR1BL.OCR1B_2 2
|
||
OCR1BL.OCR1B_1 1
|
||
OCR1BL.OCR1B_0 0
|
||
OCR1BH 0x0029 Output Compare Register 1 B High
|
||
OCR1BH.OCR1B_15 15
|
||
OCR1BH.OCR1B_14 14
|
||
OCR1BH.OCR1B_13 13
|
||
OCR1BH.OCR1B_12 12
|
||
OCR1BH.OCR1B_11 11
|
||
OCR1BH.OCR1B_10 10
|
||
OCR1BH.OCR1B_9 9
|
||
OCR1BH.OCR1B_8 8
|
||
OCR1AL 0x002A Output Compare Register 1 A Low
|
||
OCR1AL.OCR1A_7 7
|
||
OCR1AL.OCR1A_6 6
|
||
OCR1AL.OCR1A_5 5
|
||
OCR1AL.OCR1A_4 4
|
||
OCR1AL.OCR1A_3 3
|
||
OCR1AL.OCR1A_2 2
|
||
OCR1AL.OCR1A_1 1
|
||
OCR1AL.OCR1A_0 0
|
||
OCR1AH 0x002B Output Compare Register 1 A High
|
||
OCR1AH.OCR1A_15 15
|
||
OCR1AH.OCR1A_14 14
|
||
OCR1AH.OCR1A_13 13
|
||
OCR1AH.OCR1A_12 12
|
||
OCR1AH.OCR1A_11 11
|
||
OCR1AH.OCR1A_10 10
|
||
OCR1AH.OCR1A_9 9
|
||
OCR1AH.OCR1A_8 8
|
||
TCNT1L 0x002C Timer/Counter 1 Low
|
||
TCNT1L.TCNT1_7 7
|
||
TCNT1L.TCNT1_6 6
|
||
TCNT1L.TCNT1_5 5
|
||
TCNT1L.TCNT1_4 4
|
||
TCNT1L.TCNT1_3 3
|
||
TCNT1L.TCNT1_2 2
|
||
TCNT1L.TCNT1_1 1
|
||
TCNT1L.TCNT1_0 0
|
||
TCNT1H 0x002D Timer/Counter 1 High
|
||
TCNT1H.TCNT1_15 15
|
||
TCNT1H.TCNT1_14 14
|
||
TCNT1H.TCNT1_13 13
|
||
TCNT1H.TCNT1_12 12
|
||
TCNT1H.TCNT1_11 11
|
||
TCNT1H.TCNT1_10 10
|
||
TCNT1H.TCNT1_9 9
|
||
TCNT1H.TCNT1_8 8
|
||
TCCR1B 0x002E Timer/Counter1 Control Register B
|
||
TCCR1B.ICNC1 7 Input Capture Noise Canceler
|
||
TCCR1B.ICES1 6 Input Capture Edge Select
|
||
TCCR1B.WGM13 4 Waveform Generation Mode 3
|
||
TCCR1B.WGM12 3 Waveform Generation Mode 2
|
||
TCCR1B.CS12 2 Clock Select 2
|
||
TCCR1B.CS11 1 Clock Select 1
|
||
TCCR1B.CS10 0 Clock Select 0
|
||
TCCR1A 0x002F Timer/Counter1 Control Register A
|
||
TCCR1A.COM1A1 7 Compare Output Mode for Channel A 1
|
||
TCCR1A.COM1A0 6 Compare Output Mode for Channel A 0
|
||
TCCR1A.COM1B1 5 Compare Output Mode for Channel B 1
|
||
TCCR1A.COM1B0 4 Compare Output Mode for Channel B 0
|
||
TCCR1A.FOC1A 3 Force Output Compare for Channel A
|
||
TCCR1A.FOC1B 2 Force Output Compare for Channel B
|
||
TCCR1A.WGM11 1 Waveform Generation Mode 1
|
||
TCCR1A.WGM10 0 Waveform Generation Mode 0
|
||
SFIOR 0x0030 Special Function IO Register
|
||
SFIOR.ADTS2 7 ADC Auto Trigger Source 2
|
||
SFIOR.ADTS1 6 ADC Auto Trigger Source 1
|
||
SFIOR.ADTS0 5 ADC Auto Trigger Source 0
|
||
SFIOR.ADHSM 4 ADC High Speed Mode
|
||
SFIOR.ACME 3 Analog Comparator Multiplexer Enable
|
||
SFIOR.PUD 2 Pull-up disable
|
||
SFIOR.PSR2 1 Prescaler Reset Timer/Counter2
|
||
SFIOR.PSR10 0 Prescaler Reset Timer/Counter1 and Timer/Counter0
|
||
OSCCAL 0x0031 Oscillator Calibration Register
|
||
OSCCAL.CAL7 7 Oscillator Calibration Value 7
|
||
OSCCAL.CAL6 6 Oscillator Calibration Value 6
|
||
OSCCAL.CAL5 5 Oscillator Calibration Value 5
|
||
OSCCAL.CAL4 4 Oscillator Calibration Value 4
|
||
OSCCAL.CAL3 3 Oscillator Calibration Value 3
|
||
OSCCAL.CAL2 2 Oscillator Calibration Value 2
|
||
OSCCAL.CAL1 1 Oscillator Calibration Value 1
|
||
OSCCAL.CAL0 0 Oscillator Calibration Value 0
|
||
TCNT0 0x0032 Timer/Counter Register
|
||
TCNT0.TCNT0_7 7
|
||
TCNT0.TCNT0_6 6
|
||
TCNT0.TCNT0_5 5
|
||
TCNT0.TCNT0_4 4
|
||
TCNT0.TCNT0_3 3
|
||
TCNT0.TCNT0_2 2
|
||
TCNT0.TCNT0_1 1
|
||
TCNT0.TCNT0_0 0
|
||
TCCR0 0x0033 Timer/Counter Control Register
|
||
TCCR0.FOC0 7 Force Output Compare
|
||
TCCR0.WGM00 6 Waveform Generation Mode 0
|
||
TCCR0.COM01 5 Compare Match Output Mode 1
|
||
TCCR0.COM00 4 Compare Match Output Mode 0
|
||
TCCR0.WGM01 3 Waveform Generation Mode 1
|
||
TCCR0.CS02 2 Clock Select 2
|
||
TCCR0.CS01 1 Clock Select 1
|
||
TCCR0.CS00 0 Clock Select 0
|
||
MCUCSR 0x0034 MCU Control and Status Register
|
||
MCUCSR.ISC2 6 Interrupt Sense Control 2
|
||
MCUCSR.WDRF 3 Watchdog Reset Flag
|
||
MCUCSR.BORF 2 Brown-out Reset Flag
|
||
MCUCSR.EXTRF 1 External Reset Flag
|
||
MCUCSR.PORF 0 Power-on Reset Flag
|
||
MCUCR 0x0035 MCU Control Register
|
||
MCUCR.SM2 7 Sleep Mode Select Bit 2
|
||
MCUCR.SE 6 Sleep Enable
|
||
MCUCR.SM1 5 Sleep Mode Select Bit 1
|
||
MCUCR.SM0 4 Sleep Mode Select Bit 0
|
||
MCUCR.ISC11 3 Interrupt Sense Control 1 Bit 1
|
||
MCUCR.ISC10 2 Interrupt Sense Control 1 Bit 0
|
||
MCUCR.ISC01 1 Interrupt Sense Control 0 Bit 1
|
||
MCUCR.ISC00 0 Interrupt Sense Control 0 Bit 0
|
||
TWCR 0x0036 TWI Control Register
|
||
TWCR.TWINT 7 TWI Interrupt Flag
|
||
TWCR.TWEA 6 TWI Enable Acknowledge Bit
|
||
TWCR.TWSTA 5 TWI START Condition Bit
|
||
TWCR.TWSTO 4 TWI STOP Condition Bit
|
||
TWCR.TWWC 3 TWI Write Collision Flag
|
||
TWCR.TWEN 2 TWI Enable Bit
|
||
TWCR.TWIE 0 TWI Interrupt Enable
|
||
SPMCR 0x0037 Store Program Memory Control Register
|
||
SPMCR.SPMIE 7 SPM Interrupt Enable
|
||
SPMCR.RWWSB 6 Read-While-Write Section Busy
|
||
SPMCR.RWWSRE 4 Read-While-Write Section Read Enable
|
||
SPMCR.BLBSET 3 Boot Lock Bit Set
|
||
SPMCR.PGWRT 2 Page Write
|
||
SPMCR.PGERS 1 Page Erase
|
||
SPMCR.SPMEN 0 Store Program Memory Enable
|
||
TIFR 0x0038 Timer/Counter Interrupt Flag Register
|
||
TIFR.OCF2 7 Output Compare Flag 2
|
||
TIFR.TOV2 6 Timer/Counter2 Overflow Flag
|
||
TIFR.ICF1 5 Timer/Counter1, Input Capture Flag
|
||
TIFR.OCF1A 4 Timer/Counter1, Output Compare A Match Flag
|
||
TIFR.OCF1B 3 Timer/Counter1, Output Compare B Match Flag
|
||
TIFR.TOV1 2 Timer/Counter1, Overflow Flag
|
||
TIFR.OCF0 1 Output Compare Flag 0
|
||
TIFR.TOV0 0 Timer/Counter0 Overflow Flag
|
||
TIMSK 0x0039 Timer/Counter Interrupt Mask Register
|
||
TIMSK.OCIE2 7 Timer/Counter2 Output Compare Match Interrupt Enable
|
||
TIMSK.TOIE2 6 Timer/Counter2 Overflow Interrupt Enable
|
||
TIMSK.TICIE1 5 Timer/Counter1, Input Capture Interrupt Enable
|
||
TIMSK.OCIE1A 4 Timer/Counter1, Output Compare A Match Interrupt Enable
|
||
TIMSK.OCIE1B 3 Timer/Counter1, Output Compare B Match Interrupt Enable
|
||
TIMSK.TOIE1 2 Timer/Counter1, Overflow Interrupt Enable
|
||
TIMSK.OCIE0 1 Timer/Counter0 Output Compare Match Interrupt Enable
|
||
TIMSK.TOIE0 0 Timer/Counter0 Overflow Interrupt Enable
|
||
GIFR 0x003A General Interrupt Flag Register
|
||
GIFR.INTF1 7 External Interrupt Flag 1
|
||
GIFR.INTF0 6 External Interrupt Flag 0
|
||
GIFR.INTF2 5 External Interrupt Flag 2
|
||
GICR 0x003B General Interrupt Control Register
|
||
GICR.INT1 7 External Interrupt Request 1 Enable
|
||
GICR.INT0 6 External Interrupt Request 0 Enable
|
||
GICR.INT2 5 External Interrupt Request 2 Enable
|
||
GICR.IVSEL 1 Interrupt Vector Select
|
||
GICR.IVCE 0 Interrupt Vector Change Enable
|
||
OCR0 0x003C Output Compare Register
|
||
OCR0.OCR0_7 7
|
||
OCR0.OCR0_6 6
|
||
OCR0.OCR0_5 5
|
||
OCR0.OCR0_4 4
|
||
OCR0.OCR0_3 3
|
||
OCR0.OCR0_2 2
|
||
OCR0.OCR0_1 1
|
||
OCR0.OCR0_0 0
|
||
SPL 0x003D Stack Pointer Low
|
||
SPL.SP7 7
|
||
SPL.SP6 6
|
||
SPL.SP5 5
|
||
SPL.SP4 4
|
||
SPL.SP3 3
|
||
SPL.SP2 2
|
||
SPL.SP1 1
|
||
SPL.SP0 0
|
||
SPH 0x003E Stack Pointer High
|
||
SPH.SP10 10
|
||
SPH.SP9 9
|
||
SPH.SP8 8
|
||
SREG 0x003F Status Register
|
||
SREG.I 7 Global Interrupt Enable
|
||
SREG.T 6 Bit Copy Storage
|
||
SREG.H 5 Half Carry Flag
|
||
SREG.S 4 Sign Bit
|
||
SREG.V 3 Two's Complement Overflow Flag
|
||
SREG.N 2 Negative Flag
|
||
SREG.Z 1 Zero Flag
|
||
SREG.C 0 Carry Flag
|
||
|
||
; TWBR 0x0020 TWI Bit Rate Register
|
||
; TWBR.TWBR7 7 TWI Bit Rate Register bit 7
|
||
; TWBR.TWBR6 6 TWI Bit Rate Register bit 6
|
||
; TWBR.TWBR5 5 TWI Bit Rate Register bit 5
|
||
; TWBR.TWBR4 4 TWI Bit Rate Register bit 4
|
||
; TWBR.TWBR3 3 TWI Bit Rate Register bit 3
|
||
; TWBR.TWBR2 2 TWI Bit Rate Register bit 2
|
||
; TWBR.TWBR1 1 TWI Bit Rate Register bit 1
|
||
; TWBR.TWBR0 0 TWI Bit Rate Register bit 0
|
||
; TWSR 0x0021 TWI Status Register
|
||
; TWSR.TWS7 7 TWI Status
|
||
; TWSR.TWS6 6 TWI Status
|
||
; TWSR.TWS5 5 TWI Status
|
||
; TWSR.TWS4 4 TWI Status
|
||
; TWSR.TWS3 3 TWI Status
|
||
; TWSR.TWPS1 1 TWI Prescaler Bit 1
|
||
; TWSR.TWPS0 0 TWI Prescaler Bit 0
|
||
; TWAR 0x0022 TWI (Slave) Address Register
|
||
; TWAR.TWA6 7 TWI (Slave) Address Register bit 6
|
||
; TWAR.TWA5 6 TWI (Slave) Address Register bit 5
|
||
; TWAR.TWA4 5 TWI (Slave) Address Register bit 4
|
||
; TWAR.TWA3 4 TWI (Slave) Address Register bit 3
|
||
; TWAR.TWA2 3 TWI (Slave) Address Register bit 2
|
||
; TWAR.TWA1 2 TWI (Slave) Address Register bit 1
|
||
; TWAR.TWA0 1 TWI (Slave) Address Register bit 0
|
||
; TWAR.TWGCE 0 TWI General Call Recognition Enable Bit
|
||
; TWDR 0x0023 TWI Data Register
|
||
; TWDR.TWD7 7 TWI Data Register bit 7
|
||
; TWDR.TWD6 6 TWI Data Register bit 6
|
||
; TWDR.TWD5 5 TWI Data Register bit 5
|
||
; TWDR.TWD4 4 TWI Data Register bit 4
|
||
; TWDR.TWD3 3 TWI Data Register bit 3
|
||
; TWDR.TWD2 2 TWI Data Register bit 2
|
||
; TWDR.TWD1 1 TWI Data Register bit 1
|
||
; TWDR.TWD0 0 TWI Data Register bit 0
|
||
; ADCL 0x0024 ADC Data Register Low (ADLAR = 0)
|
||
; ADCL.ADC7 7 ADC Conversion Result 7
|
||
; ADCL.ADC6 6 ADC Conversion Result 6
|
||
; ADCL.ADC5 5 ADC Conversion Result 5
|
||
; ADCL.ADC4 4 ADC Conversion Result 4
|
||
; ADCL.ADC3 3 ADC Conversion Result 3
|
||
; ADCL.ADC2 2 ADC Conversion Result 2
|
||
; ADCL.ADC1 1 ADC Conversion Result 1
|
||
; ADCL.ADC0 0 ADC Conversion Result 0
|
||
; ADCH 0x0025 ADC Data Register High (ADLAR = 0)
|
||
; ADCH.ADC9 9 ADC Conversion Result 9
|
||
; ADCH.ADC8 8 ADC Conversion Result 8
|
||
; ; ADCL 0x0024 ADC Data Register Low (ADLAR = 1)
|
||
; ; ADCL.ADC1 7 ADC Conversion Result 1
|
||
; ; ADCL.ADC0 6 ADC Conversion Result 0
|
||
; ; ADCH 0x0025 ADC Data Register High (ADLAR = 1)
|
||
; ; ADCH.ADC9 15 ADC Conversion Result 9
|
||
; ; ADCH.ADC8 14 ADC Conversion Result 8
|
||
; ; ADCH.ADC7 13 ADC Conversion Result 7
|
||
; ; ADCH.ADC6 12 ADC Conversion Result 6
|
||
; ; ADCH.ADC5 11 ADC Conversion Result 5
|
||
; ; ADCH.ADC4 10 ADC Conversion Result 4
|
||
; ; ADCH.ADC3 9 ADC Conversion Result 3
|
||
; ; ADCH.ADC2 8 ADC Conversion Result 2
|
||
; ADCSRA 0x0026 ADC Control and Status Register A
|
||
; ADCSRA.ADEN 7 ADC Enable
|
||
; ADCSRA.ADSC 6 ADC Start Conversion
|
||
; ADCSRA.ADATE 5 ADC Auto Trigger Enable
|
||
; ADCSRA.ADIF 4 ADC Interrupt Flag
|
||
; ADCSRA.ADIE 3 ADC Interrupt Enable
|
||
; ADCSRA.ADPS2 2 ADC Prescaler Select Bit 2
|
||
; ADCSRA.ADPS1 1 ADC Prescaler Select Bit 1
|
||
; ADCSRA.ADPS0 0 ADC Prescaler Select Bit 0
|
||
; ADMUX 0x0027 ADC Multiplexer Selection Register
|
||
; ADMUX.REFS1 7 Reference Selection Bit 1
|
||
; ADMUX.REFS0 6 Reference Selection Bit 0
|
||
; ADMUX.ADLAR 5 ADC Left Adjust Result
|
||
; ADMUX.MUX4 4 Analog Channel and Gain Selection Bit 4
|
||
; ADMUX.MUX3 3 Analog Channel and Gain Selection Bit 3
|
||
; ADMUX.MUX2 2 Analog Channel and Gain Selection Bit 2
|
||
; ADMUX.MUX1 1 Analog Channel and Gain Selection Bit 1
|
||
; ADMUX.MUX0 0 Analog Channel and Gain Selection Bit 0
|
||
; ACSR 0x0028 Analog Comparator Control and Status Register
|
||
; ACSR.ACD 7 Analog Comparator Disable
|
||
; ACSR.ACBG 6 Analog Comparator Bandgap Select
|
||
; ACSR.ACO 5 Analog Comparator Output
|
||
; ACSR.ACI 4 Analog Comparator Interrupt Flag
|
||
; ACSR.ACIE 3 Analog Comparator Interrupt Enable
|
||
; ACSR.ACIC 2 Analog Comparator Input Capture Enable
|
||
; ACSR.ACIS1 1 Analog Comparator Interrupt Mode Select 1
|
||
; ACSR.ACIS0 0 Analog Comparator Interrupt Mode Select 0
|
||
; UBRRL 0x0029 USART Baud Rate Register Low
|
||
; UBRRL.UBRR7 7 USART Baud Rate Register bit 7
|
||
; UBRRL.UBRR6 6 USART Baud Rate Register bit 6
|
||
; UBRRL.UBRR5 5 USART Baud Rate Register bit 5
|
||
; UBRRL.UBRR4 4 USART Baud Rate Register bit 4
|
||
; UBRRL.UBRR3 3 USART Baud Rate Register bit 3
|
||
; UBRRL.UBRR2 2 USART Baud Rate Register bit 2
|
||
; UBRRL.UBRR1 1 USART Baud Rate Register bit 1
|
||
; UBRRL.UBRR0 0 USART Baud Rate Register bit 0
|
||
; UCSRB 0x002A USART Control and Status Register B
|
||
; UCSRB.RXCIE 7 RX Complete Interrupt Enable
|
||
; UCSRB.TXCIE 6 TX Complete Interrupt Enable
|
||
; UCSRB.UDRIE 5 USART Data Register Empty Interrupt Enable
|
||
; UCSRB.RXEN 4 Receiver Enable
|
||
; UCSRB.TXEN 3 Transmitter Enable
|
||
; UCSRB.UCSZ2 2 Character Size
|
||
; UCSRB.RXB8 1 Receive Data Bit 8
|
||
; UCSRB.TXB8 0 Transmit Data Bit 8
|
||
; UCSRA 0x002B USART Control and Status Register A
|
||
; UCSRA.RXC 7 USART Receive Complete
|
||
; UCSRA.TXC 6 USART Transmit Complete
|
||
; UCSRA.UDRE 5 USART Data Register Empty
|
||
; UCSRA.FE 4 Frame Error
|
||
; UCSRA.DOR 3 Data OverRun
|
||
; UCSRA.PE 2 Parity Error
|
||
; UCSRA.U2X 1 Double the USART Transmission Speed
|
||
; UCSRA.MPCM 0 Multi-processor Communication Mode
|
||
; UDR 0x002C USART I/O Data Register
|
||
; SPCR 0x002D SPI Control Register
|
||
; SPCR.SPIE 7 SPI Interrupt Enable
|
||
; SPCR.SPE 6 SPI Enable
|
||
; SPCR.DORD 5 Data Order
|
||
; SPCR.MSTR 4 Master/Slave Select
|
||
; SPCR.CPOL 3 Clock Polarity
|
||
; SPCR.CPHA 2 Clock Phase
|
||
; SPCR.SPR1 1 SPI Clock Rate Select 1
|
||
; SPCR.SPR0 0 SPI Clock Rate Select 0
|
||
; SPSR 0x002E SPI Status Register
|
||
; SPSR.SPIF 7 SPI Interrupt Flag
|
||
; SPSR.WCOL 6 Write COLlision flag
|
||
; SPSR.SPI2X 0 Double SPI Speed Bit
|
||
; SPDR 0x002F SPI Data Register
|
||
; PIND 0x0030 Port D Input Pins Address
|
||
; PIND.PIND7 7
|
||
; PIND.PIND6 6
|
||
; PIND.PIND5 5
|
||
; PIND.PIND4 4
|
||
; PIND.PIND3 3
|
||
; PIND.PIND2 2
|
||
; PIND.PIND1 1
|
||
; PIND.PIND0 0
|
||
; DDRD 0x0031 Port D Data Direction Register
|
||
; DDRD.DDD7 7 Port D Data Direction Register bit 7
|
||
; DDRD.DDD6 6 Port D Data Direction Register bit 6
|
||
; DDRD.DDD5 5 Port D Data Direction Register bit 5
|
||
; DDRD.DDD4 4 Port D Data Direction Register bit 4
|
||
; DDRD.DDD3 3 Port D Data Direction Register bit 3
|
||
; DDRD.DDD2 2 Port D Data Direction Register bit 2
|
||
; DDRD.DDD1 1 Port D Data Direction Register bit 1
|
||
; DDRD.DDD0 0 Port D Data Direction Register bit 0
|
||
; PORTD 0x0032 Port D Data Register
|
||
; PORTD.PORTD7 7 Port D Data Register bit 7
|
||
; PORTD.PORTD6 6 Port D Data Register bit 6
|
||
; PORTD.PORTD5 5 Port D Data Register bit 5
|
||
; PORTD.PORTD4 4 Port D Data Register bit 4
|
||
; PORTD.PORTD3 3 Port D Data Register bit 3
|
||
; PORTD.PORTD2 2 Port D Data Register bit 2
|
||
; PORTD.PORTD1 1 Port D Data Register bit 1
|
||
; PORTD.PORTD0 0 Port D Data Register bit 0
|
||
; PINC 0x0033 Port C Input Pins Address
|
||
; PINC.PINC7 7
|
||
; PINC.PINC6 6
|
||
; PINC.PINC5 5
|
||
; PINC.PINC4 4
|
||
; PINC.PINC3 3
|
||
; PINC.PINC2 2
|
||
; PINC.PINC1 1
|
||
; PINC.PINC0 0
|
||
; DDRC 0x0034 Port C Data Direction Register
|
||
; DDRC.DDC7 7 Port C Data Direction Register bit 7
|
||
; DDRC.DDC6 6 Port C Data Direction Register bit 6
|
||
; DDRC.DDC5 5 Port C Data Direction Register bit 5
|
||
; DDRC.DDC4 4 Port C Data Direction Register bit 4
|
||
; DDRC.DDC3 3 Port C Data Direction Register bit 3
|
||
; DDRC.DDC2 2 Port C Data Direction Register bit 2
|
||
; DDRC.DDC1 1 Port C Data Direction Register bit 1
|
||
; DDRC.DDC0 0 Port C Data Direction Register bit 0
|
||
; PORTC 0x0035 Port C Data Register
|
||
; PORTC.PORTC7 7 Port C Data Register bit 7
|
||
; PORTC.PORTC6 6 Port C Data Register bit 6
|
||
; PORTC.PORTC5 5 Port C Data Register bit 5
|
||
; PORTC.PORTC4 4 Port C Data Register bit 4
|
||
; PORTC.PORTC3 3 Port C Data Register bit 3
|
||
; PORTC.PORTC2 2 Port C Data Register bit 2
|
||
; PORTC.PORTC1 1 Port C Data Register bit 1
|
||
; PORTC.PORTC0 0 Port C Data Register bit 0
|
||
; PINB 0x0036 Port B Input Pins Address
|
||
; PINB.PINB7 7
|
||
; PINB.PINB6 6
|
||
; PINB.PINB5 5
|
||
; PINB.PINB4 4
|
||
; PINB.PINB3 3
|
||
; PINB.PINB2 2
|
||
; PINB.PINB1 1
|
||
; PINB.PINB0 0
|
||
; DDRB 0x0037 Port B Data Direction Register
|
||
; DDRB.DDB7 7 Port B Data Direction Register bit 7
|
||
; DDRB.DDB6 6 Port B Data Direction Register bit 6
|
||
; DDRB.DDB5 5 Port B Data Direction Register bit 5
|
||
; DDRB.DDB4 4 Port B Data Direction Register bit 4
|
||
; DDRB.DDB3 3 Port B Data Direction Register bit 3
|
||
; DDRB.DDB2 2 Port B Data Direction Register bit 2
|
||
; DDRB.DDB1 1 Port B Data Direction Register bit 1
|
||
; DDRB.DDB0 0 Port B Data Direction Register bit 0
|
||
; PORTB 0x0038 Port B Data Register
|
||
; PORTB.PORTB7 7 Port B Data Register bit 7
|
||
; PORTB.PORTB6 6 Port B Data Register bit 6
|
||
; PORTB.PORTB5 5 Port B Data Register bit 5
|
||
; PORTB.PORTB4 4 Port B Data Register bit 4
|
||
; PORTB.PORTB3 3 Port B Data Register bit 3
|
||
; PORTB.PORTB2 2 Port B Data Register bit 2
|
||
; PORTB.PORTB1 1 Port B Data Register bit 1
|
||
; PORTB.PORTB0 0 Port B Data Register bit 0
|
||
; PINA 0x0039 Port A Input Pins Address
|
||
; PINA.PINA7 7
|
||
; PINA.PINA6 6
|
||
; PINA.PINA5 5
|
||
; PINA.PINA4 4
|
||
; PINA.PINA3 3
|
||
; PINA.PINA2 2
|
||
; PINA.PINA1 1
|
||
; PINA.PINA0 0
|
||
; DDRA 0x003A Port A Data Direction Register
|
||
; DDRA.DDA7 7 Port A Data Direction Register bit 7
|
||
; DDRA.DDA6 6 Port A Data Direction Register bit 6
|
||
; DDRA.DDA5 5 Port A Data Direction Register bit 5
|
||
; DDRA.DDA4 4 Port A Data Direction Register bit 4
|
||
; DDRA.DDA3 3 Port A Data Direction Register bit 3
|
||
; DDRA.DDA2 2 Port A Data Direction Register bit 2
|
||
; DDRA.DDA1 1 Port A Data Direction Register bit 1
|
||
; DDRA.DDA0 0 Port A Data Direction Register bit 0
|
||
; PORTA 0x003B Port A Data Register
|
||
; PORTA.PORTA7 7 Port A Data Register bit 7
|
||
; PORTA.PORTA6 6 Port A Data Register bit 6
|
||
; PORTA.PORTA5 5 Port A Data Register bit 5
|
||
; PORTA.PORTA4 4 Port A Data Register bit 4
|
||
; PORTA.PORTA3 3 Port A Data Register bit 3
|
||
; PORTA.PORTA2 2 Port A Data Register bit 2
|
||
; PORTA.PORTA1 1 Port A Data Register bit 1
|
||
; PORTA.PORTA0 0 Port A Data Register bit 0
|
||
; EECR 0x003C EEPROM Control Register
|
||
; EECR.EERIE 3 EEPROM Ready Interrupt Enable
|
||
; EECR.EEMWE 2 EEPROM Master Write Enable
|
||
; EECR.EEWE 1 EEPROM Write Enable
|
||
; EECR.EERE 0 EEPROM Read Enable
|
||
; EEDR 0x003D EEPROM Data Register
|
||
; EEDR.EEDR7 7 EEPROM Data 7
|
||
; EEDR.EEDR6 6 EEPROM Data 6
|
||
; EEDR.EEDR5 5 EEPROM Data 5
|
||
; EEDR.EEDR4 4 EEPROM Data 4
|
||
; EEDR.EEDR3 3 EEPROM Data 3
|
||
; EEDR.EEDR2 2 EEPROM Data 2
|
||
; EEDR.EEDR1 1 EEPROM Data 1
|
||
; EEDR.EEDR0 0 EEPROM Data 0
|
||
; EEARL 0x003E EEPROM Address Register Low
|
||
; EEARL.EEAR7 7 EEPROM Addres 7
|
||
; EEARL.EEAR6 6 EEPROM Addres 6
|
||
; EEARL.EEAR5 5 EEPROM Addres 5
|
||
; EEARL.EEAR4 4 EEPROM Addres 4
|
||
; EEARL.EEAR3 3 EEPROM Addres 3
|
||
; EEARL.EEAR2 2 EEPROM Addres 2
|
||
; EEARL.EEAR1 1 EEPROM Addres 1
|
||
; EEARL.EEAR0 0 EEPROM Addres 0
|
||
; EEARH 0x003F EEPROM Address Register High
|
||
; EEARH.EEAR8 8 EEPROM Addres 8
|
||
; UCSRC 0x0040 USART Control and Status Register (page 159)
|
||
; UCSRC.URSEL 7 Register Select
|
||
; UCSRC.UMSEL 6 USART Mode Select
|
||
; UCSRC.UPM1 5 Parity Mode 1
|
||
; UCSRC.UPM0 4 Parity Mode 0
|
||
; UCSRC.USBS 3 Stop Bit Select
|
||
; UCSRC.UCSZ1 2 Character Size 1
|
||
; UCSRC.UCSZ0 1 Character Size 0
|
||
; UCSRC.UCPOL 0 Clock Polarity
|
||
; ; UBRRH 0x0040 USART Baud Rate Register High (page 159)
|
||
; ; UBRRH.URSEL 15 Register Select
|
||
; ; UBRRH.UBRR11 11 USART Baud Rate Register bit 11
|
||
; ; UBRRH.UBRR10 10 USART Baud Rate Register bit 10
|
||
; ; UBRRH.UBRR9 9 USART Baud Rate Register bit 9
|
||
; ; UBRRH.UBRR8 8 USART Baud Rate Register bit 8
|
||
; WDTCR 0x0041 Watchdog Timer Control Register
|
||
; WDTCR.WDCE 4 Watchdog Change Enable
|
||
; WDTCR.WDE 3 Watchdog Enable
|
||
; WDTCR.WDP2 2 Watchdog Timer Prescaler 2
|
||
; WDTCR.WDP1 1 Watchdog Timer Prescaler 1
|
||
; WDTCR.WDP0 0 Watchdog Timer Prescaler 0
|
||
; ASSR 0x0042 Asynchronous Status Register
|
||
; ASSR.AS2 3 Asynchronous Timer/Counter2
|
||
; ASSR.TCN2UB 2 Timer/Counter2 Update Busy
|
||
; ASSR.OCR2UB 1 Output Compare Register 2 Update Busy
|
||
; ASSR.TCR2UB 0 Timer/Counter Control Register 2 Update Busy
|
||
; OCR2 0x0043 Output Compare Register
|
||
; OCR2.OCR2_7 7
|
||
; OCR2.OCR2_6 6
|
||
; OCR2.OCR2_5 5
|
||
; OCR2.OCR2_4 4
|
||
; OCR2.OCR2_3 3
|
||
; OCR2.OCR2_2 2
|
||
; OCR2.OCR2_1 1
|
||
; OCR2.OCR2_0 0
|
||
; TCNT2 0x0044 Timer/Counter Register
|
||
; TCNT2.TCNT2_7 7
|
||
; TCNT2.TCNT2_6 6
|
||
; TCNT2.TCNT2_5 5
|
||
; TCNT2.TCNT2_4 4
|
||
; TCNT2.TCNT2_3 3
|
||
; TCNT2.TCNT2_2 2
|
||
; TCNT2.TCNT2_1 1
|
||
; TCNT2.TCNT2_0 0
|
||
; TCCR2 0x0045 Timer/Counter Control Register
|
||
; TCCR2.FOC2 7 Force Output Compare
|
||
; TCCR2.WGM20 6 Waveform Generation Mode 0
|
||
; TCCR2.COM21 5 Compare Match Output Mode 1
|
||
; TCCR2.COM20 4 Compare Match Output Mode 0
|
||
; TCCR2.WGM21 3 Waveform Generation Mode 1
|
||
; TCCR2.CS22 2 Clock Select 2
|
||
; TCCR2.CS21 1 Clock Select 1
|
||
; TCCR2.CS20 0 Clock Select 0
|
||
; ICR1L 0x0046 Input Capture Register 1 Low
|
||
; ICR1L.ICR1_7 7
|
||
; ICR1L.ICR1_6 6
|
||
; ICR1L.ICR1_5 5
|
||
; ICR1L.ICR1_4 4
|
||
; ICR1L.ICR1_3 3
|
||
; ICR1L.ICR1_2 2
|
||
; ICR1L.ICR1_1 1
|
||
; ICR1L.ICR1_0 0
|
||
; ICR1H 0x0047 Input Capture Register 1 High
|
||
; ICR1H.ICR1_15 15
|
||
; ICR1H.ICR1_14 14
|
||
; ICR1H.ICR1_13 13
|
||
; ICR1H.ICR1_12 12
|
||
; ICR1H.ICR1_11 11
|
||
; ICR1H.ICR1_10 10
|
||
; ICR1H.ICR1_9 9
|
||
; ICR1H.ICR1_8 8
|
||
; OCR1BL 0x0048 Output Compare Register 1 B Low
|
||
; OCR1BL.OCR1B_7 7
|
||
; OCR1BL.OCR1B_6 6
|
||
; OCR1BL.OCR1B_5 5
|
||
; OCR1BL.OCR1B_4 4
|
||
; OCR1BL.OCR1B_3 3
|
||
; OCR1BL.OCR1B_2 2
|
||
; OCR1BL.OCR1B_1 1
|
||
; OCR1BL.OCR1B_0 0
|
||
; OCR1BH 0x0049 Output Compare Register 1 B High
|
||
; OCR1BH.OCR1B_15 15
|
||
; OCR1BH.OCR1B_14 14
|
||
; OCR1BH.OCR1B_13 13
|
||
; OCR1BH.OCR1B_12 12
|
||
; OCR1BH.OCR1B_11 11
|
||
; OCR1BH.OCR1B_10 10
|
||
; OCR1BH.OCR1B_9 9
|
||
; OCR1BH.OCR1B_8 8
|
||
; OCR1AL 0x004A Output Compare Register 1 A Low
|
||
; OCR1AL.OCR1A_7 7
|
||
; OCR1AL.OCR1A_6 6
|
||
; OCR1AL.OCR1A_5 5
|
||
; OCR1AL.OCR1A_4 4
|
||
; OCR1AL.OCR1A_3 3
|
||
; OCR1AL.OCR1A_2 2
|
||
; OCR1AL.OCR1A_1 1
|
||
; OCR1AL.OCR1A_0 0
|
||
; OCR1AH 0x004B Output Compare Register 1 A High
|
||
; OCR1AH.OCR1A_15 15
|
||
; OCR1AH.OCR1A_14 14
|
||
; OCR1AH.OCR1A_13 13
|
||
; OCR1AH.OCR1A_12 12
|
||
; OCR1AH.OCR1A_11 11
|
||
; OCR1AH.OCR1A_10 10
|
||
; OCR1AH.OCR1A_9 9
|
||
; OCR1AH.OCR1A_8 8
|
||
; TCNT1L 0x004C Timer/Counter 1 Low
|
||
; TCNT1L.TCNT1_7 7
|
||
; TCNT1L.TCNT1_6 6
|
||
; TCNT1L.TCNT1_5 5
|
||
; TCNT1L.TCNT1_4 4
|
||
; TCNT1L.TCNT1_3 3
|
||
; TCNT1L.TCNT1_2 2
|
||
; TCNT1L.TCNT1_1 1
|
||
; TCNT1L.TCNT1_0 0
|
||
; TCNT1H 0x004D Timer/Counter 1 High
|
||
; TCNT1H.TCNT1_15 15
|
||
; TCNT1H.TCNT1_14 14
|
||
; TCNT1H.TCNT1_13 13
|
||
; TCNT1H.TCNT1_12 12
|
||
; TCNT1H.TCNT1_11 11
|
||
; TCNT1H.TCNT1_10 10
|
||
; TCNT1H.TCNT1_9 9
|
||
; TCNT1H.TCNT1_8 8
|
||
; TCCR1B 0x004E Timer/Counter1 Control Register B
|
||
; TCCR1B.ICNC1 7 Input Capture Noise Canceler
|
||
; TCCR1B.ICES1 6 Input Capture Edge Select
|
||
; TCCR1B.WGM13 4 Waveform Generation Mode 3
|
||
; TCCR1B.WGM12 3 Waveform Generation Mode 2
|
||
; TCCR1B.CS12 2 Clock Select 2
|
||
; TCCR1B.CS11 1 Clock Select 1
|
||
; TCCR1B.CS10 0 Clock Select 0
|
||
; TCCR1A 0x004F Timer/Counter1 Control Register A
|
||
; TCCR1A.COM1A1 7 Compare Output Mode for Channel A 1
|
||
; TCCR1A.COM1A0 6 Compare Output Mode for Channel A 0
|
||
; TCCR1A.COM1B1 5 Compare Output Mode for Channel B 1
|
||
; TCCR1A.COM1B0 4 Compare Output Mode for Channel B 0
|
||
; TCCR1A.FOC1A 3 Force Output Compare for Channel A
|
||
; TCCR1A.FOC1B 2 Force Output Compare for Channel B
|
||
; TCCR1A.WGM11 1 Waveform Generation Mode 1
|
||
; TCCR1A.WGM10 0 Waveform Generation Mode 0
|
||
; SFIOR 0x0050 Special Function IO Register
|
||
; SFIOR.ADTS2 7 ADC Auto Trigger Source 2
|
||
; SFIOR.ADTS1 6 ADC Auto Trigger Source 1
|
||
; SFIOR.ADTS0 5 ADC Auto Trigger Source 0
|
||
; SFIOR.ADHSM 4 ADC High Speed Mode
|
||
; SFIOR.ACME 3 Analog Comparator Multiplexer Enable
|
||
; SFIOR.PUD 2 Pull-up disable
|
||
; SFIOR.PSR2 1 Prescaler Reset Timer/Counter2
|
||
; SFIOR.PSR10 0 Prescaler Reset Timer/Counter1 and Timer/Counter0
|
||
; OSCCAL 0x0051 Oscillator Calibration Register
|
||
; OSCCAL.CAL7 7 Oscillator Calibration Value 7
|
||
; OSCCAL.CAL6 6 Oscillator Calibration Value 6
|
||
; OSCCAL.CAL5 5 Oscillator Calibration Value 5
|
||
; OSCCAL.CAL4 4 Oscillator Calibration Value 4
|
||
; OSCCAL.CAL3 3 Oscillator Calibration Value 3
|
||
; OSCCAL.CAL2 2 Oscillator Calibration Value 2
|
||
; OSCCAL.CAL1 1 Oscillator Calibration Value 1
|
||
; OSCCAL.CAL0 0 Oscillator Calibration Value 0
|
||
; TCNT0 0x0052 Timer/Counter Register
|
||
; TCNT0.TCNT0_7 7
|
||
; TCNT0.TCNT0_6 6
|
||
; TCNT0.TCNT0_5 5
|
||
; TCNT0.TCNT0_4 4
|
||
; TCNT0.TCNT0_3 3
|
||
; TCNT0.TCNT0_2 2
|
||
; TCNT0.TCNT0_1 1
|
||
; TCNT0.TCNT0_0 0
|
||
; TCCR0 0x0053 Timer/Counter Control Register
|
||
; TCCR0.FOC0 7 Force Output Compare
|
||
; TCCR0.WGM00 6 Waveform Generation Mode 0
|
||
; TCCR0.COM01 5 Compare Match Output Mode 1
|
||
; TCCR0.COM00 4 Compare Match Output Mode 0
|
||
; TCCR0.WGM01 3 Waveform Generation Mode 1
|
||
; TCCR0.CS02 2 Clock Select 2
|
||
; TCCR0.CS01 1 Clock Select 1
|
||
; TCCR0.CS00 0 Clock Select 0
|
||
; MCUCSR 0x0054 MCU Control and Status Register
|
||
; MCUCSR.ISC2 6 Interrupt Sense Control 2
|
||
; MCUCSR.WDRF 3 Watchdog Reset Flag
|
||
; MCUCSR.BORF 2 Brown-out Reset Flag
|
||
; MCUCSR.EXTRF 1 External Reset Flag
|
||
; MCUCSR.PORF 0 Power-on Reset Flag
|
||
; MCUCR 0x0055 MCU Control Register
|
||
; MCUCR.SM2 7 Sleep Mode Select Bit 2
|
||
; MCUCR.SE 6 Sleep Enable
|
||
; MCUCR.SM1 5 Sleep Mode Select Bit 1
|
||
; MCUCR.SM0 4 Sleep Mode Select Bit 0
|
||
; MCUCR.ISC11 3 Interrupt Sense Control 1 Bit 1
|
||
; MCUCR.ISC10 2 Interrupt Sense Control 1 Bit 0
|
||
; MCUCR.ISC01 1 Interrupt Sense Control 0 Bit 1
|
||
; MCUCR.ISC00 0 Interrupt Sense Control 0 Bit 0
|
||
; TWCR 0x0056 TWI Control Register
|
||
; TWCR.TWINT 7 TWI Interrupt Flag
|
||
; TWCR.TWEA 6 TWI Enable Acknowledge Bit
|
||
; TWCR.TWSTA 5 TWI START Condition Bit
|
||
; TWCR.TWSTO 4 TWI STOP Condition Bit
|
||
; TWCR.TWWC 3 TWI Write Collision Flag
|
||
; TWCR.TWEN 2 TWI Enable Bit
|
||
; TWCR.TWIE 0 TWI Interrupt Enable
|
||
; SPMCR 0x0057 Store Program Memory Control Register
|
||
; SPMCR.SPMIE 7 SPM Interrupt Enable
|
||
; SPMCR.RWWSB 6 Read-While-Write Section Busy
|
||
; SPMCR.RWWSRE 4 Read-While-Write Section Read Enable
|
||
; SPMCR.BLBSET 3 Boot Lock Bit Set
|
||
; SPMCR.PGWRT 2 Page Write
|
||
; SPMCR.PGERS 1 Page Erase
|
||
; SPMCR.SPMEN 0 Store Program Memory Enable
|
||
; TIFR 0x0058 Timer/Counter Interrupt Flag Register
|
||
; TIFR.OCF2 7 Output Compare Flag 2
|
||
; TIFR.TOV2 6 Timer/Counter2 Overflow Flag
|
||
; TIFR.ICF1 5 Timer/Counter1, Input Capture Flag
|
||
; TIFR.OCF1A 4 Timer/Counter1, Output Compare A Match Flag
|
||
; TIFR.OCF1B 3 Timer/Counter1, Output Compare B Match Flag
|
||
; TIFR.TOV1 2 Timer/Counter1, Overflow Flag
|
||
; TIFR.OCF0 1 Output Compare Flag 0
|
||
; TIFR.TOV0 0 Timer/Counter0 Overflow Flag
|
||
; TIMSK 0x0059 Timer/Counter Interrupt Mask Register
|
||
; TIMSK.OCIE2 7 Timer/Counter2 Output Compare Match Interrupt Enable
|
||
; TIMSK.TOIE2 6 Timer/Counter2 Overflow Interrupt Enable
|
||
; TIMSK.TICIE1 5 Timer/Counter1, Input Capture Interrupt Enable
|
||
; TIMSK.OCIE1A 4 Timer/Counter1, Output Compare A Match Interrupt Enable
|
||
; TIMSK.OCIE1B 3 Timer/Counter1, Output Compare B Match Interrupt Enable
|
||
; TIMSK.TOIE1 2 Timer/Counter1, Overflow Interrupt Enable
|
||
; TIMSK.OCIE0 1 Timer/Counter0 Output Compare Match Interrupt Enable
|
||
; TIMSK.TOIE0 0 Timer/Counter0 Overflow Interrupt Enable
|
||
; GIFR 0x005A General Interrupt Flag Register
|
||
; GIFR.INTF1 7 External Interrupt Flag 1
|
||
; GIFR.INTF0 6 External Interrupt Flag 0
|
||
; GIFR.INTF2 5 External Interrupt Flag 2
|
||
; GICR 0x005B General Interrupt Control Register
|
||
; GICR.INT1 7 External Interrupt Request 1 Enable
|
||
; GICR.INT0 6 External Interrupt Request 0 Enable
|
||
; GICR.INT2 5 External Interrupt Request 2 Enable
|
||
; GICR.IVSEL 1 Interrupt Vector Select
|
||
; GICR.IVCE 0 Interrupt Vector Change Enable
|
||
; OCR0 0x005C Output Compare Register
|
||
; OCR0.OCR0_7 7
|
||
; OCR0.OCR0_6 6
|
||
; OCR0.OCR0_5 5
|
||
; OCR0.OCR0_4 4
|
||
; OCR0.OCR0_3 3
|
||
; OCR0.OCR0_2 2
|
||
; OCR0.OCR0_1 1
|
||
; OCR0.OCR0_0 0
|
||
; SPL 0x005D Stack Pointer Low
|
||
; SPL.SP7 7
|
||
; SPL.SP6 6
|
||
; SPL.SP5 5
|
||
; SPL.SP4 4
|
||
; SPL.SP3 3
|
||
; SPL.SP2 2
|
||
; SPL.SP1 1
|
||
; SPL.SP0 0
|
||
; SPH 0x005E Stack Pointer High
|
||
; SPH.SP10 10
|
||
; SPH.SP9 9
|
||
; SPH.SP8 8
|
||
; SREG 0x005F Status Register
|
||
; SREG.I 7 Global Interrupt Enable
|
||
; SREG.T 6 Bit Copy Storage
|
||
; SREG.H 5 Half Carry Flag
|
||
; SREG.S 4 Sign Bit
|
||
; SREG.V 3 Two's Complement Overflow Flag
|
||
; SREG.N 2 Negative Flag
|
||
; SREG.Z 1 Zero Flag
|
||
; SREG.C 0 Carry Flag
|
||
|
||
|
||
.ATmega8_L
|
||
SUBARCH=4
|
||
; doc2486.pdf
|
||
;
|
||
|
||
RAM=1024
|
||
ROM=8192
|
||
EEPROM=512
|
||
|
||
; MEMORY MAP
|
||
area DATA FSR 0x0000:0x0060
|
||
area DATA I_SRAM 0x0060:0x0460 Internal SRAM
|
||
|
||
|
||
; Interrupt and reset vector assignments
|
||
entry __RESET 0x0000 External Pin, Power-on Reset, Brown-out
|
||
entry INT0_ 0x0001 External Interrupt Request 0
|
||
entry INT1_ 0x0002 External Interrupt Request 1
|
||
entry TIMER2_COMP 0x0003 Timer/Counter2 Compare Match
|
||
entry TIMER2_OVF 0x0004 Timer/Counter2 Overflow
|
||
entry TIMER1_CAPT 0x0005 Timer/Counter1 Capture Event
|
||
entry TIMER1_COMPA 0x0006 Timer/Counter1 Compare Match A
|
||
entry TIMER1_COMPB 0x0007 Timer/Counter1 Compare Match B
|
||
entry TIMER1_OVF 0x0008 Timer/Counter1 Overflow
|
||
entry TIMER0_OVF 0x0009 Timer/Counter0 Overflow
|
||
entry SPI_STC 0x000A Serial Transfer Complete
|
||
entry USART_RXC 0x000B USART, Rx Complete
|
||
entry USART_UDRE 0x000C USART Data Register Empty
|
||
entry USART_TXC 0x000D USART, Tx Complete
|
||
entry ADC_ 0x000E ADC Conversion Complete
|
||
entry EE_RDY 0x000F EEPROM Ready
|
||
entry ANA_COMP 0x0010 Analog Comparator
|
||
entry TWI_ 0x0011 Two-wire Serial Interface
|
||
entry SPM_RDY 0x0012 Store Program Memory Ready
|
||
|
||
|
||
; INPUT/OUTPUT PORTS
|
||
TWBR 0x0000 Two-wire Serial Interface Bit Rate Register
|
||
TWBR.TWBR7 7 TWI Bit Rate Register bit 7
|
||
TWBR.TWBR6 6 TWI Bit Rate Register bit 6
|
||
TWBR.TWBR5 5 TWI Bit Rate Register bit 5
|
||
TWBR.TWBR4 4 TWI Bit Rate Register bit 4
|
||
TWBR.TWBR3 3 TWI Bit Rate Register bit 3
|
||
TWBR.TWBR2 2 TWI Bit Rate Register bit 2
|
||
TWBR.TWBR1 1 TWI Bit Rate Register bit 1
|
||
TWBR.TWBR0 0 TWI Bit Rate Register bit 0
|
||
TWSR 0x0001 TWI Status Register
|
||
TWSR.TWS7 7 TWI Status 7
|
||
TWSR.TWS6 6 TWI Status 6
|
||
TWSR.TWS5 5 TWI Status 5
|
||
TWSR.TWS4 4 TWI Status 4
|
||
TWSR.TWS3 3 TWI Status 3
|
||
TWSR.TWS1 1 TWI Status 1
|
||
TWSR.TWS0 0 TWI Status 0
|
||
TWAR 0x0002 TWI (Slave) Address Register
|
||
TWAR.TWA6 7 TWI (Slave) Address Register bit 6
|
||
TWAR.TWA5 6 TWI (Slave) Address Register bit 5
|
||
TWAR.TWA4 5 TWI (Slave) Address Register bit 4
|
||
TWAR.TWA3 4 TWI (Slave) Address Register bit 3
|
||
TWAR.TWA2 3 TWI (Slave) Address Register bit 2
|
||
TWAR.TWA1 2 TWI (Slave) Address Register bit 1
|
||
TWAR.TWA0 1 TWI (Slave) Address Register bit 0
|
||
TWAR.TWGCE 0 TWI General Call Recognition Enable Bit
|
||
TWDR 0x0003 TWI Data Register
|
||
TWDR.TWD7 7 TWI Data Register bit 7
|
||
TWDR.TWD6 6 TWI Data Register bit 6
|
||
TWDR.TWD5 5 TWI Data Register bit 5
|
||
TWDR.TWD4 4 TWI Data Register bit 4
|
||
TWDR.TWD3 3 TWI Data Register bit 3
|
||
TWDR.TWD2 2 TWI Data Register bit 2
|
||
TWDR.TWD1 1 TWI Data Register bit 1
|
||
TWDR.TWD0 0 TWI Data Register bit 0
|
||
ADCL 0x0004 ADC Data Register Low (ADLAR = 0)
|
||
ADCL.ADC7 7 ADC Conversion Result 7
|
||
ADCL.ADC6 6 ADC Conversion Result 6
|
||
ADCL.ADC5 5 ADC Conversion Result 5
|
||
ADCL.ADC4 4 ADC Conversion Result 4
|
||
ADCL.ADC3 3 ADC Conversion Result 3
|
||
ADCL.ADC2 2 ADC Conversion Result 2
|
||
ADCL.ADC1 1 ADC Conversion Result 1
|
||
ADCL.ADC0 0 ADC Conversion Result 0
|
||
ADCH 0x0005 ADC Data Register High (ADLAR = 0)
|
||
ADCH.ADC9 9 ADC Conversion Result 9
|
||
ADCH.ADC8 8 ADC Conversion Result 8
|
||
; ADCL 0x0004 ADC Data Register Low (ADLAR = 1)
|
||
; ADCL.ADC1 7 ADC Conversion Result 1
|
||
; ADCL.ADC0 6 ADC Conversion Result 0
|
||
; ADCH 0x0005 ADC Data Register High (ADLAR = 1)
|
||
; ADCH.ADC9 15 ADC Conversion Result 9
|
||
; ADCH.ADC8 14 ADC Conversion Result 8
|
||
; ADCH.ADC7 13 ADC Conversion Result 7
|
||
; ADCH.ADC6 12 ADC Conversion Result 6
|
||
; ADCH.ADC5 11 ADC Conversion Result 5
|
||
; ADCH.ADC4 10 ADC Conversion Result 4
|
||
; ADCH.ADC3 9 ADC Conversion Result 3
|
||
; ADCH.ADC2 8 ADC Conversion Result 2
|
||
ADCSRA 0x0006 ADC Control and Status Register A
|
||
ADCSRA.ADEN 7 ADC Enable
|
||
ADCSRA.ADSC 6 ADC Start Conversion
|
||
ADCSRA.ADFR 5 ADC Free Running Select
|
||
ADCSRA.ADIF 4 ADC Interrupt Flag
|
||
ADCSRA.ADIE 3 ADC Interrupt Enable
|
||
ADCSRA.ADPS2 2 ADC Prescaler Select Bit 2
|
||
ADCSRA.ADPS1 1 ADC Prescaler Select Bit 1
|
||
ADCSRA.ADPS0 0 ADC Prescaler Select Bit 0
|
||
ADMUX 0x0007 ADC Multiplexer Selection Register
|
||
ADMUX.REFS1 7 Reference Selection Bit 1
|
||
ADMUX.REFS0 6 Reference Selection Bit 0
|
||
ADMUX.ADLAR 5 ADC Left Adjust Result
|
||
ADMUX.MUX3 3 Analog Channel Selection Bit 3
|
||
ADMUX.MUX2 2 Analog Channel Selection Bit 2
|
||
ADMUX.MUX1 1 Analog Channel Selection Bit 1
|
||
ADMUX.MUX0 0 Analog Channel Selection Bit 0
|
||
ACSR 0x0008 Analog Comparator Control and Status Register
|
||
ACSR.ACD 7 Analog Comparator Disable
|
||
ACSR.ACBG 6 Analog Comparator Bandgap Select
|
||
ACSR.ACO 5 Analog Comparator Output
|
||
ACSR.ACI 4 Analog Comparator Interrupt Flag
|
||
ACSR.ACIE 3 Analog Comparator Interrupt Enable
|
||
ACSR.ACIC 2 Analog Comparator Input Capture Enable
|
||
ACSR.ACIS1 1 Analog Comparator Interrupt Mode Select 1
|
||
ACSR.ACIS0 0 Analog Comparator Interrupt Mode Select 0
|
||
UBRRL 0x0009 USART Baud Rate Register Low
|
||
UBRRL.UBRR7 7 USART Baud Rate Register bit 7
|
||
UBRRL.UBRR6 6 USART Baud Rate Register bit 6
|
||
UBRRL.UBRR5 5 USART Baud Rate Register bit 5
|
||
UBRRL.UBRR4 4 USART Baud Rate Register bit 4
|
||
UBRRL.UBRR3 3 USART Baud Rate Register bit 3
|
||
UBRRL.UBRR2 2 USART Baud Rate Register bit 2
|
||
UBRRL.UBRR1 1 USART Baud Rate Register bit 1
|
||
UBRRL.UBRR0 0 USART Baud Rate Register bit 0
|
||
UCSRB 0x000A USART Control and Status Register B
|
||
UCSRB.RXCIE 7 RX Complete Interrupt Enable
|
||
UCSRB.TXCIE 6 TX Complete Interrupt Enable
|
||
UCSRB.UDRIE 5 USART Data Register Empty Interrupt Enable
|
||
UCSRB.RXEN 4 Receiver Enable
|
||
UCSRB.TXEN 3 Transmitter Enable
|
||
UCSRB.UCSZ2 2 Character Size
|
||
UCSRB.RXB8 1 Receive Data Bit 8
|
||
UCSRB.TXB8 0 Transmit Data Bit 8
|
||
UCSRA 0x000B USART Control and Status Register A
|
||
UCSRA.RXC 7 USART Receive Complete
|
||
UCSRA.TXC 6 USART Transmit Complete
|
||
UCSRA.UDRE 5 USART Data Register Empty
|
||
UCSRA.FE 4 Frame Error
|
||
UCSRA.DOR 3 Data OverRun
|
||
UCSRA.PE 2 Parity Error
|
||
UCSRA.U2X 1 Double the USART transmission speed
|
||
UCSRA.MPCM 0 Multi-processor Communication Mode
|
||
UDR 0x000C USART I/O Data Register
|
||
SPCR 0x000D SPI Control Register
|
||
SPCR.SPIE 7 SPI Interrupt Enable
|
||
SPCR.SPE 6 SPI Enable
|
||
SPCR.DORD 5 Data Order
|
||
SPCR.MSTR 4 Master/Slave Select
|
||
SPCR.CPOL 3 Clock Polarity
|
||
SPCR.CPHA 2 Clock Phase
|
||
SPCR.SPR1 1 SPI Clock Rate Select 1
|
||
SPCR.SPR0 0 SPI Clock Rate Select 0
|
||
SPSR 0x000E SPI Status Register
|
||
SPSR.SPIF 7 SPI Interrupt Flag
|
||
SPSR.WCOL 6 Write COLlision flag
|
||
SPSR.SPI2X 0 Double SPI Speed Bit
|
||
SPDR 0x000F SPI Data Register
|
||
PIND 0x0010 Port D Input Pins Address
|
||
PIND.PIND7 7
|
||
PIND.PIND6 6
|
||
PIND.PIND5 5
|
||
PIND.PIND4 4
|
||
PIND.PIND3 3
|
||
PIND.PIND2 2
|
||
PIND.PIND1 1
|
||
PIND.PIND0 0
|
||
DDRD 0x0011 Port D Data Direction Register
|
||
DDRD.DDD7 7 Port D Data Direction Register bit 7
|
||
DDRD.DDD6 6 Port D Data Direction Register bit 6
|
||
DDRD.DDD5 5 Port D Data Direction Register bit 5
|
||
DDRD.DDD4 4 Port D Data Direction Register bit 4
|
||
DDRD.DDD3 3 Port D Data Direction Register bit 3
|
||
DDRD.DDD2 2 Port D Data Direction Register bit 2
|
||
DDRD.DDD1 1 Port D Data Direction Register bit 1
|
||
DDRD.DDD0 0 Port D Data Direction Register bit 0
|
||
PORTD 0x0012 Port D Data Register
|
||
PORTD.PORTD7 7 Port D Data Register bit 7
|
||
PORTD.PORTD6 6 Port D Data Register bit 6
|
||
PORTD.PORTD5 5 Port D Data Register bit 5
|
||
PORTD.PORTD4 4 Port D Data Register bit 4
|
||
PORTD.PORTD3 3 Port D Data Register bit 3
|
||
PORTD.PORTD2 2 Port D Data Register bit 2
|
||
PORTD.PORTD1 1 Port D Data Register bit 1
|
||
PORTD.PORTD0 0 Port D Data Register bit 0
|
||
PINC 0x0013 Port C Input Pins Address
|
||
PINC.PINC6 6
|
||
PINC.PINC5 5
|
||
PINC.PINC4 4
|
||
PINC.PINC3 3
|
||
PINC.PINC2 2
|
||
PINC.PINC1 1
|
||
PINC.PINC0 0
|
||
DDRC 0x0014 Port C Data Direction Register
|
||
DDRC.DDC6 6 Port C Data Direction Register bit 6
|
||
DDRC.DDC5 5 Port C Data Direction Register bit 5
|
||
DDRC.DDC4 4 Port C Data Direction Register bit 4
|
||
DDRC.DDC3 3 Port C Data Direction Register bit 3
|
||
DDRC.DDC2 2 Port C Data Direction Register bit 2
|
||
DDRC.DDC1 1 Port C Data Direction Register bit 1
|
||
DDRC.DDC0 0 Port C Data Direction Register bit 0
|
||
PORTC 0x0015 Port C Data Register
|
||
PORTC.PORTC6 6 Port C Data Register bit 6
|
||
PORTC.PORTC5 5 Port C Data Register bit 5
|
||
PORTC.PORTC4 4 Port C Data Register bit 4
|
||
PORTC.PORTC3 3 Port C Data Register bit 3
|
||
PORTC.PORTC2 2 Port C Data Register bit 2
|
||
PORTC.PORTC1 1 Port C Data Register bit 1
|
||
PORTC.PORTC0 0 Port C Data Register bit 0
|
||
PINB 0x0016 Port B Input Pins Address
|
||
PINB.PINB7 7
|
||
PINB.PINB6 6
|
||
PINB.PINB5 5
|
||
PINB.PINB4 4
|
||
PINB.PINB3 3
|
||
PINB.PINB2 2
|
||
PINB.PINB1 1
|
||
PINB.PINB0 0
|
||
DDRB 0x0017 Port B Data Direction Register
|
||
DDRB.DDB7 7 Port B Data Direction Register bit 7
|
||
DDRB.DDB6 6 Port B Data Direction Register bit 6
|
||
DDRB.DDB5 5 Port B Data Direction Register bit 5
|
||
DDRB.DDB4 4 Port B Data Direction Register bit 4
|
||
DDRB.DDB3 3 Port B Data Direction Register bit 3
|
||
DDRB.DDB2 2 Port B Data Direction Register bit 2
|
||
DDRB.DDB1 1 Port B Data Direction Register bit 1
|
||
DDRB.DDB0 0 Port B Data Direction Register bit 0
|
||
PORTB 0x0018 Port B Data Register
|
||
PORTB.PORTB7 7 Port B Data Register bit 7
|
||
PORTB.PORTB6 6 Port B Data Register bit 6
|
||
PORTB.PORTB5 5 Port B Data Register bit 5
|
||
PORTB.PORTB4 4 Port B Data Register bit 4
|
||
PORTB.PORTB3 3 Port B Data Register bit 3
|
||
PORTB.PORTB2 2 Port B Data Register bit 2
|
||
PORTB.PORTB1 1 Port B Data Register bit 1
|
||
PORTB.PORTB0 0 Port B Data Register bit 0
|
||
RESERVED0019 0x0019 RESERVED
|
||
RESERVED001A 0x001A RESERVED
|
||
RESERVED001B 0x001B RESERVED
|
||
EECR 0x001C EEPROM Control Register
|
||
EECR.EERIE 3 EEPROM Ready Interrupt Enable
|
||
EECR.EEMWE 2 EEPROM Master Write Enable
|
||
EECR.EEWE 1 EEPROM Write Enable
|
||
EECR.EERE 0 EEPROM Read Enable
|
||
EEDR 0x001D EEPROM Data Register
|
||
EEDR.EEDR7 7 EEPROM Data 7
|
||
EEDR.EEDR6 6 EEPROM Data 6
|
||
EEDR.EEDR5 5 EEPROM Data 5
|
||
EEDR.EEDR4 4 EEPROM Data 4
|
||
EEDR.EEDR3 3 EEPROM Data 3
|
||
EEDR.EEDR2 2 EEPROM Data 2
|
||
EEDR.EEDR1 1 EEPROM Data 1
|
||
EEDR.EEDR0 0 EEPROM Data 0
|
||
EEARL 0x001E EEPROM Address Register Low
|
||
EEARL.EEAR7 7 EEPROM Addres 7
|
||
EEARL.EEAR6 6 EEPROM Addres 6
|
||
EEARL.EEAR5 5 EEPROM Addres 5
|
||
EEARL.EEAR4 4 EEPROM Addres 4
|
||
EEARL.EEAR3 3 EEPROM Addres 3
|
||
EEARL.EEAR2 2 EEPROM Addres 2
|
||
EEARL.EEAR1 1 EEPROM Addres 1
|
||
EEARL.EEAR0 0 EEPROM Addres 0
|
||
EEARH 0x001F EEPROM Address Register High
|
||
EEARH.EEAR8 8 EEPROM Addres 8
|
||
UCSRC 0x0020 USART Control and Status Register (page 148)
|
||
UCSRC.URSEL 7 Register Select
|
||
UCSRC.UMSEL 6 USART Mode Select
|
||
UCSRC.UPM1 5 Parity Mode 1
|
||
UCSRC.UPM0 4 Parity Mode 0
|
||
UCSRC.USBS 3 Stop Bit Select
|
||
UCSRC.UCSZ1 2 Character Size 1
|
||
UCSRC.UCSZ0 1 Character Size 0
|
||
UCSRC.UCPOL 0 Clock Polarity
|
||
; UBRRH 0x0020 USART Baud Rate Register High (page 148)
|
||
; UBRRH.URSEL 15 Register Select
|
||
; UBRRH.UBRR11 11 USART Baud Rate Register bit 11
|
||
; UBRRH.UBRR10 10 USART Baud Rate Register bit 10
|
||
; UBRRH.UBRR9 9 USART Baud Rate Register bit 9
|
||
; UBRRH.UBRR8 8 USART Baud Rate Register bit 8
|
||
WDTCR 0x0021 Watchdog Timer Control Register
|
||
WDTCR.WDCE 4 Watchdog Change Enable
|
||
WDTCR.WDE 3 Watchdog Enable
|
||
WDTCR.WDP2 2 Watchdog Timer Prescaler 2
|
||
WDTCR.WDP1 1 Watchdog Timer Prescaler 1
|
||
WDTCR.WDP0 0 Watchdog Timer Prescaler 0
|
||
ASSR 0x0022 Asynchronous Status Register
|
||
ASSR.AS2 3 Asynchronous Timer/Counter2
|
||
ASSR.TCN2UB 2 Timer/Counter2 Update Busy
|
||
ASSR.OCR2UB 1 Output Compare Register2 Update Busy
|
||
ASSR.TCR2UB 0 Timer/Counter Control Register2 Update Busy
|
||
OCR2 0x0023 Output Compare Register
|
||
OCR2.OCR2_7 7
|
||
OCR2.OCR2_6 6
|
||
OCR2.OCR2_5 5
|
||
OCR2.OCR2_4 4
|
||
OCR2.OCR2_3 3
|
||
OCR2.OCR2_2 2
|
||
OCR2.OCR2_1 1
|
||
OCR2.OCR2_0 0
|
||
TCNT2 0x0024 Timer/Counter Register
|
||
TCNT2.TCNT2_7 7
|
||
TCNT2.TCNT2_6 6
|
||
TCNT2.TCNT2_5 5
|
||
TCNT2.TCNT2_4 4
|
||
TCNT2.TCNT2_3 3
|
||
TCNT2.TCNT2_2 2
|
||
TCNT2.TCNT2_1 1
|
||
TCNT2.TCNT2_0 0
|
||
TCCR2 0x0025 Timer/Counter Control Register
|
||
TCCR2.FOC2 7 Force Output Compare
|
||
TCCR2.WGM20 6 Waveform Generation Mode 0
|
||
TCCR2.COM21 5 Compare Match Output Mode 1
|
||
TCCR2.COM20 4 Compare Match Output Mode 0
|
||
TCCR2.WGM21 3 Waveform Generation Mode 1
|
||
TCCR2.CS22 2 Clock Select 2
|
||
TCCR2.CS21 1 Clock Select 1
|
||
TCCR2.CS20 0 Clock Select 0
|
||
ICR1L 0x0026 Input Capture Register 1 Low
|
||
ICR1L.ICR1_7 7
|
||
ICR1L.ICR1_6 6
|
||
ICR1L.ICR1_5 5
|
||
ICR1L.ICR1_4 4
|
||
ICR1L.ICR1_3 3
|
||
ICR1L.ICR1_2 2
|
||
ICR1L.ICR1_1 1
|
||
ICR1L.ICR1_0 0
|
||
ICR1H 0x0027 Input Capture Register 1 High
|
||
ICR1H.ICR1_15 15
|
||
ICR1H.ICR1_14 14
|
||
ICR1H.ICR1_13 13
|
||
ICR1H.ICR1_12 12
|
||
ICR1H.ICR1_11 11
|
||
ICR1H.ICR1_10 10
|
||
ICR1H.ICR1_9 9
|
||
ICR1H.ICR1_8 8
|
||
OCR1BL 0x0028 Output Compare Register 1 B Low
|
||
OCR1BL.OCR1B_7 7
|
||
OCR1BL.OCR1B_6 6
|
||
OCR1BL.OCR1B_5 5
|
||
OCR1BL.OCR1B_4 4
|
||
OCR1BL.OCR1B_3 3
|
||
OCR1BL.OCR1B_2 2
|
||
OCR1BL.OCR1B_1 1
|
||
OCR1BL.OCR1B_0 0
|
||
OCR1BH 0x0029 Output Compare Register 1 B High
|
||
OCR1BH.OCR1B_15 15
|
||
OCR1BH.OCR1B_14 14
|
||
OCR1BH.OCR1B_13 13
|
||
OCR1BH.OCR1B_12 12
|
||
OCR1BH.OCR1B_11 11
|
||
OCR1BH.OCR1B_10 10
|
||
OCR1BH.OCR1B_9 9
|
||
OCR1BH.OCR1B_8 8
|
||
OCR1AL 0x002A Output Compare Register 1 A Low
|
||
OCR1AL.OCR1A_7 7
|
||
OCR1AL.OCR1A_6 6
|
||
OCR1AL.OCR1A_5 5
|
||
OCR1AL.OCR1A_4 4
|
||
OCR1AL.OCR1A_3 3
|
||
OCR1AL.OCR1A_2 2
|
||
OCR1AL.OCR1A_1 1
|
||
OCR1AL.OCR1A_0 0
|
||
OCR1AH 0x002B Output Compare Register 1 A High
|
||
OCR1AH.OCR1A_15 15
|
||
OCR1AH.OCR1A_14 14
|
||
OCR1AH.OCR1A_13 13
|
||
OCR1AH.OCR1A_12 12
|
||
OCR1AH.OCR1A_11 11
|
||
OCR1AH.OCR1A_10 10
|
||
OCR1AH.OCR1A_9 9
|
||
OCR1AH.OCR1A_8 8
|
||
TCNT1L 0x002C Timer/Counter 1 Low
|
||
TCNT1L.TCNT1_7 7
|
||
TCNT1L.TCNT1_6 6
|
||
TCNT1L.TCNT1_5 5
|
||
TCNT1L.TCNT1_4 4
|
||
TCNT1L.TCNT1_3 3
|
||
TCNT1L.TCNT1_2 2
|
||
TCNT1L.TCNT1_1 1
|
||
TCNT1L.TCNT1_0 0
|
||
TCNT1H 0x002D Timer/Counter 1 High
|
||
TCNT1H.TCNT1_15 15
|
||
TCNT1H.TCNT1_14 14
|
||
TCNT1H.TCNT1_13 13
|
||
TCNT1H.TCNT1_12 12
|
||
TCNT1H.TCNT1_11 11
|
||
TCNT1H.TCNT1_10 10
|
||
TCNT1H.TCNT1_9 9
|
||
TCNT1H.TCNT1_8 8
|
||
TCCR1B 0x002E Timer/Counter 1 Control Register B
|
||
TCCR1B.ICNC1 7 Input Capture Noise Canceler
|
||
TCCR1B.ICES1 6 Input Capture Edge Select
|
||
TCCR1B.WGM13 4 Waveform Generation Mode 3
|
||
TCCR1B.WGM12 3 Waveform Generation Mode 2
|
||
TCCR1B.CS12 2 Clock Select 2
|
||
TCCR1B.CS11 1 Clock Select 1
|
||
TCCR1B.CS10 0 Clock Select 0
|
||
TCCR1A 0x002F Timer/Counter 1 Control Register A
|
||
TCCR1A.COM1A1 7 Compare Output Mode for channel A 1
|
||
TCCR1A.COM1A0 6 Compare Output Mode for channel A 0
|
||
TCCR1A.COM1B1 5 Compare Output Mode for channel B 1
|
||
TCCR1A.COM1B0 4 Compare Output Mode for channel B 0
|
||
TCCR1A.FOC1A 3 Force Output Compare for channel A
|
||
TCCR1A.FOC1B 2 Force Output Compare for channel B
|
||
TCCR1A.WGM11 1 Waveform Generation Mode 1
|
||
TCCR1A.WGM10 0 Waveform Generation Mode 0
|
||
SFIOR 0x0030 Special Function IO Register
|
||
SFIOR.ADHSM 4 ADC High Speed Mode
|
||
SFIOR.ACME 3 Analog Comparator Multiplexer Enable
|
||
SFIOR.PUD 2 Pull-up Disable
|
||
SFIOR.PSR2 1 Prescaler Reset Timer/Counter2
|
||
SFIOR.PSR10 0 Prescaler Reset Timer/Counter1 and Timer/Counter0
|
||
OSCCAL 0x0031 Oscillator Calibration Register
|
||
OSCCAL.CAL7 7 Oscillator Calibration Value 7
|
||
OSCCAL.CAL6 6 Oscillator Calibration Value 6
|
||
OSCCAL.CAL5 5 Oscillator Calibration Value 5
|
||
OSCCAL.CAL4 4 Oscillator Calibration Value 4
|
||
OSCCAL.CAL3 3 Oscillator Calibration Value 3
|
||
OSCCAL.CAL2 2 Oscillator Calibration Value 2
|
||
OSCCAL.CAL1 1 Oscillator Calibration Value 1
|
||
OSCCAL.CAL0 0 Oscillator Calibration Value 0
|
||
TCNT0 0x0032 Timer/Counter Register
|
||
TCNT0.TCNT0_7 7
|
||
TCNT0.TCNT0_6 6
|
||
TCNT0.TCNT0_5 5
|
||
TCNT0.TCNT0_4 4
|
||
TCNT0.TCNT0_3 3
|
||
TCNT0.TCNT0_2 2
|
||
TCNT0.TCNT0_1 1
|
||
TCNT0.TCNT0_0 0
|
||
TCCR0 0x0033 Timer/Counter Control Register
|
||
TCCR0.CS02 2 Clock Select 2
|
||
TCCR0.CS01 1 Clock Select 1
|
||
TCCR0.CS00 0 Clock Select 0
|
||
MCUCSR 0x0034 MCU Control and Status Register
|
||
MCUCSR.WDRF 3 Watchdog Reset Flag
|
||
MCUCSR.BORF 2 Brown-out Reset Flag
|
||
MCUCSR.EXTRF 1 External Reset Flag
|
||
MCUCSR.PORF 0 Power-on Reset Flag
|
||
MCUCR 0x0035 MCU Control Register
|
||
MCUCR.SE 7 Sleep Enable
|
||
MCUCR.SM2 6 Sleep Mode Select Bit 2
|
||
MCUCR.SM1 5 Sleep Mode Select Bit 1
|
||
MCUCR.SM0 4 Sleep Mode Select Bit 0
|
||
MCUCR.ISC11 3 Interrupt Sense Control 1 Bit 1
|
||
MCUCR.ISC10 2 Interrupt Sense Control 1 Bit 0
|
||
MCUCR.ISC01 1 Interrupt Sense Control 0 Bit 1
|
||
MCUCR.ISC00 0 Interrupt Sense Control 0 Bit 0
|
||
TWCR 0x0036 TWI Control Register
|
||
TWCR.TWINT 7 TWI Interrupt Flag
|
||
TWCR.TWEA 6 TWI Enable Acknowledge Bit
|
||
TWCR.TWSTA 5 TWI START Condition Bit
|
||
TWCR.TWSTO 4 TWI STOP Condition Bit
|
||
TWCR.TWWC 3 TWI Write Collision Flag
|
||
TWCR.TWEN 2 TWI Enable Bit
|
||
TWCR.TWIE 0 TWI Interrupt Enable
|
||
SPMCR 0x0037 Store Program Memory Control Register
|
||
SPMCR.SPMIE 7 SPM Interrupt Enable
|
||
SPMCR.RWWSB 6 Read-While-Write Section Busy
|
||
SPMCR.RWWSRE 4 Read-While-Write Section Read Enable
|
||
SPMCR.BLBSET 3 Boot Lock Bit Set
|
||
SPMCR.PGWRT 2 Page Write
|
||
SPMCR.PGERS 1 Page Erase
|
||
SPMCR.SPMEN 0 Store Program Memory Enable
|
||
TIFR 0x0038 Timer/Counter Interrupt Flag Register
|
||
TIFR.OCF2 7 Output Compare Flag 2
|
||
TIFR.TOV2 6 Timer/Counter2 Overflow Flag
|
||
TIFR.ICF1 5 Timer/Counter1, Input Capture Flag
|
||
TIFR.OCF1A 4 Timer/Counter1, Output Compare A Match Flag
|
||
TIFR.OCF1B 3 Timer/Counter1, Output Compare B Match Flag
|
||
TIFR.TOV1 2 Timer/Counter1, Overflow Flag
|
||
TIFR.TOV0 0 Timer/Counter0 Overflow Flag
|
||
TIMSK 0x0039 Timer/Counter Interrupt Mask Register
|
||
TIMSK.OCIE2 7 Timer/Counter2 Output Compare Match Interrupt Enable
|
||
TIMSK.TOIE2 6 Timer/Counter2 Overflow Interrupt Enable
|
||
TIMSK.TICIE1 5 Timer/Counter1, Input Capture Interrupt Enable
|
||
TIMSK.OCIE1A 4 Timer/Counter1, Output Compare A Match Interrupt Enable
|
||
TIMSK.OCIE1B 3 Timer/Counter1, Output Compare B Match Interrupt Enable
|
||
TIMSK.TOIE1 2 Timer/Counter1, Overflow Interrupt Enable
|
||
TIMSK.TOIE0 0 Timer/Counter0 Overflow Interrupt Enable
|
||
GIFR 0x003A General Interrupt Flag Register
|
||
GIFR.INTF1 7 External Interrupt Flag 1
|
||
GIFR.INTF0 6 External Interrupt Flag 0
|
||
GICR 0x003B General Interrupt Control Register
|
||
GICR.INT1 7 External Interrupt Request 1 Enable
|
||
GICR.INT0 6 External Interrupt Request 0 Enable
|
||
GICR.IVSEL 1 Interrupt Vector Select
|
||
GICR.IVCE 0 Interrupt Vector Change Enable
|
||
RESERVED003C 0x003C RESERVED
|
||
SPL 0x003D Stack Pointer Low
|
||
SPL.SP7 7
|
||
SPL.SP6 6
|
||
SPL.SP5 5
|
||
SPL.SP4 4
|
||
SPL.SP3 3
|
||
SPL.SP2 2
|
||
SPL.SP1 1
|
||
SPL.SP0 0
|
||
SPH 0x003E Stack Pointer High
|
||
SPH.SP10 10
|
||
SPH.SP9 9
|
||
SPH.SP8 8
|
||
SREG 0x003F Status Register
|
||
SREG.I 7 Global Interrupt Enable
|
||
SREG.T 6 Bit Copy Storage
|
||
SREG.H 5 Half Carry Flag
|
||
SREG.S 4 Sign Bit
|
||
SREG.V 3 Two's Complement Overflow Flag
|
||
SREG.N 2 Negative Flag
|
||
SREG.Z 1 Zero Flag
|
||
SREG.C 0 Carry Flag
|
||
|
||
; TWBR 0x0020 Two-wire Serial Interface Bit Rate Register
|
||
; TWBR.TWBR7 7 TWI Bit Rate Register bit 7
|
||
; TWBR.TWBR6 6 TWI Bit Rate Register bit 6
|
||
; TWBR.TWBR5 5 TWI Bit Rate Register bit 5
|
||
; TWBR.TWBR4 4 TWI Bit Rate Register bit 4
|
||
; TWBR.TWBR3 3 TWI Bit Rate Register bit 3
|
||
; TWBR.TWBR2 2 TWI Bit Rate Register bit 2
|
||
; TWBR.TWBR1 1 TWI Bit Rate Register bit 1
|
||
; TWBR.TWBR0 0 TWI Bit Rate Register bit 0
|
||
; TWSR 0x0021 TWI Status Register
|
||
; TWSR.TWS7 7 TWI Status 7
|
||
; TWSR.TWS6 6 TWI Status 6
|
||
; TWSR.TWS5 5 TWI Status 5
|
||
; TWSR.TWS4 4 TWI Status 4
|
||
; TWSR.TWS3 3 TWI Status 3
|
||
; TWSR.TWS1 1 TWI Status 1
|
||
; TWSR.TWS0 0 TWI Status 0
|
||
; TWAR 0x0022 TWI (Slave) Address Register
|
||
; TWAR.TWA6 7 TWI (Slave) Address Register bit 6
|
||
; TWAR.TWA5 6 TWI (Slave) Address Register bit 5
|
||
; TWAR.TWA4 5 TWI (Slave) Address Register bit 4
|
||
; TWAR.TWA3 4 TWI (Slave) Address Register bit 3
|
||
; TWAR.TWA2 3 TWI (Slave) Address Register bit 2
|
||
; TWAR.TWA1 2 TWI (Slave) Address Register bit 1
|
||
; TWAR.TWA0 1 TWI (Slave) Address Register bit 0
|
||
; TWAR.TWGCE 0 TWI General Call Recognition Enable Bit
|
||
; TWDR 0x0023 TWI Data Register
|
||
; TWDR.TWD7 7 TWI Data Register bit 7
|
||
; TWDR.TWD6 6 TWI Data Register bit 6
|
||
; TWDR.TWD5 5 TWI Data Register bit 5
|
||
; TWDR.TWD4 4 TWI Data Register bit 4
|
||
; TWDR.TWD3 3 TWI Data Register bit 3
|
||
; TWDR.TWD2 2 TWI Data Register bit 2
|
||
; TWDR.TWD1 1 TWI Data Register bit 1
|
||
; TWDR.TWD0 0 TWI Data Register bit 0
|
||
; ADCL 0x0024 ADC Data Register Low (ADLAR = 0)
|
||
; ADCL.ADC7 7 ADC Conversion Result 7
|
||
; ADCL.ADC6 6 ADC Conversion Result 6
|
||
; ADCL.ADC5 5 ADC Conversion Result 5
|
||
; ADCL.ADC4 4 ADC Conversion Result 4
|
||
; ADCL.ADC3 3 ADC Conversion Result 3
|
||
; ADCL.ADC2 2 ADC Conversion Result 2
|
||
; ADCL.ADC1 1 ADC Conversion Result 1
|
||
; ADCL.ADC0 0 ADC Conversion Result 0
|
||
; ADCH 0x0025 ADC Data Register High (ADLAR = 0)
|
||
; ADCH.ADC9 9 ADC Conversion Result 9
|
||
; ADCH.ADC8 8 ADC Conversion Result 8
|
||
; ; ADCL 0x0024 ADC Data Register Low (ADLAR = 1)
|
||
; ; ADCL.ADC1 7 ADC Conversion Result 1
|
||
; ; ADCL.ADC0 6 ADC Conversion Result 0
|
||
; ; ADCH 0x0025 ADC Data Register High (ADLAR = 1)
|
||
; ; ADCH.ADC9 15 ADC Conversion Result 9
|
||
; ; ADCH.ADC8 14 ADC Conversion Result 8
|
||
; ; ADCH.ADC7 13 ADC Conversion Result 7
|
||
; ; ADCH.ADC6 12 ADC Conversion Result 6
|
||
; ; ADCH.ADC5 11 ADC Conversion Result 5
|
||
; ; ADCH.ADC4 10 ADC Conversion Result 4
|
||
; ; ADCH.ADC3 9 ADC Conversion Result 3
|
||
; ; ADCH.ADC2 8 ADC Conversion Result 2
|
||
; ADCSRA 0x0026 ADC Control and Status Register A
|
||
; ADCSRA.ADEN 7 ADC Enable
|
||
; ADCSRA.ADSC 6 ADC Start Conversion
|
||
; ADCSRA.ADFR 5 ADC Free Running Select
|
||
; ADCSRA.ADIF 4 ADC Interrupt Flag
|
||
; ADCSRA.ADIE 3 ADC Interrupt Enable
|
||
; ADCSRA.ADPS2 2 ADC Prescaler Select Bit 2
|
||
; ADCSRA.ADPS1 1 ADC Prescaler Select Bit 1
|
||
; ADCSRA.ADPS0 0 ADC Prescaler Select Bit 0
|
||
; ADMUX 0x0027 ADC Multiplexer Selection Register
|
||
; ADMUX.REFS1 7 Reference Selection Bit 1
|
||
; ADMUX.REFS0 6 Reference Selection Bit 0
|
||
; ADMUX.ADLAR 5 ADC Left Adjust Result
|
||
; ADMUX.MUX3 3 Analog Channel Selection Bit 3
|
||
; ADMUX.MUX2 2 Analog Channel Selection Bit 2
|
||
; ADMUX.MUX1 1 Analog Channel Selection Bit 1
|
||
; ADMUX.MUX0 0 Analog Channel Selection Bit 0
|
||
; ACSR 0x0028 Analog Comparator Control and Status Register
|
||
; ACSR.ACD 7 Analog Comparator Disable
|
||
; ACSR.ACBG 6 Analog Comparator Bandgap Select
|
||
; ACSR.ACO 5 Analog Comparator Output
|
||
; ACSR.ACI 4 Analog Comparator Interrupt Flag
|
||
; ACSR.ACIE 3 Analog Comparator Interrupt Enable
|
||
; ACSR.ACIC 2 Analog Comparator Input Capture Enable
|
||
; ACSR.ACIS1 1 Analog Comparator Interrupt Mode Select 1
|
||
; ACSR.ACIS0 0 Analog Comparator Interrupt Mode Select 0
|
||
; UBRRL 0x0029 USART Baud Rate Register Low
|
||
; UBRRL.UBRR7 7 USART Baud Rate Register bit 7
|
||
; UBRRL.UBRR6 6 USART Baud Rate Register bit 6
|
||
; UBRRL.UBRR5 5 USART Baud Rate Register bit 5
|
||
; UBRRL.UBRR4 4 USART Baud Rate Register bit 4
|
||
; UBRRL.UBRR3 3 USART Baud Rate Register bit 3
|
||
; UBRRL.UBRR2 2 USART Baud Rate Register bit 2
|
||
; UBRRL.UBRR1 1 USART Baud Rate Register bit 1
|
||
; UBRRL.UBRR0 0 USART Baud Rate Register bit 0
|
||
; UCSRB 0x002A USART Control and Status Register B
|
||
; UCSRB.RXCIE 7 RX Complete Interrupt Enable
|
||
; UCSRB.TXCIE 6 TX Complete Interrupt Enable
|
||
; UCSRB.UDRIE 5 USART Data Register Empty Interrupt Enable
|
||
; UCSRB.RXEN 4 Receiver Enable
|
||
; UCSRB.TXEN 3 Transmitter Enable
|
||
; UCSRB.UCSZ2 2 Character Size
|
||
; UCSRB.RXB8 1 Receive Data Bit 8
|
||
; UCSRB.TXB8 0 Transmit Data Bit 8
|
||
; UCSRA 0x002B USART Control and Status Register A
|
||
; UCSRA.RXC 7 USART Receive Complete
|
||
; UCSRA.TXC 6 USART Transmit Complete
|
||
; UCSRA.UDRE 5 USART Data Register Empty
|
||
; UCSRA.FE 4 Frame Error
|
||
; UCSRA.DOR 3 Data OverRun
|
||
; UCSRA.PE 2 Parity Error
|
||
; UCSRA.U2X 1 Double the USART transmission speed
|
||
; UCSRA.MPCM 0 Multi-processor Communication Mode
|
||
; UDR 0x002C USART I/O Data Register
|
||
; SPCR 0x002D SPI Control Register
|
||
; SPCR.SPIE 7 SPI Interrupt Enable
|
||
; SPCR.SPE 6 SPI Enable
|
||
; SPCR.DORD 5 Data Order
|
||
; SPCR.MSTR 4 Master/Slave Select
|
||
; SPCR.CPOL 3 Clock Polarity
|
||
; SPCR.CPHA 2 Clock Phase
|
||
; SPCR.SPR1 1 SPI Clock Rate Select 1
|
||
; SPCR.SPR0 0 SPI Clock Rate Select 0
|
||
; SPSR 0x002E SPI Status Register
|
||
; SPSR.SPIF 7 SPI Interrupt Flag
|
||
; SPSR.WCOL 6 Write COLlision flag
|
||
; SPSR.SPI2X 0 Double SPI Speed Bit
|
||
; SPDR 0x002F SPI Data Register
|
||
; PIND 0x0030 Port D Input Pins Address
|
||
; PIND.PIND7 7
|
||
; PIND.PIND6 6
|
||
; PIND.PIND5 5
|
||
; PIND.PIND4 4
|
||
; PIND.PIND3 3
|
||
; PIND.PIND2 2
|
||
; PIND.PIND1 1
|
||
; PIND.PIND0 0
|
||
; DDRD 0x0031 Port D Data Direction Register
|
||
; DDRD.DDD7 7 Port D Data Direction Register bit 7
|
||
; DDRD.DDD6 6 Port D Data Direction Register bit 6
|
||
; DDRD.DDD5 5 Port D Data Direction Register bit 5
|
||
; DDRD.DDD4 4 Port D Data Direction Register bit 4
|
||
; DDRD.DDD3 3 Port D Data Direction Register bit 3
|
||
; DDRD.DDD2 2 Port D Data Direction Register bit 2
|
||
; DDRD.DDD1 1 Port D Data Direction Register bit 1
|
||
; DDRD.DDD0 0 Port D Data Direction Register bit 0
|
||
; PORTD 0x0032 Port D Data Register
|
||
; PORTD.PORTD7 7 Port D Data Register bit 7
|
||
; PORTD.PORTD6 6 Port D Data Register bit 6
|
||
; PORTD.PORTD5 5 Port D Data Register bit 5
|
||
; PORTD.PORTD4 4 Port D Data Register bit 4
|
||
; PORTD.PORTD3 3 Port D Data Register bit 3
|
||
; PORTD.PORTD2 2 Port D Data Register bit 2
|
||
; PORTD.PORTD1 1 Port D Data Register bit 1
|
||
; PORTD.PORTD0 0 Port D Data Register bit 0
|
||
; PINC 0x0033 Port C Input Pins Address
|
||
; PINC.PINC6 6
|
||
; PINC.PINC5 5
|
||
; PINC.PINC4 4
|
||
; PINC.PINC3 3
|
||
; PINC.PINC2 2
|
||
; PINC.PINC1 1
|
||
; PINC.PINC0 0
|
||
; DDRC 0x0034 Port C Data Direction Register
|
||
; DDRC.DDC6 6 Port C Data Direction Register bit 6
|
||
; DDRC.DDC5 5 Port C Data Direction Register bit 5
|
||
; DDRC.DDC4 4 Port C Data Direction Register bit 4
|
||
; DDRC.DDC3 3 Port C Data Direction Register bit 3
|
||
; DDRC.DDC2 2 Port C Data Direction Register bit 2
|
||
; DDRC.DDC1 1 Port C Data Direction Register bit 1
|
||
; DDRC.DDC0 0 Port C Data Direction Register bit 0
|
||
; PORTC 0x0035 Port C Data Register
|
||
; PORTC.PORTC6 6 Port C Data Register bit 6
|
||
; PORTC.PORTC5 5 Port C Data Register bit 5
|
||
; PORTC.PORTC4 4 Port C Data Register bit 4
|
||
; PORTC.PORTC3 3 Port C Data Register bit 3
|
||
; PORTC.PORTC2 2 Port C Data Register bit 2
|
||
; PORTC.PORTC1 1 Port C Data Register bit 1
|
||
; PORTC.PORTC0 0 Port C Data Register bit 0
|
||
; PINB 0x0036 Port B Input Pins Address
|
||
; PINB.PINB7 7
|
||
; PINB.PINB6 6
|
||
; PINB.PINB5 5
|
||
; PINB.PINB4 4
|
||
; PINB.PINB3 3
|
||
; PINB.PINB2 2
|
||
; PINB.PINB1 1
|
||
; PINB.PINB0 0
|
||
; DDRB 0x0037 Port B Data Direction Register
|
||
; DDRB.DDB7 7 Port B Data Direction Register bit 7
|
||
; DDRB.DDB6 6 Port B Data Direction Register bit 6
|
||
; DDRB.DDB5 5 Port B Data Direction Register bit 5
|
||
; DDRB.DDB4 4 Port B Data Direction Register bit 4
|
||
; DDRB.DDB3 3 Port B Data Direction Register bit 3
|
||
; DDRB.DDB2 2 Port B Data Direction Register bit 2
|
||
; DDRB.DDB1 1 Port B Data Direction Register bit 1
|
||
; DDRB.DDB0 0 Port B Data Direction Register bit 0
|
||
; PORTB 0x0038 Port B Data Register
|
||
; PORTB.PORTB7 7 Port B Data Register bit 7
|
||
; PORTB.PORTB6 6 Port B Data Register bit 6
|
||
; PORTB.PORTB5 5 Port B Data Register bit 5
|
||
; PORTB.PORTB4 4 Port B Data Register bit 4
|
||
; PORTB.PORTB3 3 Port B Data Register bit 3
|
||
; PORTB.PORTB2 2 Port B Data Register bit 2
|
||
; PORTB.PORTB1 1 Port B Data Register bit 1
|
||
; PORTB.PORTB0 0 Port B Data Register bit 0
|
||
; RESERVED0039 0x0039 RESERVED
|
||
; RESERVED003A 0x003A RESERVED
|
||
; RESERVED003B 0x003B RESERVED
|
||
; EECR 0x003C EEPROM Control Register
|
||
; EECR.EERIE 3 EEPROM Ready Interrupt Enable
|
||
; EECR.EEMWE 2 EEPROM Master Write Enable
|
||
; EECR.EEWE 1 EEPROM Write Enable
|
||
; EECR.EERE 0 EEPROM Read Enable
|
||
; EEDR 0x003D EEPROM Data Register
|
||
; EEDR.EEDR7 7 EEPROM Data 7
|
||
; EEDR.EEDR6 6 EEPROM Data 6
|
||
; EEDR.EEDR5 5 EEPROM Data 5
|
||
; EEDR.EEDR4 4 EEPROM Data 4
|
||
; EEDR.EEDR3 3 EEPROM Data 3
|
||
; EEDR.EEDR2 2 EEPROM Data 2
|
||
; EEDR.EEDR1 1 EEPROM Data 1
|
||
; EEDR.EEDR0 0 EEPROM Data 0
|
||
; EEARL 0x003E EEPROM Address Register Low
|
||
; EEARL.EEAR7 7 EEPROM Addres 7
|
||
; EEARL.EEAR6 6 EEPROM Addres 6
|
||
; EEARL.EEAR5 5 EEPROM Addres 5
|
||
; EEARL.EEAR4 4 EEPROM Addres 4
|
||
; EEARL.EEAR3 3 EEPROM Addres 3
|
||
; EEARL.EEAR2 2 EEPROM Addres 2
|
||
; EEARL.EEAR1 1 EEPROM Addres 1
|
||
; EEARL.EEAR0 0 EEPROM Addres 0
|
||
; EEARH 0x003F EEPROM Address Register High
|
||
; EEARH.EEAR8 8 EEPROM Addres 8
|
||
; UCSRC 0x0040 USART Control and Status Register (page 148)
|
||
; UCSRC.URSEL 7 Register Select
|
||
; UCSRC.UMSEL 6 USART Mode Select
|
||
; UCSRC.UPM1 5 Parity Mode 1
|
||
; UCSRC.UPM0 4 Parity Mode 0
|
||
; UCSRC.USBS 3 Stop Bit Select
|
||
; UCSRC.UCSZ1 2 Character Size 1
|
||
; UCSRC.UCSZ0 1 Character Size 0
|
||
; UCSRC.UCPOL 0 Clock Polarity
|
||
; ; UBRRH 0x0040 USART Baud Rate Register High (page 148)
|
||
; ; UBRRH.URSEL 15 Register Select
|
||
; ; UBRRH.UBRR11 11 USART Baud Rate Register bit 11
|
||
; ; UBRRH.UBRR10 10 USART Baud Rate Register bit 10
|
||
; ; UBRRH.UBRR9 9 USART Baud Rate Register bit 9
|
||
; ; UBRRH.UBRR8 8 USART Baud Rate Register bit 8
|
||
; WDTCR 0x0041 Watchdog Timer Control Register
|
||
; WDTCR.WDCE 4 Watchdog Change Enable
|
||
; WDTCR.WDE 3 Watchdog Enable
|
||
; WDTCR.WDP2 2 Watchdog Timer Prescaler 2
|
||
; WDTCR.WDP1 1 Watchdog Timer Prescaler 1
|
||
; WDTCR.WDP0 0 Watchdog Timer Prescaler 0
|
||
; ASSR 0x0042 Asynchronous Status Register
|
||
; ASSR.AS2 3 Asynchronous Timer/Counter2
|
||
; ASSR.TCN2UB 2 Timer/Counter2 Update Busy
|
||
; ASSR.OCR2UB 1 Output Compare Register2 Update Busy
|
||
; ASSR.TCR2UB 0 Timer/Counter Control Register2 Update Busy
|
||
; OCR2 0x0043 Output Compare Register
|
||
; OCR2.OCR2_7 7
|
||
; OCR2.OCR2_6 6
|
||
; OCR2.OCR2_5 5
|
||
; OCR2.OCR2_4 4
|
||
; OCR2.OCR2_3 3
|
||
; OCR2.OCR2_2 2
|
||
; OCR2.OCR2_1 1
|
||
; OCR2.OCR2_0 0
|
||
; TCNT2 0x0044 Timer/Counter Register
|
||
; TCNT2.TCNT2_7 7
|
||
; TCNT2.TCNT2_6 6
|
||
; TCNT2.TCNT2_5 5
|
||
; TCNT2.TCNT2_4 4
|
||
; TCNT2.TCNT2_3 3
|
||
; TCNT2.TCNT2_2 2
|
||
; TCNT2.TCNT2_1 1
|
||
; TCNT2.TCNT2_0 0
|
||
; TCCR2 0x0045 Timer/Counter Control Register
|
||
; TCCR2.FOC2 7 Force Output Compare
|
||
; TCCR2.WGM20 6 Waveform Generation Mode 0
|
||
; TCCR2.COM21 5 Compare Match Output Mode 1
|
||
; TCCR2.COM20 4 Compare Match Output Mode 0
|
||
; TCCR2.WGM21 3 Waveform Generation Mode 1
|
||
; TCCR2.CS22 2 Clock Select 2
|
||
; TCCR2.CS21 1 Clock Select 1
|
||
; TCCR2.CS20 0 Clock Select 0
|
||
; ICR1L 0x0046 Input Capture Register 1 Low
|
||
; ICR1L.ICR1_7 7
|
||
; ICR1L.ICR1_6 6
|
||
; ICR1L.ICR1_5 5
|
||
; ICR1L.ICR1_4 4
|
||
; ICR1L.ICR1_3 3
|
||
; ICR1L.ICR1_2 2
|
||
; ICR1L.ICR1_1 1
|
||
; ICR1L.ICR1_0 0
|
||
; ICR1H 0x0047 Input Capture Register 1 High
|
||
; ICR1H.ICR1_15 15
|
||
; ICR1H.ICR1_14 14
|
||
; ICR1H.ICR1_13 13
|
||
; ICR1H.ICR1_12 12
|
||
; ICR1H.ICR1_11 11
|
||
; ICR1H.ICR1_10 10
|
||
; ICR1H.ICR1_9 9
|
||
; ICR1H.ICR1_8 8
|
||
; OCR1BL 0x0048 Output Compare Register 1 B Low
|
||
; OCR1BL.OCR1B_7 7
|
||
; OCR1BL.OCR1B_6 6
|
||
; OCR1BL.OCR1B_5 5
|
||
; OCR1BL.OCR1B_4 4
|
||
; OCR1BL.OCR1B_3 3
|
||
; OCR1BL.OCR1B_2 2
|
||
; OCR1BL.OCR1B_1 1
|
||
; OCR1BL.OCR1B_0 0
|
||
; OCR1BH 0x0049 Output Compare Register 1 B High
|
||
; OCR1BH.OCR1B_15 15
|
||
; OCR1BH.OCR1B_14 14
|
||
; OCR1BH.OCR1B_13 13
|
||
; OCR1BH.OCR1B_12 12
|
||
; OCR1BH.OCR1B_11 11
|
||
; OCR1BH.OCR1B_10 10
|
||
; OCR1BH.OCR1B_9 9
|
||
; OCR1BH.OCR1B_8 8
|
||
; OCR1AL 0x004A Output Compare Register 1 A Low
|
||
; OCR1AL.OCR1A_7 7
|
||
; OCR1AL.OCR1A_6 6
|
||
; OCR1AL.OCR1A_5 5
|
||
; OCR1AL.OCR1A_4 4
|
||
; OCR1AL.OCR1A_3 3
|
||
; OCR1AL.OCR1A_2 2
|
||
; OCR1AL.OCR1A_1 1
|
||
; OCR1AL.OCR1A_0 0
|
||
; OCR1AH 0x004B Output Compare Register 1 A High
|
||
; OCR1AH.OCR1A_15 15
|
||
; OCR1AH.OCR1A_14 14
|
||
; OCR1AH.OCR1A_13 13
|
||
; OCR1AH.OCR1A_12 12
|
||
; OCR1AH.OCR1A_11 11
|
||
; OCR1AH.OCR1A_10 10
|
||
; OCR1AH.OCR1A_9 9
|
||
; OCR1AH.OCR1A_8 8
|
||
; TCNT1L 0x004C Timer/Counter 1 Low
|
||
; TCNT1L.TCNT1_7 7
|
||
; TCNT1L.TCNT1_6 6
|
||
; TCNT1L.TCNT1_5 5
|
||
; TCNT1L.TCNT1_4 4
|
||
; TCNT1L.TCNT1_3 3
|
||
; TCNT1L.TCNT1_2 2
|
||
; TCNT1L.TCNT1_1 1
|
||
; TCNT1L.TCNT1_0 0
|
||
; TCNT1H 0x004D Timer/Counter 1 High
|
||
; TCNT1H.TCNT1_15 15
|
||
; TCNT1H.TCNT1_14 14
|
||
; TCNT1H.TCNT1_13 13
|
||
; TCNT1H.TCNT1_12 12
|
||
; TCNT1H.TCNT1_11 11
|
||
; TCNT1H.TCNT1_10 10
|
||
; TCNT1H.TCNT1_9 9
|
||
; TCNT1H.TCNT1_8 8
|
||
; TCCR1B 0x004E Timer/Counter 1 Control Register B
|
||
; TCCR1B.ICNC1 7 Input Capture Noise Canceler
|
||
; TCCR1B.ICES1 6 Input Capture Edge Select
|
||
; TCCR1B.WGM13 4 Waveform Generation Mode 3
|
||
; TCCR1B.WGM12 3 Waveform Generation Mode 2
|
||
; TCCR1B.CS12 2 Clock Select 2
|
||
; TCCR1B.CS11 1 Clock Select 1
|
||
; TCCR1B.CS10 0 Clock Select 0
|
||
; TCCR1A 0x004F Timer/Counter 1 Control Register A
|
||
; TCCR1A.COM1A1 7 Compare Output Mode for channel A 1
|
||
; TCCR1A.COM1A0 6 Compare Output Mode for channel A 0
|
||
; TCCR1A.COM1B1 5 Compare Output Mode for channel B 1
|
||
; TCCR1A.COM1B0 4 Compare Output Mode for channel B 0
|
||
; TCCR1A.FOC1A 3 Force Output Compare for channel A
|
||
; TCCR1A.FOC1B 2 Force Output Compare for channel B
|
||
; TCCR1A.WGM11 1 Waveform Generation Mode 1
|
||
; TCCR1A.WGM10 0 Waveform Generation Mode 0
|
||
; SFIOR 0x0050 Special Function IO Register
|
||
; SFIOR.ADHSM 4 ADC High Speed Mode
|
||
; SFIOR.ACME 3 Analog Comparator Multiplexer Enable
|
||
; SFIOR.PUD 2 Pull-up Disable
|
||
; SFIOR.PSR2 1 Prescaler Reset Timer/Counter2
|
||
; SFIOR.PSR10 0 Prescaler Reset Timer/Counter1 and Timer/Counter0
|
||
; OSCCAL 0x0051 Oscillator Calibration Register
|
||
; OSCCAL.CAL7 7 Oscillator Calibration Value 7
|
||
; OSCCAL.CAL6 6 Oscillator Calibration Value 6
|
||
; OSCCAL.CAL5 5 Oscillator Calibration Value 5
|
||
; OSCCAL.CAL4 4 Oscillator Calibration Value 4
|
||
; OSCCAL.CAL3 3 Oscillator Calibration Value 3
|
||
; OSCCAL.CAL2 2 Oscillator Calibration Value 2
|
||
; OSCCAL.CAL1 1 Oscillator Calibration Value 1
|
||
; OSCCAL.CAL0 0 Oscillator Calibration Value 0
|
||
; TCNT0 0x0052 Timer/Counter Register
|
||
; TCNT0.TCNT0_7 7
|
||
; TCNT0.TCNT0_6 6
|
||
; TCNT0.TCNT0_5 5
|
||
; TCNT0.TCNT0_4 4
|
||
; TCNT0.TCNT0_3 3
|
||
; TCNT0.TCNT0_2 2
|
||
; TCNT0.TCNT0_1 1
|
||
; TCNT0.TCNT0_0 0
|
||
; TCCR0 0x0053 Timer/Counter Control Register
|
||
; TCCR0.CS02 2 Clock Select 2
|
||
; TCCR0.CS01 1 Clock Select 1
|
||
; TCCR0.CS00 0 Clock Select 0
|
||
; MCUCSR 0x0054 MCU Control and Status Register
|
||
; MCUCSR.WDRF 3 Watchdog Reset Flag
|
||
; MCUCSR.BORF 2 Brown-out Reset Flag
|
||
; MCUCSR.EXTRF 1 External Reset Flag
|
||
; MCUCSR.PORF 0 Power-on Reset Flag
|
||
; MCUCR 0x0055 MCU Control Register
|
||
; MCUCR.SE 7 Sleep Enable
|
||
; MCUCR.SM2 6 Sleep Mode Select Bit 2
|
||
; MCUCR.SM1 5 Sleep Mode Select Bit 1
|
||
; MCUCR.SM0 4 Sleep Mode Select Bit 0
|
||
; MCUCR.ISC11 3 Interrupt Sense Control 1 Bit 1
|
||
; MCUCR.ISC10 2 Interrupt Sense Control 1 Bit 0
|
||
; MCUCR.ISC01 1 Interrupt Sense Control 0 Bit 1
|
||
; MCUCR.ISC00 0 Interrupt Sense Control 0 Bit 0
|
||
; TWCR 0x0056 TWI Control Register
|
||
; TWCR.TWINT 7 TWI Interrupt Flag
|
||
; TWCR.TWEA 6 TWI Enable Acknowledge Bit
|
||
; TWCR.TWSTA 5 TWI START Condition Bit
|
||
; TWCR.TWSTO 4 TWI STOP Condition Bit
|
||
; TWCR.TWWC 3 TWI Write Collision Flag
|
||
; TWCR.TWEN 2 TWI Enable Bit
|
||
; TWCR.TWIE 0 TWI Interrupt Enable
|
||
; SPMCR 0x0057 Store Program Memory Control Register
|
||
; SPMCR.SPMIE 7 SPM Interrupt Enable
|
||
; SPMCR.RWWSB 6 Read-While-Write Section Busy
|
||
; SPMCR.RWWSRE 4 Read-While-Write Section Read Enable
|
||
; SPMCR.BLBSET 3 Boot Lock Bit Set
|
||
; SPMCR.PGWRT 2 Page Write
|
||
; SPMCR.PGERS 1 Page Erase
|
||
; SPMCR.SPMEN 0 Store Program Memory Enable
|
||
; TIFR 0x0058 Timer/Counter Interrupt Flag Register
|
||
; TIFR.OCF2 7 Output Compare Flag 2
|
||
; TIFR.TOV2 6 Timer/Counter2 Overflow Flag
|
||
; TIFR.ICF1 5 Timer/Counter1, Input Capture Flag
|
||
; TIFR.OCF1A 4 Timer/Counter1, Output Compare A Match Flag
|
||
; TIFR.OCF1B 3 Timer/Counter1, Output Compare B Match Flag
|
||
; TIFR.TOV1 2 Timer/Counter1, Overflow Flag
|
||
; TIFR.TOV0 0 Timer/Counter0 Overflow Flag
|
||
; TIMSK 0x0059 Timer/Counter Interrupt Mask Register
|
||
; TIMSK.OCIE2 7 Timer/Counter2 Output Compare Match Interrupt Enable
|
||
; TIMSK.TOIE2 6 Timer/Counter2 Overflow Interrupt Enable
|
||
; TIMSK.TICIE1 5 Timer/Counter1, Input Capture Interrupt Enable
|
||
; TIMSK.OCIE1A 4 Timer/Counter1, Output Compare A Match Interrupt Enable
|
||
; TIMSK.OCIE1B 3 Timer/Counter1, Output Compare B Match Interrupt Enable
|
||
; TIMSK.TOIE1 2 Timer/Counter1, Overflow Interrupt Enable
|
||
; TIMSK.TOIE0 0 Timer/Counter0 Overflow Interrupt Enable
|
||
; GIFR 0x005A General Interrupt Flag Register
|
||
; GIFR.INTF1 7 External Interrupt Flag 1
|
||
; GIFR.INTF0 6 External Interrupt Flag 0
|
||
; GICR 0x005B General Interrupt Control Register
|
||
; GICR.INT1 7 External Interrupt Request 1 Enable
|
||
; GICR.INT0 6 External Interrupt Request 0 Enable
|
||
; GICR.IVSEL 1 Interrupt Vector Select
|
||
; GICR.IVCE 0 Interrupt Vector Change Enable
|
||
; RESERVED005C 0x005C RESERVED
|
||
; SPL 0x005D Stack Pointer Low
|
||
; SPL.SP7 7
|
||
; SPL.SP6 6
|
||
; SPL.SP5 5
|
||
; SPL.SP4 4
|
||
; SPL.SP3 3
|
||
; SPL.SP2 2
|
||
; SPL.SP1 1
|
||
; SPL.SP0 0
|
||
; SPH 0x005E Stack Pointer High
|
||
; SPH.SP10 10
|
||
; SPH.SP9 9
|
||
; SPH.SP8 8
|
||
; SREG 0x005F Status Register
|
||
; SREG.I 7 Global Interrupt Enable
|
||
; SREG.T 6 Bit Copy Storage
|
||
; SREG.H 5 Half Carry Flag
|
||
; SREG.S 4 Sign Bit
|
||
; SREG.V 3 Two's Complement Overflow Flag
|
||
; SREG.N 2 Negative Flag
|
||
; SREG.Z 1 Zero Flag
|
||
; SREG.C 0 Carry Flag
|
||
|
||
|
||
.ATtiny15L
|
||
SUBARCH=1
|
||
; doc1187.pdf
|
||
;
|
||
|
||
RAM=0
|
||
ROM=1024
|
||
EEPROM=64
|
||
|
||
; MEMORY MAP
|
||
|
||
; Interrupt and reset vector assignments
|
||
entry __RESET 0x0000 External Reset, Power-on Reset, Brown-out Reset, and Watchdog Reset
|
||
entry INT0_ 0x0001 External Interrupt Request 0
|
||
entry I_O_Pins 0x0002 Pin Change Interrupt
|
||
entry TIMER1_COMPA 0x0003 Timer/Counter1 Compare Match A
|
||
entry TIMER1_OVF 0x0004 Timer/Counter1 Overflow
|
||
entry TIMER0_OVF 0x0005 Timer/Counter0 Overflow
|
||
entry EE_RDY 0x0006 EEPROM Ready
|
||
entry ANA_COMP 0x0007 Analog Comparator
|
||
entry ADC_ 0x0008 ADC Conversion Complete
|
||
|
||
|
||
; INPUT/OUTPUT PORTS
|
||
RESERVED0000 0x0000 RESERVED
|
||
RESERVED0001 0x0001 RESERVED
|
||
RESERVED0002 0x0002 RESERVED
|
||
RESERVED0003 0x0003 RESERVED
|
||
ADCL 0x0004 The ADC Data Register Low (ADLAR = 0)
|
||
ADCL.ADC7 7 ADC Conversion result 7
|
||
ADCL.ADC6 6 ADC Conversion result 6
|
||
ADCL.ADC5 5 ADC Conversion result 5
|
||
ADCL.ADC4 4 ADC Conversion result 4
|
||
ADCL.ADC3 3 ADC Conversion result 3
|
||
ADCL.ADC2 2 ADC Conversion result 2
|
||
ADCL.ADC1 1 ADC Conversion result 1
|
||
ADCL.ADC0 0 ADC Conversion result 0
|
||
ADCH 0x0005 The ADC Data Register High (ADLAR = 0)
|
||
ADCH.ADC9 9 ADC Conversion result 9
|
||
ADCH.ADC8 8 ADC Conversion result 8
|
||
; ADCL 0x0004 The ADC Data Register Low (ADLAR = 1)
|
||
; ADCL.ADC1 7 ADC Conversion result 1
|
||
; ADCL.ADC0 6 ADC Conversion result 0
|
||
; ADCH 0x0005 The ADC Data Register High (ADLAR = 1)
|
||
; ADCH.ADC9 15 ADC Conversion result 9
|
||
; ADCH.ADC8 14 ADC Conversion result 8
|
||
; ADCH.ADC7 13 ADC Conversion result 7
|
||
; ADCH.ADC6 12 ADC Conversion result 6
|
||
; ADCH.ADC5 11 ADC Conversion result 5
|
||
; ADCH.ADC4 10 ADC Conversion result 4
|
||
; ADCH.ADC3 9 ADC Conversion result 3
|
||
; ADCH.ADC2 8 ADC Conversion result 2
|
||
ADCSR 0x0006 ADC Control and Status Register
|
||
ADCSR.ADEN 7 ADC Enable
|
||
ADCSR.ADSC 6 ADC Start Conversion
|
||
ADCSR.ADFR 5 ADC Free Running Select
|
||
ADCSR.ADIF 4 ADC Interrupt Flag
|
||
ADCSR.ADIE 3 ADC Interrupt Enable
|
||
ADCSR.ADPS2 2 ADC Prescaler Select Bit 2
|
||
ADCSR.ADPS1 1 ADC Prescaler Select Bit 1
|
||
ADCSR.ADPS0 0 ADC Prescaler Select Bit 0
|
||
ADMUX 0x0007 ADC Multiplexer Selection Register
|
||
ADMUX.REFS1 7 Reference Selection Bit 1
|
||
ADMUX.REFS0 6 Reference Selection Bit 0
|
||
ADMUX.ADLAR 5 ADC Left Adjust Result
|
||
ADMUX.MUX2 2 Analog Channel and Gain Selection Bit 2
|
||
ADMUX.MUX1 1 Analog Channel and Gain Selection Bit 1
|
||
ADMUX.MUX0 0 Analog Channel and Gain Selection Bit 0
|
||
ACSR 0x0008 Analog Comparator Control and Status Register
|
||
ACSR.ACD 7 Analog Comparator Disable
|
||
ACSR.ACBG 6 Analog Comparator Bandgap Select
|
||
ACSR.ACO 5 Analog Comparator Output
|
||
ACSR.ACI 4 Analog Comparator Interrupt Flag
|
||
ACSR.ACIE 3 Analog Comparator Interrupt Enable
|
||
ACSR.ACIS1 1 Analog Comparator Interrupt Mode Select 1
|
||
ACSR.ACIS0 0 Analog Comparator Interrupt Mode Select 0
|
||
RESERVED0009 0x0009 RESERVED
|
||
RESERVED000A 0x000A RESERVED
|
||
RESERVED000B 0x000B RESERVED
|
||
RESERVED000C 0x000C RESERVED
|
||
RESERVED000D 0x000D RESERVED
|
||
RESERVED000E 0x000E RESERVED
|
||
RESERVED000F 0x000F RESERVED
|
||
RESERVED0010 0x0010 RESERVED
|
||
RESERVED0011 0x0011 RESERVED
|
||
RESERVED0012 0x0012 RESERVED
|
||
RESERVED0013 0x0013 RESERVED
|
||
RESERVED0014 0x0014 RESERVED
|
||
RESERVED0015 0x0015 RESERVED
|
||
PINB 0x0016 Port B Input Pins Address
|
||
PINB.PINB5 5
|
||
PINB.PINB4 4
|
||
PINB.PINB3 3
|
||
PINB.PINB2 2
|
||
PINB.PINB1 1
|
||
PINB.PINB0 0
|
||
DDRB 0x0017 Port B Data Direction Register
|
||
DDRB.DDB5 5 Port B Data Direction Register bit 5
|
||
DDRB.DDB4 4 Port B Data Direction Register bit 4
|
||
DDRB.DDB3 3 Port B Data Direction Register bit 3
|
||
DDRB.DDB2 2 Port B Data Direction Register bit 2
|
||
DDRB.DDB1 1 Port B Data Direction Register bit 1
|
||
DDRB.DDB0 0 Port B Data Direction Register bit 0
|
||
PORTB 0x0018 Port B Data Register
|
||
PORTB.PORTB4 4 Port B Data Register bit 4
|
||
PORTB.PORTB3 3 Port B Data Register bit 3
|
||
PORTB.PORTB2 2 Port B Data Register bit 2
|
||
PORTB.PORTB1 1 Port B Data Register bit 1
|
||
PORTB.PORTB0 0 Port B Data Register bit 0
|
||
RESERVED0019 0x0019 RESERVED
|
||
RESERVED001A 0x001A RESERVED
|
||
RESERVED001B 0x001B RESERVED
|
||
EECR 0x001C EEPROM Control Register
|
||
EECR.EERIE 3 EEPROM Ready Interrupt Enable
|
||
EECR.EEMWE 2 EEPROM Master Write Enable
|
||
EECR.EEWE 1 EEPROM Write Enable
|
||
EECR.EERE 0 EEPROM Read Enable
|
||
EEDR 0x001D EEPROM Data Register
|
||
EEDR.EEDR7 7 EEPROM Data 7
|
||
EEDR.EEDR6 6 EEPROM Data 6
|
||
EEDR.EEDR5 5 EEPROM Data 5
|
||
EEDR.EEDR4 4 EEPROM Data 4
|
||
EEDR.EEDR3 3 EEPROM Data 3
|
||
EEDR.EEDR2 2 EEPROM Data 2
|
||
EEDR.EEDR1 1 EEPROM Data 1
|
||
EEDR.EEDR0 0 EEPROM Data 0
|
||
EEAR 0x001E EEPROM Address Register
|
||
EEAR.EEAR5 5 EEPROM Addres 5
|
||
EEAR.EEAR4 4 EEPROM Addres 4
|
||
EEAR.EEAR3 3 EEPROM Addres 3
|
||
EEAR.EEAR2 2 EEPROM Addres 2
|
||
EEAR.EEAR1 1 EEPROM Addres 1
|
||
EEAR.EEAR0 0 EEPROM Addres 0
|
||
RESERVED001F 0x001F RESERVED
|
||
RESERVED0020 0x0020 RESERVED
|
||
WDTCR 0x0021 Watchdog Timer Control Register
|
||
WDTCR.WDTOE 4 Watchdog Turn-off Enable
|
||
WDTCR.WDE 3 Watchdog Enable
|
||
WDTCR.WDP2 2 Watchdog Timer Prescaler 2
|
||
WDTCR.WDP1 1 Watchdog Timer Prescaler 1
|
||
WDTCR.WDP0 0 Watchdog Timer Prescaler 0
|
||
RESERVED0022 0x0022 RESERVED
|
||
RESERVED0023 0x0023 RESERVED
|
||
RESERVED0024 0x0024 RESERVED
|
||
RESERVED0025 0x0025 RESERVED
|
||
RESERVED0026 0x0026 RESERVED
|
||
RESERVED0027 0x0027 RESERVED
|
||
RESERVED0028 0x0028 RESERVED
|
||
RESERVED0029 0x0029 RESERVED
|
||
RESERVED002A 0x002A RESERVED
|
||
RESERVED002B 0x002B RESERVED
|
||
SFIOR 0x002C Special Function IO Register
|
||
SFIOR.FOC1A 2 Force Output Compare 1A
|
||
SFIOR.PSR1 1 Prescaler Reset Timer/Counter1
|
||
SFIOR.PSR0 0 Prescaler Reset Timer/Counter0
|
||
OCR1B 0x002D Timer/Counter1 Output Compare RegisterB
|
||
OCR1A 0x002E Timer/Counter1 Output Compare Register A
|
||
TCNT1 0x002F Timer/Counter1
|
||
TCCR1 0x0030 Timer/Counter1 Control Register
|
||
TCCR1.CTC1 7 Clear Timer/Counter on Compare Match
|
||
TCCR1.PWM1 6 Pulse Width Modulator Enable
|
||
TCCR1.COM1A1 5 Compare Output Mode, Bit 1
|
||
TCCR1.COM1A0 4 Compare Output Mode, Bit 0
|
||
TCCR1.CS13 3 Clock Select Bit 3
|
||
TCCR1.CS12 2 Clock Select Bit 2
|
||
TCCR1.CS11 1 Clock Select Bit 1
|
||
TCCR1.CS10 0 Clock Select Bit 0
|
||
OSCCAL 0x0031 System Clock Oscillator Calibration Register
|
||
OSCCAL.CAL7 7
|
||
OSCCAL.CAL6 6
|
||
OSCCAL.CAL5 5
|
||
OSCCAL.CAL4 4
|
||
OSCCAL.CAL3 3
|
||
OSCCAL.CAL2 2
|
||
OSCCAL.CAL1 1
|
||
OSCCAL.CAL0 0
|
||
TCNT0 0x0032 Timer Counter 0
|
||
TCCR0 0x0033 Timer/Counter0 Control Register
|
||
TCCR0.CS02 2 Clock Select0, Bit 2
|
||
TCCR0.CS01 1 Clock Select0, Bit 1
|
||
TCCR0.CS00 0 Clock Select0, Bit 0
|
||
MCUSR 0x0034 MCU Status Register
|
||
MCUSR.WDRF 3 Watchdog Reset Flag
|
||
MCUSR.BORF 2 Brown-out Reset Flag
|
||
MCUSR.EXTRF 1 External Reset Flag
|
||
MCUSR.PORF 0 Power-on Reset Flag
|
||
MCUCR 0x0035 MCU Control Register
|
||
MCUCR.PUD 6 Pull-up Disable
|
||
MCUCR.SE 5 SleepEnable
|
||
MCUCR.SM1 4 Sleep Mode Select Bit 1
|
||
MCUCR.SM0 3 Sleep Mode Select Bit 0
|
||
MCUCR.ISC01 1 Interrupt Sense Control 0 Bit 1
|
||
MCUCR.ISC00 0 Interrupt Sense Control 0 Bit 0
|
||
RESERVED0036 0x0036 RESERVED
|
||
RESERVED0037 0x0037 RESERVED
|
||
TIFR 0x0038 Timer/Counter Interrupt Flag Register
|
||
TIFR.OCF1A 6 Output Compare Flag 1A
|
||
TIFR.TOV1 2 Timer/Counter1 Overflow Flag
|
||
TIFR.TOV0 1 Timer/Counter0 Overflow Flag
|
||
TIMSK 0x0039 Timer/Counter Interrupt Mask Register
|
||
TIMSK.OCIE1A 6 Timer/Counter1 Output Compare Interrupt Enable
|
||
TIMSK.TOIE1 2 Timer/Counter1 Overflow Interrupt Enable
|
||
TIMSK.TOIE0 1 Timer/Counter0 Overflow Interrupt Enable
|
||
GIFR 0x003A General Interrupt Flag Register
|
||
GIFR.INTF0 6 External Interrupt Flag0
|
||
GIFR.PCIF 5 Pin Change Interrupt Flag
|
||
GIMSK 0x003B General Interrupt Mask Register
|
||
GIMSK.INT0 6 External Interrupt Request 0 Enable
|
||
GIMSK.PCIE 5 PinChange InterruptEnable
|
||
RESERVED003C 0x003C RESERVED
|
||
RESERVED003D 0x003D RESERVED
|
||
RESERVED003E 0x003E RESERVED
|
||
SREG 0x003F Status Register
|
||
SREG.I 7 Global Interrupt Enable
|
||
SREG.T 6 Bit Copy Storage
|
||
SREG.H 5 Half Carry Flag
|
||
SREG.S 4 Sign Bit
|
||
SREG.V 3 Two's Complement Overflow Flag
|
||
SREG.N 2 Negative Flag
|
||
SREG.Z 1 Zero Flag
|
||
SREG.C 0 Carry Flag
|
||
|
||
|
||
.ATtiny26L
|
||
SUBARCH=2
|
||
; doc1477.pdf
|
||
;
|
||
|
||
RAM=128
|
||
ROM=2048
|
||
EEPROM=128
|
||
|
||
; MEMORY MAP
|
||
area DATA FSR_ 0x0000:0x0060
|
||
area DATA I_SRAM 0x0060:0x00E0 Internal SRAM
|
||
|
||
|
||
; Interrupt and reset vector assignments
|
||
entry __RESET 0x0000 Hardware Pin and Watchdog Reset
|
||
entry INT0_ 0x0001 External Interrupt Request 0
|
||
entry I_O_Pins 0x0002 Pin Change Interrupt
|
||
entry TIMER1_CMPA 0x0003 Timer/Counter1 Compare Match 1A
|
||
entry TIMER1_CMPB 0x0004 Timer/Counter1 Compare Match 1B
|
||
entry TIMER1_OVF1 0x0005 Timer/Counter1 Overflow
|
||
entry TIMER0_OVF0 0x0006 Timer/Counter0 Overflow
|
||
entry USI_STRT 0x0007 USI Start
|
||
entry USI_OVF 0x0008 USI Overflow
|
||
entry EE_RDY 0x0009 EEPROM Ready
|
||
entry ANA_COMP 0x000A Analog Comparator
|
||
entry ADC_ 0x000B ADC Conversion Complete
|
||
|
||
|
||
; INPUT/OUTPUT PORTS
|
||
RESERVED0000 0x0000 RESERVED
|
||
RESERVED0001 0x0001 RESERVED
|
||
RESERVED0002 0x0002 RESERVED
|
||
RESERVED0003 0x0003 RESERVED
|
||
ADCL 0x0004 The ADC Data Register Low (ADLAR = 0)
|
||
ADCL.ADC7 7 ADC Conversion result 7
|
||
ADCL.ADC6 6 ADC Conversion result 6
|
||
ADCL.ADC5 5 ADC Conversion result 5
|
||
ADCL.ADC4 4 ADC Conversion result 4
|
||
ADCL.ADC3 3 ADC Conversion result 3
|
||
ADCL.ADC2 2 ADC Conversion result 2
|
||
ADCL.ADC1 1 ADC Conversion result 1
|
||
ADCL.ADC0 0 ADC Conversion result 0
|
||
ADCH 0x0005 The ADC Data Register High (ADLAR = 0)
|
||
ADCH.ADC9 9 ADC Conversion result 9
|
||
ADCH.ADC8 8 ADC Conversion result 8
|
||
; ADCL 0x0004 The ADC Data Register Low (ADLAR = 1)
|
||
; ADCL.ADC1 7 ADC Conversion result 1
|
||
; ADCL.ADC0 6 ADC Conversion result 0
|
||
; ADCH 0x0005 The ADC Data Register High (ADLAR = 1)
|
||
; ADCH.ADC9 15 ADC Conversion result 9
|
||
; ADCH.ADC8 14 ADC Conversion result 8
|
||
; ADCH.ADC7 13 ADC Conversion result 7
|
||
; ADCH.ADC6 12 ADC Conversion result 6
|
||
; ADCH.ADC5 11 ADC Conversion result 5
|
||
; ADCH.ADC4 10 ADC Conversion result 4
|
||
; ADCH.ADC3 9 ADC Conversion result 3
|
||
; ADCH.ADC2 8 ADC Conversion result 2
|
||
ADCSR 0x0006 ADC Control and Status Register
|
||
ADCSR.ADEN 7 ADC Enable
|
||
ADCSR.ADSC 6 ADC Start Conversion
|
||
ADCSR.ADFR 5 ADC Free Running Select
|
||
ADCSR.ADIF 4 ADC Interrupt Flag
|
||
ADCSR.ADIE 3 ADC Interrupt Enable
|
||
ADCSR.ADPS2 2 ADC Prescaler Select Bit 2
|
||
ADCSR.ADPS1 1 ADC Prescaler Select Bit 1
|
||
ADCSR.ADPS0 0 ADC Prescaler Select Bit 0
|
||
ADMUX 0x0007 ADC Multiplexer Selection Register
|
||
ADMUX.REFS1 7 Reference Selection Bit 1
|
||
ADMUX.REFS0 6 Reference Selection Bit 0
|
||
ADMUX.ADLAR 5 ADC Left Adjust Result
|
||
ADMUX.MUX4 4 Analog Channel and Gain Selection Bit 4
|
||
ADMUX.MUX3 3 Analog Channel and Gain Selection Bit 3
|
||
ADMUX.MUX2 2 Analog Channel and Gain Selection Bit 2
|
||
ADMUX.MUX1 1 Analog Channel and Gain Selection Bit 1
|
||
ADMUX.MUX0 0 Analog Channel and Gain Selection Bit 0
|
||
ACSR 0x0008 Analog Comparator Control and Status Register
|
||
ACSR.ACD 7 Analog Comparator Disable
|
||
ACSR.ACBG 6 Analog Comparator Bandgap Select
|
||
ACSR.ACO 5 Analog Comparator Output
|
||
ACSR.ACI 4 Analog Comparator Interrupt Flag
|
||
ACSR.ACIE 3 Analog Comparator Interrupt Enable
|
||
ACSR.ACME 2 Analog Comparator Multiplexer Enable
|
||
ACSR.ACIS1 1 Analog Comparator Interrupt Mode Select 1
|
||
ACSR.ACIS0 0 Analog Comparator Interrupt Mode Select 0
|
||
RESERVED0009 0x0009 RESERVED
|
||
RESERVED000A 0x000A RESERVED
|
||
RESERVED000B 0x000B RESERVED
|
||
RESERVED000C 0x000C RESERVED
|
||
USICR 0x000D USI Control Register
|
||
USICR.USISIE 7 Start Condition Interrupt Enable
|
||
USICR.USIOIE 6 Counter Overflow Interrupt Enable
|
||
USICR.USIWM1 5 Wire Mode 1
|
||
USICR.USIWM0 4 Wire Mode 0
|
||
USICR.USICS1 3 Clock Source Select 1
|
||
USICR.USICS0 2 Clock Source Select 0
|
||
USICR.USICLK 1 Clock Strobe
|
||
USICR.USITC 0 Toggle Clock Port Pin
|
||
USISR 0x000E USI Status Register
|
||
USISR.USISIF 7 Start Condition Interrupt Flag
|
||
USISR.USIOIF 6 Counter Overflow Interrupt Flag
|
||
USISR.USIPF 5 Stop Condition Flag
|
||
USISR.USIDC 4 Data Output Collision
|
||
USISR.USICNT3 3 Counter Value 3
|
||
USISR.USICNT2 2 Counter Value 2
|
||
USISR.USICNT1 1 Counter Value 1
|
||
USISR.USICNT0 0 Counter Value 0
|
||
USIDR 0x000F USI Data Register
|
||
RESERVED0010 0x0010 RESERVED
|
||
RESERVED0011 0x0011 RESERVED
|
||
RESERVED0012 0x0012 RESERVED
|
||
RESERVED0013 0x0013 RESERVED
|
||
RESERVED0014 0x0014 RESERVED
|
||
RESERVED0015 0x0015 RESERVED
|
||
PINB 0x0016 Port B Input Pins Address
|
||
PINB.PINB7 7
|
||
PINB.PINB6 6
|
||
PINB.PINB5 5
|
||
PINB.PINB4 4
|
||
PINB.PINB3 3
|
||
PINB.PINB2 2
|
||
PINB.PINB1 1
|
||
PINB.PINB0 0
|
||
DDRB 0x0017 Port B Data Direction Register
|
||
DDRB.DDB7 7 Port B Data Direction Register bit 7
|
||
DDRB.DDB6 6 Port B Data Direction Register bit 6
|
||
DDRB.DDB5 5 Port B Data Direction Register bit 5
|
||
DDRB.DDB4 4 Port B Data Direction Register bit 4
|
||
DDRB.DDB3 3 Port B Data Direction Register bit 3
|
||
DDRB.DDB2 2 Port B Data Direction Register bit 2
|
||
DDRB.DDB1 1 Port B Data Direction Register bit 1
|
||
DDRB.DDB0 0 Port B Data Direction Register bit 0
|
||
PORTB 0x0018 Port B Data Register
|
||
PORTB.PORTB7 7 Port B Data Register bit 7
|
||
PORTB.PORTB6 6 Port B Data Register bit 6
|
||
PORTB.PORTB5 5 Port B Data Register bit 5
|
||
PORTB.PORTB4 4 Port B Data Register bit 4
|
||
PORTB.PORTB3 3 Port B Data Register bit 3
|
||
PORTB.PORTB2 2 Port B Data Register bit 2
|
||
PORTB.PORTB1 1 Port B Data Register bit 1
|
||
PORTB.PORTB0 0 Port B Data Register bit 0
|
||
PINA 0x0019 Port A Input Pins Address
|
||
PINA.PINA7 7
|
||
PINA.PINA6 6
|
||
PINA.PINA5 5
|
||
PINA.PINA4 4
|
||
PINA.PINA3 3
|
||
PINA.PINA2 2
|
||
PINA.PINA1 1
|
||
PINA.PINA0 0
|
||
DDRA 0x001A Port A Data Direction Register
|
||
DDRA.DDA7 7 Port A Data Direction Register bit 7
|
||
DDRA.DDA6 6 Port A Data Direction Register bit 6
|
||
DDRA.DDA5 5 Port A Data Direction Register bit 5
|
||
DDRA.DDA4 4 Port A Data Direction Register bit 4
|
||
DDRA.DDA3 3 Port A Data Direction Register bit 3
|
||
DDRA.DDA2 2 Port A Data Direction Register bit 2
|
||
DDRA.DDA1 1 Port A Data Direction Register bit 1
|
||
DDRA.DDA0 0 Port A Data Direction Register bit 0
|
||
PORTA 0x001B Port A Data Register
|
||
PORTA.PORTA7 7 Port A Data Register bit 7
|
||
PORTA.PORTA6 6 Port A Data Register bit 6
|
||
PORTA.PORTA5 5 Port A Data Register bit 5
|
||
PORTA.PORTA4 4 Port A Data Register bit 4
|
||
PORTA.PORTA3 3 Port A Data Register bit 3
|
||
PORTA.PORTA2 2 Port A Data Register bit 2
|
||
PORTA.PORTA1 1 Port A Data Register bit 1
|
||
PORTA.PORTA0 0 Port A Data Register bit 0
|
||
EECR 0x001C EEPROM Control Register
|
||
EECR.EERIE 3 EEPROM Ready Interrupt Enable
|
||
EECR.EEMWE 2 EEPROM Master Write Enable
|
||
EECR.EEWE 1 EEPROM Write Enable
|
||
EECR.EERE 0 EEPROM Read Enable
|
||
EEDR 0x001D EEPROM Data Register
|
||
EEDR.EEDR7 7 EEPROM Data 7
|
||
EEDR.EEDR6 6 EEPROM Data 6
|
||
EEDR.EEDR5 5 EEPROM Data 5
|
||
EEDR.EEDR4 4 EEPROM Data 4
|
||
EEDR.EEDR3 3 EEPROM Data 3
|
||
EEDR.EEDR2 2 EEPROM Data 2
|
||
EEDR.EEDR1 1 EEPROM Data 1
|
||
EEDR.EEDR0 0 EEPROM Data 0
|
||
EEAR 0x001E EEPROM Address Register
|
||
EEAR.EEAR6 6 EEPROM Addres 6
|
||
EEAR.EEAR5 5 EEPROM Addres 5
|
||
EEAR.EEAR4 4 EEPROM Addres 4
|
||
EEAR.EEAR3 3 EEPROM Addres 3
|
||
EEAR.EEAR2 2 EEPROM Addres 2
|
||
EEAR.EEAR1 1 EEPROM Addres 1
|
||
EEAR.EEAR0 0 EEPROM Addres 0
|
||
RESERVED0001F 0x001F RESERVED
|
||
RESERVED0020 0x0020 RESERVED
|
||
WDTCR 0x0021 Watchdog Timer Control Register
|
||
WDTCR.WDCE 4 Watchdog Change Enable
|
||
WDTCR.WDE 3 Watchdog Enable
|
||
WDTCR.WDP2 2 Watchdog Timer Prescaler 2
|
||
WDTCR.WDP1 1 Watchdog Timer Prescaler 1
|
||
WDTCR.WDP0 0 Watchdog Timer Prescaler 0
|
||
RESERVED0022 0x0022 RESERVED
|
||
RESERVED0023 0x0023 RESERVED
|
||
RESERVED0024 0x0024 RESERVED
|
||
RESERVED0025 0x0025 RESERVED
|
||
RESERVED0026 0x0026 RESERVED
|
||
RESERVED0027 0x0027 RESERVED
|
||
RESERVED0028 0x0028 RESERVED
|
||
PLLCSR 0x0029 PLL Control and Status Register
|
||
PLLCSR.PCKE 2 PCK Enable
|
||
PLLCSR.PLLE 1 PLL Enable
|
||
PLLCSR.PLOCK 0 PLL Lock Detector
|
||
RESERVED002A 0x002A RESERVED
|
||
OCR1C 0x002B Timer/Counter1 Output Compare Register C
|
||
OCR1B 0x002C Timer/Counter1 Output Compare Register B
|
||
OCR1A 0x002D Timer/Counter1 Output Compare Register A
|
||
TCNT1 0x002E Timer/Counter1
|
||
TCCR1B 0x002F Timer/Counter1 Control Register B
|
||
TCCR1B.CTC1 7 Clear Timer/Counter on Compare Match
|
||
TCCR1B.PSR1 6 Prescaler Reset Timer/Counter1
|
||
TCCR1B.CS13 3 Clock Select Bit 3
|
||
TCCR1B.CS12 2 Clock Select Bit 2
|
||
TCCR1B.CS11 1 Clock Select Bit 1
|
||
TCCR1B.CS10 0 Clock Select Bit 0
|
||
TCCR1A 0x0030 Timer/Counter1 Control Register A
|
||
TCCR1A.COM1A1 7 Comparator A Output Mode, Bit 1
|
||
TCCR1A.COM1A0 6 Comparator A Output Mode, Bit 0
|
||
TCCR1A.COM1B1 5 Comparator B Output Mode, Bit 1
|
||
TCCR1A.COM1B0 4 Comparator B Output Mode, Bit 0
|
||
TCCR1A.FOC1A 3 Force Output Compare Match 1A
|
||
TCCR1A.FOC1B 2 Force Output Compare Match 1B
|
||
TCCR1A.PWM1A 1 Pulse Width Modulator A Enable
|
||
TCCR1A.PWM1B 0 Pulse Width Modulator B Enable
|
||
OSCCAL 0x0031 Oscillator Calibration Register
|
||
OSCCAL.CAL7 7 Oscillator Calibration Value 7
|
||
OSCCAL.CAL6 6 Oscillator Calibration Value 6
|
||
OSCCAL.CAL5 5 Oscillator Calibration Value 5
|
||
OSCCAL.CAL4 4 Oscillator Calibration Value 4
|
||
OSCCAL.CAL3 3 Oscillator Calibration Value 3
|
||
OSCCAL.CAL2 2 Oscillator Calibration Value 2
|
||
OSCCAL.CAL1 1 Oscillator Calibration Value 1
|
||
OSCCAL.CAL0 0 Oscillator Calibration Value 0
|
||
TCNT0 0x0032 Timer/Counter0
|
||
TCCR0 0x0033 Timer/Counter0 Control Register
|
||
TCCR0.PSR0 3 Prescaler Reset Timer/Counter0
|
||
TCCR0.CS02 2 Clock Select0, Bit 2
|
||
TCCR0.CS01 1 Clock Select0, Bit 1
|
||
TCCR0.CS00 0 Clock Select0, Bit 0
|
||
MCUSR 0x0034 MCU Status Register
|
||
MCUSR.WDRF 3 Watchdog Reset Flag
|
||
MCUSR.BORF 2 Brown-out Reset Flag
|
||
MCUSR.EXTRF 1 External Reset Flag
|
||
MCUSR.PORF 0 Power-on Reset Flag
|
||
MCUCR 0x0035 MCU Control Register
|
||
MCUCR.PUD 6 Pull-up Disable
|
||
MCUCR.SE 5 Sleep Enable
|
||
MCUCR.SM1 4 Sleep Mode Select Bit 1
|
||
MCUCR.SM0 3 Sleep Mode Select Bit 0
|
||
MCUCR.ISC01 1 Interrupt Sense Control 0 Bit 1
|
||
MCUCR.ISC00 0 Interrupt Sense Control 0 Bit 0
|
||
RESERVED0036 0x0036 RESERVED
|
||
RESERVED0037 0x0037 RESERVED
|
||
TIFR 0x0038 Timer/Counter Interrupt Flag Register
|
||
TIFR.OCF1A 6 Output Compare Flag 1A
|
||
TIFR.OCF1B 5 Output Compare Flag 1B
|
||
TIFR.TOV1 2 Timer/Counter1 Overflow Flag
|
||
TIFR.TOV0 1 Timer/Counter0 Overflow Flag
|
||
TIMSK 0x0039 Timer/Counter Interrupt Mask Register
|
||
TIMSK.OCIE1A 6 Timer/Counter1 Output Compare Interrupt Enable
|
||
TIMSK.OCIE1B 5 Timer/Counter1 Output Compare Interrupt Enable
|
||
TIMSK.TOIE1 2 Timer/Counter1 Overflow Interrupt Enable
|
||
TIMSK.TOIE0 1 Timer/Counter0 Overflow Interrupt Enable
|
||
GIFR 0x003A General Interrupt Flag Register
|
||
GIFR.INTF0 6 External Interrupt Flag0
|
||
GIFR.PCIF 5 Pin Change Interrupt Flag
|
||
GIMSK 0x003B General Interrupt Mask Register
|
||
GIMSK.INT0 6 External Interrupt Request 0 Enable
|
||
GIMSK.PCIE1 5 Pin Change Interrupt Enable1
|
||
GIMSK.PCIE0 4 Pin Change Interrupt Enable0
|
||
RESERVED003C 0x003C RESERVED
|
||
SP 0x003D Stack Pointer
|
||
SP.SP7 7
|
||
SP.SP6 6
|
||
SP.SP5 5
|
||
SP.SP4 4
|
||
SP.SP3 3
|
||
SP.SP2 2
|
||
SP.SP1 1
|
||
SP.SP0 0
|
||
SREG 0x003F Status Register
|
||
SREG.I 7 Global Interrupt Enable
|
||
SREG.T 6 Bit Copy Storage
|
||
SREG.H 5 Half Carry Flag
|
||
SREG.S 4 Sign Bit
|
||
SREG.V 3 Two's Complement Overflow Flag
|
||
SREG.N 2 Negative Flag
|
||
SREG.Z 1 Zero Flag
|
||
SREG.C 0 Carry Flag
|
||
|
||
; RESERVED0020 0x0020 RESERVED
|
||
; RESERVED0021 0x0021 RESERVED
|
||
; RESERVED0022 0x0022 RESERVED
|
||
; RESERVED0023 0x0023 RESERVED
|
||
; ADCL 0x0024 The ADC Data Register Low (ADLAR = 0)
|
||
; ADCL.ADC7 7 ADC Conversion result 7
|
||
; ADCL.ADC6 6 ADC Conversion result 6
|
||
; ADCL.ADC5 5 ADC Conversion result 5
|
||
; ADCL.ADC4 4 ADC Conversion result 4
|
||
; ADCL.ADC3 3 ADC Conversion result 3
|
||
; ADCL.ADC2 2 ADC Conversion result 2
|
||
; ADCL.ADC1 1 ADC Conversion result 1
|
||
; ADCL.ADC0 0 ADC Conversion result 0
|
||
; ADCH 0x0025 The ADC Data Register High (ADLAR = 0)
|
||
; ADCH.ADC9 9 ADC Conversion result 9
|
||
; ADCH.ADC8 8 ADC Conversion result 8
|
||
; ; ADCL 0x0024 The ADC Data Register Low (ADLAR = 1)
|
||
; ; ADCL.ADC1 7 ADC Conversion result 1
|
||
; ; ADCL.ADC0 6 ADC Conversion result 0
|
||
; ; ADCH 0x0025 The ADC Data Register High (ADLAR = 1)
|
||
; ; ADCH.ADC9 15 ADC Conversion result 9
|
||
; ; ADCH.ADC8 14 ADC Conversion result 8
|
||
; ; ADCH.ADC7 13 ADC Conversion result 7
|
||
; ; ADCH.ADC6 12 ADC Conversion result 6
|
||
; ; ADCH.ADC5 11 ADC Conversion result 5
|
||
; ; ADCH.ADC4 10 ADC Conversion result 4
|
||
; ; ADCH.ADC3 9 ADC Conversion result 3
|
||
; ; ADCH.ADC2 8 ADC Conversion result 2
|
||
; ADCSR 0x0026 ADC Control and Status Register
|
||
; ADCSR.ADEN 7 ADC Enable
|
||
; ADCSR.ADSC 6 ADC Start Conversion
|
||
; ADCSR.ADFR 5 ADC Free Running Select
|
||
; ADCSR.ADIF 4 ADC Interrupt Flag
|
||
; ADCSR.ADIE 3 ADC Interrupt Enable
|
||
; ADCSR.ADPS2 2 ADC Prescaler Select Bit 2
|
||
; ADCSR.ADPS1 1 ADC Prescaler Select Bit 1
|
||
; ADCSR.ADPS0 0 ADC Prescaler Select Bit 0
|
||
; ADMUX 0x0027 ADC Multiplexer Selection Register
|
||
; ADMUX.REFS1 7 Reference Selection Bit 1
|
||
; ADMUX.REFS0 6 Reference Selection Bit 0
|
||
; ADMUX.ADLAR 5 ADC Left Adjust Result
|
||
; ADMUX.MUX4 4 Analog Channel and Gain Selection Bit 4
|
||
; ADMUX.MUX3 3 Analog Channel and Gain Selection Bit 3
|
||
; ADMUX.MUX2 2 Analog Channel and Gain Selection Bit 2
|
||
; ADMUX.MUX1 1 Analog Channel and Gain Selection Bit 1
|
||
; ADMUX.MUX0 0 Analog Channel and Gain Selection Bit 0
|
||
; ACSR 0x0028 Analog Comparator Control and Status Register
|
||
; ACSR.ACD 7 Analog Comparator Disable
|
||
; ACSR.ACBG 6 Analog Comparator Bandgap Select
|
||
; ACSR.ACO 5 Analog Comparator Output
|
||
; ACSR.ACI 4 Analog Comparator Interrupt Flag
|
||
; ACSR.ACIE 3 Analog Comparator Interrupt Enable
|
||
; ACSR.ACME 2 Analog Comparator Multiplexer Enable
|
||
; ACSR.ACIS1 1 Analog Comparator Interrupt Mode Select 1
|
||
; ACSR.ACIS0 0 Analog Comparator Interrupt Mode Select 0
|
||
; RESERVED0029 0x0029 RESERVED
|
||
; RESERVED002A 0x002A RESERVED
|
||
; RESERVED002B 0x002B RESERVED
|
||
; RESERVED002C 0x002C RESERVED
|
||
; USICR 0x002D USI Control Register
|
||
; USICR.USISIE 7 Start Condition Interrupt Enable
|
||
; USICR.USIOIE 6 Counter Overflow Interrupt Enable
|
||
; USICR.USIWM1 5 Wire Mode 1
|
||
; USICR.USIWM0 4 Wire Mode 0
|
||
; USICR.USICS1 3 Clock Source Select 1
|
||
; USICR.USICS0 2 Clock Source Select 0
|
||
; USICR.USICLK 1 Clock Strobe
|
||
; USICR.USITC 0 Toggle Clock Port Pin
|
||
; USISR 0x002E USI Status Register
|
||
; USISR.USISIF 7 Start Condition Interrupt Flag
|
||
; USISR.USIOIF 6 Counter Overflow Interrupt Flag
|
||
; USISR.USIPF 5 Stop Condition Flag
|
||
; USISR.USIDC 4 Data Output Collision
|
||
; USISR.USICNT3 3 Counter Value 3
|
||
; USISR.USICNT2 2 Counter Value 2
|
||
; USISR.USICNT1 1 Counter Value 1
|
||
; USISR.USICNT0 0 Counter Value 0
|
||
; USIDR 0x002F USI Data Register
|
||
; RESERVED0030 0x0030 RESERVED
|
||
; RESERVED0031 0x0031 RESERVED
|
||
; RESERVED0032 0x0032 RESERVED
|
||
; RESERVED0033 0x0033 RESERVED
|
||
; RESERVED0034 0x0034 RESERVED
|
||
; RESERVED0035 0x0035 RESERVED
|
||
; PINB 0x0036 Port B Input Pins Address
|
||
; PINB.PINB7 7
|
||
; PINB.PINB6 6
|
||
; PINB.PINB5 5
|
||
; PINB.PINB4 4
|
||
; PINB.PINB3 3
|
||
; PINB.PINB2 2
|
||
; PINB.PINB1 1
|
||
; PINB.PINB0 0
|
||
; DDRB 0x0037 Port B Data Direction Register
|
||
; DDRB.DDB7 7 Port B Data Direction Register bit 7
|
||
; DDRB.DDB6 6 Port B Data Direction Register bit 6
|
||
; DDRB.DDB5 5 Port B Data Direction Register bit 5
|
||
; DDRB.DDB4 4 Port B Data Direction Register bit 4
|
||
; DDRB.DDB3 3 Port B Data Direction Register bit 3
|
||
; DDRB.DDB2 2 Port B Data Direction Register bit 2
|
||
; DDRB.DDB1 1 Port B Data Direction Register bit 1
|
||
; DDRB.DDB0 0 Port B Data Direction Register bit 0
|
||
; PORTB 0x0038 Port B Data Register
|
||
; PORTB.PORTB7 7 Port B Data Register bit 7
|
||
; PORTB.PORTB6 6 Port B Data Register bit 6
|
||
; PORTB.PORTB5 5 Port B Data Register bit 5
|
||
; PORTB.PORTB4 4 Port B Data Register bit 4
|
||
; PORTB.PORTB3 3 Port B Data Register bit 3
|
||
; PORTB.PORTB2 2 Port B Data Register bit 2
|
||
; PORTB.PORTB1 1 Port B Data Register bit 1
|
||
; PORTB.PORTB0 0 Port B Data Register bit 0
|
||
; PINA 0x0039 Port A Input Pins Address
|
||
; PINA.PINA7 7
|
||
; PINA.PINA6 6
|
||
; PINA.PINA5 5
|
||
; PINA.PINA4 4
|
||
; PINA.PINA3 3
|
||
; PINA.PINA2 2
|
||
; PINA.PINA1 1
|
||
; PINA.PINA0 0
|
||
; DDRA 0x003A Port A Data Direction Register
|
||
; DDRA.DDA7 7 Port A Data Direction Register bit 7
|
||
; DDRA.DDA6 6 Port A Data Direction Register bit 6
|
||
; DDRA.DDA5 5 Port A Data Direction Register bit 5
|
||
; DDRA.DDA4 4 Port A Data Direction Register bit 4
|
||
; DDRA.DDA3 3 Port A Data Direction Register bit 3
|
||
; DDRA.DDA2 2 Port A Data Direction Register bit 2
|
||
; DDRA.DDA1 1 Port A Data Direction Register bit 1
|
||
; DDRA.DDA0 0 Port A Data Direction Register bit 0
|
||
; PORTA 0x003B Port A Data Register
|
||
; PORTA.PORTA7 7 Port A Data Register bit 7
|
||
; PORTA.PORTA6 6 Port A Data Register bit 6
|
||
; PORTA.PORTA5 5 Port A Data Register bit 5
|
||
; PORTA.PORTA4 4 Port A Data Register bit 4
|
||
; PORTA.PORTA3 3 Port A Data Register bit 3
|
||
; PORTA.PORTA2 2 Port A Data Register bit 2
|
||
; PORTA.PORTA1 1 Port A Data Register bit 1
|
||
; PORTA.PORTA0 0 Port A Data Register bit 0
|
||
; EECR 0x003C EEPROM Control Register
|
||
; EECR.EERIE 3 EEPROM Ready Interrupt Enable
|
||
; EECR.EEMWE 2 EEPROM Master Write Enable
|
||
; EECR.EEWE 1 EEPROM Write Enable
|
||
; EECR.EERE 0 EEPROM Read Enable
|
||
; EEDR 0x003D EEPROM Data Register
|
||
; EEDR.EEDR7 7 EEPROM Data 7
|
||
; EEDR.EEDR6 6 EEPROM Data 6
|
||
; EEDR.EEDR5 5 EEPROM Data 5
|
||
; EEDR.EEDR4 4 EEPROM Data 4
|
||
; EEDR.EEDR3 3 EEPROM Data 3
|
||
; EEDR.EEDR2 2 EEPROM Data 2
|
||
; EEDR.EEDR1 1 EEPROM Data 1
|
||
; EEDR.EEDR0 0 EEPROM Data 0
|
||
; EEAR 0x003E EEPROM Address Register
|
||
; EEAR.EEAR6 6 EEPROM Addres 6
|
||
; EEAR.EEAR5 5 EEPROM Addres 5
|
||
; EEAR.EEAR4 4 EEPROM Addres 4
|
||
; EEAR.EEAR3 3 EEPROM Addres 3
|
||
; EEAR.EEAR2 2 EEPROM Addres 2
|
||
; EEAR.EEAR1 1 EEPROM Addres 1
|
||
; EEAR.EEAR0 0 EEPROM Addres 0
|
||
; RESERVED003F 0x003F RESERVED
|
||
; RESERVED0040 0x0040 RESERVED
|
||
; WDTCR 0x0041 Watchdog Timer Control Register
|
||
; WDTCR.WDCE 4 Watchdog Change Enable
|
||
; WDTCR.WDE 3 Watchdog Enable
|
||
; WDTCR.WDP2 2 Watchdog Timer Prescaler 2
|
||
; WDTCR.WDP1 1 Watchdog Timer Prescaler 1
|
||
; WDTCR.WDP0 0 Watchdog Timer Prescaler 0
|
||
; RESERVED0042 0x0042 RESERVED
|
||
; RESERVED0043 0x0043 RESERVED
|
||
; RESERVED0044 0x0044 RESERVED
|
||
; RESERVED0045 0x0045 RESERVED
|
||
; RESERVED0046 0x0046 RESERVED
|
||
; RESERVED0047 0x0047 RESERVED
|
||
; RESERVED0048 0x0048 RESERVED
|
||
; PLLCSR 0x0049 PLL Control and Status Register
|
||
; PLLCSR.PCKE 2 PCK Enable
|
||
; PLLCSR.PLLE 1 PLL Enable
|
||
; PLLCSR.PLOCK 0 PLL Lock Detector
|
||
; RESERVED004A 0x004A RESERVED
|
||
; OCR1C 0x004B Timer/Counter1 Output Compare Register C
|
||
; OCR1B 0x004C Timer/Counter1 Output Compare Register B
|
||
; OCR1A 0x004D Timer/Counter1 Output Compare Register A
|
||
; TCNT1 0x004E Timer/Counter1
|
||
; TCCR1B 0x004F Timer/Counter1 Control Register B
|
||
; TCCR1B.CTC1 7 Clear Timer/Counter on Compare Match
|
||
; TCCR1B.PSR1 6 Prescaler Reset Timer/Counter1
|
||
; TCCR1B.CS13 3 Clock Select Bit 3
|
||
; TCCR1B.CS12 2 Clock Select Bit 2
|
||
; TCCR1B.CS11 1 Clock Select Bit 1
|
||
; TCCR1B.CS10 0 Clock Select Bit 0
|
||
; TCCR1A 0x0050 Timer/Counter1 Control Register A
|
||
; TCCR1A.COM1A1 7 Comparator A Output Mode, Bit 1
|
||
; TCCR1A.COM1A0 6 Comparator A Output Mode, Bit 0
|
||
; TCCR1A.COM1B1 5 Comparator B Output Mode, Bit 1
|
||
; TCCR1A.COM1B0 4 Comparator B Output Mode, Bit 0
|
||
; TCCR1A.FOC1A 3 Force Output Compare Match 1A
|
||
; TCCR1A.FOC1B 2 Force Output Compare Match 1B
|
||
; TCCR1A.PWM1A 1 Pulse Width Modulator A Enable
|
||
; TCCR1A.PWM1B 0 Pulse Width Modulator B Enable
|
||
; OSCCAL 0x0051 Oscillator Calibration Register
|
||
; OSCCAL.CAL7 7 Oscillator Calibration Value 7
|
||
; OSCCAL.CAL6 6 Oscillator Calibration Value 6
|
||
; OSCCAL.CAL5 5 Oscillator Calibration Value 5
|
||
; OSCCAL.CAL4 4 Oscillator Calibration Value 4
|
||
; OSCCAL.CAL3 3 Oscillator Calibration Value 3
|
||
; OSCCAL.CAL2 2 Oscillator Calibration Value 2
|
||
; OSCCAL.CAL1 1 Oscillator Calibration Value 1
|
||
; OSCCAL.CAL0 0 Oscillator Calibration Value 0
|
||
; TCNT0 0x0052 Timer/Counter0
|
||
; TCCR0 0x0053 Timer/Counter0 Control Register
|
||
; TCCR0.PSR0 3 Prescaler Reset Timer/Counter0
|
||
; TCCR0.CS02 2 Clock Select0, Bit 2
|
||
; TCCR0.CS01 1 Clock Select0, Bit 1
|
||
; TCCR0.CS00 0 Clock Select0, Bit 0
|
||
; MCUSR 0x0054 MCU Status Register
|
||
; MCUSR.WDRF 3 Watchdog Reset Flag
|
||
; MCUSR.BORF 2 Brown-out Reset Flag
|
||
; MCUSR.EXTRF 1 External Reset Flag
|
||
; MCUSR.PORF 0 Power-on Reset Flag
|
||
; MCUCR 0x0055 MCU Control Register
|
||
; MCUCR.PUD 6 Pull-up Disable
|
||
; MCUCR.SE 5 Sleep Enable
|
||
; MCUCR.SM1 4 Sleep Mode Select Bit 1
|
||
; MCUCR.SM0 3 Sleep Mode Select Bit 0
|
||
; MCUCR.ISC01 1 Interrupt Sense Control 0 Bit 1
|
||
; MCUCR.ISC00 0 Interrupt Sense Control 0 Bit 0
|
||
; RESERVED0056 0x0056 RESERVED
|
||
; RESERVED0057 0x0057 RESERVED
|
||
; TIFR 0x0058 Timer/Counter Interrupt Flag Register
|
||
; TIFR.OCF1A 6 Output Compare Flag 1A
|
||
; TIFR.OCF1B 5 Output Compare Flag 1B
|
||
; TIFR.TOV1 2 Timer/Counter1 Overflow Flag
|
||
; TIFR.TOV0 1 Timer/Counter0 Overflow Flag
|
||
; TIMSK 0x0059 Timer/Counter Interrupt Mask Register
|
||
; TIMSK.OCIE1A 6 Timer/Counter1 Output Compare Interrupt Enable
|
||
; TIMSK.OCIE1B 5 Timer/Counter1 Output Compare Interrupt Enable
|
||
; TIMSK.TOIE1 2 Timer/Counter1 Overflow Interrupt Enable
|
||
; TIMSK.TOIE0 1 Timer/Counter0 Overflow Interrupt Enable
|
||
; GIFR 0x005A General Interrupt Flag Register
|
||
; GIFR.INTF0 6 External Interrupt Flag0
|
||
; GIFR.PCIF 5 Pin Change Interrupt Flag
|
||
; GIMSK 0x005B General Interrupt Mask Register
|
||
; GIMSK.INT0 6 External Interrupt Request 0 Enable
|
||
; GIMSK.PCIE1 5 Pin Change Interrupt Enable1
|
||
; GIMSK.PCIE0 4 Pin Change Interrupt Enable0
|
||
; RESERVED005C 0x005C RESERVED
|
||
; SP 0x005D Stack Pointer
|
||
; SP.SP7 7
|
||
; SP.SP6 6
|
||
; SP.SP5 5
|
||
; SP.SP4 4
|
||
; SP.SP3 3
|
||
; SP.SP2 2
|
||
; SP.SP1 1
|
||
; SP.SP0 0
|
||
; SREG 0x005F Status Register
|
||
; SREG.I 7 Global Interrupt Enable
|
||
; SREG.T 6 Bit Copy Storage
|
||
; SREG.H 5 Half Carry Flag
|
||
; SREG.S 4 Sign Bit
|
||
; SREG.V 3 Two's Complement Overflow Flag
|
||
; SREG.N 2 Negative Flag
|
||
; SREG.Z 1 Zero Flag
|
||
; SREG.C 0 Carry Flag
|
||
|
||
|
||
.ATtiny28L_V
|
||
SUBARCH=1
|
||
; doc1062.pdf
|
||
;
|
||
|
||
RAM=0
|
||
ROM=2048
|
||
EEPROM=0
|
||
|
||
; MEMORY MAP
|
||
|
||
; Interrupt and reset vector assignments
|
||
entry __RESET 0x0000 Hardware Pin, Power-on Reset and Watchdog Reset
|
||
entry INT0_ 0x0001 External Interrupt Request 0
|
||
entry INT1_ 0x0002 External Interrupt Request 1
|
||
entry Input_Pins 0x0003 Low-level Input on Port B
|
||
entry TIMER0_OVF0 0x0004 Timer/Counter0 Overflow
|
||
entry ANA_COMP 0x0005 Analog Comparator
|
||
|
||
|
||
; INPUT/OUTPUT PORTS
|
||
OSCCAL 0x0000 Oscillator Calibration Register
|
||
OSCCAL.CAL7 7 Oscillator Calibration Value 7
|
||
OSCCAL.CAL6 6 Oscillator Calibration Value 6
|
||
OSCCAL.CAL5 5 Oscillator Calibration Value 5
|
||
OSCCAL.CAL4 4 Oscillator Calibration Value 4
|
||
OSCCAL.CAL3 3 Oscillator Calibration Value 3
|
||
OSCCAL.CAL2 2 Oscillator Calibration Value 2
|
||
OSCCAL.CAL1 1 Oscillator Calibration Value 1
|
||
OSCCAL.CAL0 0 Oscillator Calibration Value 0
|
||
WDTCR 0x0001 Watchdog Timer Control Register
|
||
WDTCR.WDTOE 4 Watchdog Turn-off Enable
|
||
WDTCR.WDE 3 Watchdog Enable
|
||
WDTCR.WDP2 2 Watchdog Timer Prescaler 2
|
||
WDTCR.WDP1 1 Watchdog Timer Prescaler 1
|
||
WDTCR.WDP0 0 Watchdog Timer Prescaler 0
|
||
MODCR 0x0002 Modulation Control Register
|
||
MODCR.ONTIM4 7 Modulation On-time 4
|
||
MODCR.ONTIM3 6 Modulation On-time 3
|
||
MODCR.ONTIM2 5 Modulation On-time 2
|
||
MODCR.ONTIM1 4 Modulation On-time 1
|
||
MODCR.ONTIM0 3 Modulation On-time 0
|
||
MODCR.MCONF2 2 Modulation Configuration Bit 2
|
||
MODCR.MCONF1 1 Modulation Configuration Bit 1
|
||
MODCR.MCONF0 0 Modulation Configuration Bit 0
|
||
TCNT0 0x0003 Timer Counter 0
|
||
TCCR0 0x0004 Timer/Counter0 Control Register
|
||
TCCR0.FOV0 7 Force Overflow
|
||
TCCR0.OOM01 4 Overflow Output Mode, Bit 1
|
||
TCCR0.OOM00 3 Overflow Output Mode, Bit 0
|
||
TCCR0.CS02 2 Clock Select0, Bit 2
|
||
TCCR0.CS01 1 Clock Select0, Bit 1
|
||
TCCR0.CS00 0 Clock Select0, Bit 0
|
||
IFR 0x0005 Interrupt Flag Register
|
||
IFR.INTF1 7 External Interrupt Flag1
|
||
IFR.INTF0 6 External Interrupt Flag0
|
||
IFR.TOV0 4 Timer/Counter0 Overflow Flag
|
||
ICR 0x0006 Interrupt Control Register
|
||
ICR.INT1 7 External Interrupt Request 1 Enable
|
||
ICR.INT0 6 External Interrupt Request 0 Enable
|
||
ICR.LLIE 5 Low-level Input Interrupt Enable
|
||
ICR.TOIE0 4 Timer/Counter0 Overflow Interrupt Enable
|
||
ICR.ISC11 3 Interrupt Sense Control 1 Bit 1
|
||
ICR.ISC10 2 Interrupt Sense Control 1 Bit 0
|
||
ICR.ISC01 1 Interrupt Sense Control 0 Bit 1
|
||
ICR.ISC00 0 Interrupt Sense Control 0 Bit 0
|
||
MCUCS 0x0007 MCU Control and Status Register
|
||
MCUCS.PLUPB 7 Pull-up Enable Port B
|
||
MCUCS.SE 5 Sleep Enable
|
||
MCUCS.SM 4 Sleep Mode
|
||
MCUCS.WDRF 3 Watchdog Reset Flag
|
||
MCUCS.EXTRF 1 External Reset Flag
|
||
MCUCS.PORF 0 Power-on Reset Flag
|
||
ACSR 0x0008 Analog Comparator Control and Status Register
|
||
ACSR.ACD 7 Analog Comparator Disable
|
||
ACSR.ACO 5 Analog Comparator Output
|
||
ACSR.ACI 4 Analog Comparator Interrupt Flag
|
||
ACSR.ACIE 3 Analog Comparator Interrupt Enable
|
||
ACSR.ACIS1 1 Analog Comparator Interrupt Mode Select 1
|
||
ACSR.ACIS0 0 Analog Comparator Interrupt Mode Select 0
|
||
RESERVED0009 0x0009 RESERVED
|
||
RESERVED000A 0x000A RESERVED
|
||
RESERVED000B 0x000B RESERVED
|
||
RESERVED000C 0x000C RESERVED
|
||
RESERVED000D 0x000D RESERVED
|
||
RESERVED000E 0x000E RESERVED
|
||
RESERVED000F 0x000F RESERVED
|
||
PIND 0x0010 Port D Input Pins Address
|
||
PIND.PIND7 7
|
||
PIND.PIND6 6
|
||
PIND.PIND5 5
|
||
PIND.PIND4 4
|
||
PIND.PIND3 3
|
||
PIND.PIND2 2
|
||
PIND.PIND1 1
|
||
PIND.PIND0 0
|
||
DDRD 0x0011 Port D Data Direction Register
|
||
DDRD.DDD7 7 Port D Data Direction Register bit 7
|
||
DDRD.DDD6 6 Port D Data Direction Register bit 6
|
||
DDRD.DDD5 5 Port D Data Direction Register bit 5
|
||
DDRD.DDD4 4 Port D Data Direction Register bit 4
|
||
DDRD.DDD3 3 Port D Data Direction Register bit 3
|
||
DDRD.DDD2 2 Port D Data Direction Register bit 2
|
||
DDRD.DDD1 1 Port D Data Direction Register bit 1
|
||
DDRD.DDD0 0 Port D Data Direction Register bit 0
|
||
PORTD 0x0012 Port D Data Register
|
||
PORTD.PORTD7 7 Port D Data Register bit 7
|
||
PORTD.PORTD6 6 Port D Data Register bit 6
|
||
PORTD.PORTD5 5 Port D Data Register bit 5
|
||
PORTD.PORTD4 4 Port D Data Register bit 4
|
||
PORTD.PORTD3 3 Port D Data Register bit 3
|
||
PORTD.PORTD2 2 Port D Data Register bit 2
|
||
PORTD.PORTD1 1 Port D Data Register bit 1
|
||
PORTD.PORTD0 0 Port D Data Register bit 0
|
||
RESERVED0013 0x0013 RESERVED
|
||
RESERVED0014 0x0014 RESERVED
|
||
RESERVED0015 0x0015 RESERVED
|
||
PINB 0x0016 Port B Input Pins Address
|
||
PINB.PINB7 7
|
||
PINB.PINB6 6
|
||
PINB.PINB5 5
|
||
PINB.PINB4 4
|
||
PINB.PINB3 3
|
||
PINB.PINB2 2
|
||
PINB.PINB1 1
|
||
PINB.PINB0 0
|
||
RESERVED0017 0x0017 RESERVED
|
||
RESERVED0018 0x0018 RESERVED
|
||
PINA 0x0019 Port A Input Pins Address
|
||
PINA.PINA3 3
|
||
PINA.PINA1 1
|
||
PINA.PINA0 0
|
||
DDRA 0x001A Port A Data Direction Register
|
||
DDRA.DDA3 3 Port A Data Direction Register bit 3
|
||
DDRA.DDA2 2 Port A Data Direction Register bit 2
|
||
DDRA.DDA1 1 Port A Data Direction Register bit 1
|
||
DDRA.DDA0 0 Port A Data Direction Register bit 0
|
||
PORTA 0x001B Port A Data Register
|
||
PORTA.PORTA3 3 Port A Data Register bit 3
|
||
PORTA.PORTA2 2 Port A Data Register bit 2
|
||
PORTA.PORTA1 1 Port A Data Register bit 1
|
||
PORTA.PORTA0 0 Port A Data Register bit 0
|
||
RESERVED001C 0x001C RESERVED
|
||
RESERVED001D 0x001D RESERVED
|
||
RESERVED001E 0x001E RESERVED
|
||
RESERVED001F 0x001F RESERVED
|
||
RESERVED0020 0x0020 RESERVED
|
||
RESERVED0021 0x0021 RESERVED
|
||
RESERVED0022 0x0022 RESERVED
|
||
RESERVED0023 0x0023 RESERVED
|
||
RESERVED0024 0x0024 RESERVED
|
||
RESERVED0025 0x0025 RESERVED
|
||
RESERVED0026 0x0026 RESERVED
|
||
RESERVED0027 0x0027 RESERVED
|
||
RESERVED0028 0x0028 RESERVED
|
||
RESERVED0029 0x0029 RESERVED
|
||
RESERVED002A 0x002A RESERVED
|
||
RESERVED002B 0x002B RESERVED
|
||
RESERVED002C 0x002C RESERVED
|
||
RESERVED002D 0x002D RESERVED
|
||
RESERVED002E 0x002E RESERVED
|
||
RESERVED002F 0x002F RESERVED
|
||
RESERVED0030 0x0030 RESERVED
|
||
RESERVED0031 0x0031 RESERVED
|
||
RESERVED0032 0x0032 RESERVED
|
||
RESERVED0033 0x0033 RESERVED
|
||
RESERVED0034 0x0034 RESERVED
|
||
RESERVED0035 0x0035 RESERVED
|
||
RESERVED0036 0x0036 RESERVED
|
||
RESERVED0037 0x0037 RESERVED
|
||
RESERVED0038 0x0038 RESERVED
|
||
RESERVED0039 0x0039 RESERVED
|
||
RESERVED003A 0x003A RESERVED
|
||
RESERVED003B 0x003B RESERVED
|
||
RESERVED003C 0x003C RESERVED
|
||
RESERVED003D 0x003D RESERVED
|
||
RESERVED003E 0x003E RESERVED
|
||
SREG 0x003F Status Register
|
||
SREG.I 7 Global Interrupt Enable
|
||
SREG.T 6 Bit Copy Storage
|
||
SREG.H 5 Half Carry Flag
|
||
SREG.S 4 Sign Bit
|
||
SREG.V 3 Two's Complement Overflow Flag
|
||
SREG.N 2 Negative Flag
|
||
SREG.Z 1 Zero Flag
|
||
SREG.C 0 Carry Flag
|
||
|
||
|
||
.ATtiny_11
|
||
SUBARCH=1
|
||
; doc1006.pdf
|
||
;
|
||
|
||
RAM=0
|
||
ROM=1024
|
||
EEPROM=0
|
||
|
||
; MEMORY MAP
|
||
|
||
; Interrupt and reset vector assignments
|
||
entry __RESET 0x0000 External Pin, Power-on Reset and Watchdog Reset
|
||
entry INT0_ 0x0001 External Interrupt Request 0
|
||
entry I_O_Pins 0x0002 Pin Change Interrupt
|
||
entry TIMER0_OVF0 0x0003 Timer/Counter0 Overflow
|
||
entry ANA_COMP 0x0004 Analog Comparator
|
||
|
||
|
||
; INPUT/OUTPUT PORTS
|
||
RESERVED0000 0x0000 RESERVED
|
||
RESERVED0001 0x0001 RESERVED
|
||
RESERVED0002 0x0002 RESERVED
|
||
RESERVED0003 0x0003 RESERVED
|
||
RESERVED0004 0x0004 RESERVED
|
||
RESERVED0005 0x0005 RESERVED
|
||
RESERVED0006 0x0006 RESERVED
|
||
RESERVED0007 0x0007 RESERVED
|
||
ACSR 0x0008 Analog Comparator Control and Status Register
|
||
ACSR.ACD 7 Analog Comparator Disable
|
||
ACSR.ACO 5 Analog Comparator Output
|
||
ACSR.ACI 4 Analog Comparator Interrupt Flag
|
||
ACSR.ACIE 3 Analog Comparator Interrupt Enable
|
||
ACSR.ACIS1 1 Analog Comparator Interrupt Mode Select 1
|
||
ACSR.ACIS0 0 Analog Comparator Interrupt Mode Select 0
|
||
RESERVED0009 0x0009 RESERVED
|
||
RESERVED000A 0x000A RESERVED
|
||
RESERVED000B 0x000B RESERVED
|
||
RESERVED000C 0x000C RESERVED
|
||
RESERVED000D 0x000D RESERVED
|
||
RESERVED000E 0x000E RESERVED
|
||
RESERVED000F 0x000F RESERVED
|
||
RESERVED0010 0x0010 RESERVED
|
||
RESERVED0011 0x0011 RESERVED
|
||
RESERVED0012 0x0012 RESERVED
|
||
RESERVED0013 0x0013 RESERVED
|
||
RESERVED0014 0x0014 RESERVED
|
||
RESERVED0015 0x0015 RESERVED
|
||
PINB 0x0016 Port B Input Pins Address
|
||
PINB.PINB5 5
|
||
PINB.PINB4 4
|
||
PINB.PINB3 3
|
||
PINB.PINB2 2
|
||
PINB.PINB1 1
|
||
PINB.PINB0 0
|
||
DDRB 0x0017 Port B Data Direction Register
|
||
DDRB.DDB4 4 Port B Data Direction Register bit 4
|
||
DDRB.DDB3 3 Port B Data Direction Register bit 3
|
||
DDRB.DDB2 2 Port B Data Direction Register bit 2
|
||
DDRB.DDB1 1 Port B Data Direction Register bit 1
|
||
DDRB.DDB0 0 Port B Data Direction Register bit 0
|
||
PORTB 0x0018 Port B Data Register
|
||
PORTB.PORTB4 4 Port B Data Register bit 4
|
||
PORTB.PORTB3 3 Port B Data Register bit 3
|
||
PORTB.PORTB2 2 Port B Data Register bit 2
|
||
PORTB.PORTB1 1 Port B Data Register bit 1
|
||
PORTB.PORTB0 0 Port B Data Register bit 0
|
||
RESERVED0019 0x0019 RESERVED
|
||
RESERVED001A 0x001A RESERVED
|
||
RESERVED001B 0x001B RESERVED
|
||
RESERVED001C 0x001C RESERVED
|
||
RESERVED001D 0x001D RESERVED
|
||
RESERVED001E 0x001E RESERVED
|
||
RESERVED001F 0x001F RESERVED
|
||
RESERVED0020 0x0020 RESERVED
|
||
WDTCR 0x0021 Watchdog Timer Control Register
|
||
WDTCR.WDTOE 4 Watchdog Turn-off Enable
|
||
WDTCR.WDE 3 Watchdog Enable
|
||
WDTCR.WDP2 2 Watchdog Timer Prescaler 2
|
||
WDTCR.WDP1 1 Watchdog Timer Prescaler 1
|
||
WDTCR.WDP0 0 Watchdog Timer Prescaler 0
|
||
RESERVED0022 0x0022 RESERVED
|
||
RESERVED0023 0x0023 RESERVED
|
||
RESERVED0024 0x0024 RESERVED
|
||
RESERVED0025 0x0025 RESERVED
|
||
RESERVED0026 0x0026 RESERVED
|
||
RESERVED0027 0x0027 RESERVED
|
||
RESERVED0028 0x0028 RESERVED
|
||
RESERVED0029 0x0029 RESERVED
|
||
RESERVED002A 0x002A RESERVED
|
||
RESERVED002B 0x002B RESERVED
|
||
RESERVED002C 0x002C RESERVED
|
||
RESERVED002D 0x002D RESERVED
|
||
RESERVED002E 0x002E RESERVED
|
||
RESERVED002F 0x002F RESERVED
|
||
RESERVED0030 0x0030 RESERVED
|
||
RESERVED0031 0x0031 RESERVED
|
||
TCNT0 0x0032 Timer Counter 0
|
||
TCCR0 0x0033 Timer/Counter0 Control Register
|
||
TCCR0.CS02 2 Clock Select0, Bit 2
|
||
TCCR0.CS01 1 Clock Select0, Bit 1
|
||
TCCR0.CS00 0 Clock Select0, Bit 0
|
||
MCUSR 0x0034 MCU Status Register
|
||
MCUSR.EXTRF 1 EXTernal Reset Flag
|
||
MCUSR.PORF 0 Power-on Reset Flag
|
||
MCUCR 0x0035 MCU Control Register
|
||
MCUCR.SE 5 Sleep Enable
|
||
MCUCR.SM 4 Sleep Mode
|
||
MCUCR.ISC01 1 Interrupt Sense Control0 Bit 1
|
||
MCUCR.ISC00 0 Interrupt Sense Control0 Bit 0
|
||
RESERVED0036 0x0036 RESERVED
|
||
RESERVED0037 0x0037 RESERVED
|
||
TIFR 0x0038 Timer/Counter Interrupt Flag Register
|
||
TIFR.TOV0 1 Timer/Counter0 Overflow Flag
|
||
TIMSK 0x0039 Timer/Counter Interrupt Mask Register
|
||
TIMSK.TOIE0 1 Timer/Counter0 Overflow Interrupt Enable
|
||
GIFR 0x003A General Interrupt Flag Register
|
||
GIFR.INTF0 6 External Interrupt Flag0
|
||
GIFR.PCIF 5 Pin Change Interrupt Flag
|
||
GIMSK 0x003B General Interrupt Mask Register
|
||
GIMSK.INT0 6 External Interrupt Request 0 Enable
|
||
GIMSK.PCIE 5 Pin Change Interrupt Enable
|
||
RESERVED003C 0x003C RESERVED
|
||
RESERVED003D 0x003D RESERVED
|
||
RESERVED003E 0x003E RESERVED
|
||
SREG 0x003F Status Register
|
||
SREG.I 7 Global Interrupt Enable
|
||
SREG.T 6 Bit Copy Storage
|
||
SREG.H 5 Half Carry Flag
|
||
SREG.S 4 Sign Bit
|
||
SREG.V 3 Two's Complement Overflow Flag
|
||
SREG.N 2 Negative Flag
|
||
SREG.Z 1 Zero Flag
|
||
SREG.C 0 Carry Flag
|
||
|
||
|
||
.ATtiny_11_12
|
||
SUBARCH=1
|
||
; doc1006.pdf
|
||
;
|
||
|
||
RAM=0
|
||
ROM=1024
|
||
EEPROM=64
|
||
|
||
; MEMORY MAP
|
||
|
||
; Interrupt and reset vector assignments
|
||
entry __RESET 0x0000 External Pin, Power-on Reset, Brown-out Reset and Watchdog Reset
|
||
entry INT0_ 0x0001 External Interrupt Request 0
|
||
entry I_O_Pins 0x0002 Pin Change Interrupt
|
||
entry TIMER0_OVF0 0x0003 Timer/Counter0 Overflow
|
||
entry EE_RDY 0x0004 EEPROM Ready
|
||
entry ANA_COMP 0x0005 Analog Comparator
|
||
|
||
|
||
; INPUT/OUTPUT PORTS
|
||
RESERVED0000 0x0000 RESERVED
|
||
RESERVED0001 0x0001 RESERVED
|
||
RESERVED0002 0x0002 RESERVED
|
||
RESERVED0003 0x0003 RESERVED
|
||
RESERVED0004 0x0004 RESERVED
|
||
RESERVED0005 0x0005 RESERVED
|
||
RESERVED0006 0x0006 RESERVED
|
||
RESERVED0007 0x0007 RESERVED
|
||
ACSR 0x0008 Analog Comparator Control and Status Register
|
||
ACSR.ACD 7 Analog Comparator Disable
|
||
ACSR.AINBG 6 Analog Comparator Bandgap Select
|
||
ACSR.ACO 5 Analog Comparator Output
|
||
ACSR.ACI 4 Analog Comparator Interrupt Flag
|
||
ACSR.ACIE 3 Analog Comparator Interrupt Enable
|
||
ACSR.ACIS1 1 Analog Comparator Interrupt Mode Select 1
|
||
ACSR.ACIS0 0 Analog Comparator Interrupt Mode Select 0
|
||
RESERVED0009 0x0009 RESERVED
|
||
RESERVED000A 0x000A RESERVED
|
||
RESERVED000B 0x000B RESERVED
|
||
RESERVED000C 0x000C RESERVED
|
||
RESERVED000D 0x000D RESERVED
|
||
RESERVED000E 0x000E RESERVED
|
||
RESERVED000F 0x000F RESERVED
|
||
RESERVED0010 0x0010 RESERVED
|
||
RESERVED0011 0x0011 RESERVED
|
||
RESERVED0012 0x0012 RESERVED
|
||
RESERVED0013 0x0013 RESERVED
|
||
RESERVED0014 0x0014 RESERVED
|
||
RESERVED0015 0x0015 RESERVED
|
||
PINB 0x0016 Port B Input Pins Address
|
||
PINB.PINB5 5
|
||
PINB.PINB4 4
|
||
PINB.PINB3 3
|
||
PINB.PINB2 2
|
||
PINB.PINB1 1
|
||
PINB.PINB0 0
|
||
DDRB 0x0017 Port B Data Direction Register
|
||
DDRB.DDB5 5 Port B Data Direction Register bit 5
|
||
DDRB.DDB4 4 Port B Data Direction Register bit 4
|
||
DDRB.DDB3 3 Port B Data Direction Register bit 3
|
||
DDRB.DDB2 2 Port B Data Direction Register bit 2
|
||
DDRB.DDB1 1 Port B Data Direction Register bit 1
|
||
DDRB.DDB0 0 Port B Data Direction Register bit 0
|
||
PORTB 0x0018 Port B Data Register
|
||
PORTB.PORTB4 4 Port B Data Register bit 4
|
||
PORTB.PORTB3 3 Port B Data Register bit 3
|
||
PORTB.PORTB2 2 Port B Data Register bit 2
|
||
PORTB.PORTB1 1 Port B Data Register bit 1
|
||
PORTB.PORTB0 0 Port B Data Register bit 0
|
||
RESERVED0019 0x0019 RESERVED
|
||
RESERVED001A 0x001A RESERVED
|
||
RESERVED001B 0x001B RESERVED
|
||
EECR 0x001C EEPROM Control Register
|
||
EECR.EERIE 3 EEPROM Ready Interrupt Enable
|
||
EECR.EEMWE 2 EEPROM Master Write Enable
|
||
EECR.EEWE 1 EEPROM Write Enable
|
||
EECR.EERE 0 EEPROM Read Enable
|
||
EEDR 0x001D EEPROM Data Register
|
||
EEDR.EEDR7 7 EEPROM Data 7
|
||
EEDR.EEDR6 6 EEPROM Data 6
|
||
EEDR.EEDR5 5 EEPROM Data 5
|
||
EEDR.EEDR4 4 EEPROM Data 4
|
||
EEDR.EEDR3 3 EEPROM Data 3
|
||
EEDR.EEDR2 2 EEPROM Data 2
|
||
EEDR.EEDR1 1 EEPROM Data 1
|
||
EEDR.EEDR0 0 EEPROM Data 0
|
||
EEAR 0x001E EEPROM Address Register
|
||
EEAR.EEAR5 5
|
||
EEAR.EEAR4 4
|
||
EEAR.EEAR3 3
|
||
EEAR.EEAR2 2
|
||
EEAR.EEAR1 1
|
||
EEAR.EEAR0 0
|
||
RESERVED001F 0x001F RESERVED
|
||
RESERVED0020 0x0020 RESERVED
|
||
WDTCR 0x0021 Watchdog Timer Control Register
|
||
WDTCR.WDTOE 4 Watchdog Turn-off Enable
|
||
WDTCR.WDE 3 Watchdog Enable
|
||
WDTCR.WDP2 2 Watchdog Timer Prescaler 2
|
||
WDTCR.WDP1 1 Watchdog Timer Prescaler 1
|
||
WDTCR.WDP0 0 Watchdog Timer Prescaler 0
|
||
RESERVED0022 0x0022 RESERVED
|
||
RESERVED0023 0x0023 RESERVED
|
||
RESERVED0024 0x0024 RESERVED
|
||
RESERVED0025 0x0025 RESERVED
|
||
RESERVED0026 0x0026 RESERVED
|
||
RESERVED0027 0x0027 RESERVED
|
||
RESERVED0028 0x0028 RESERVED
|
||
RESERVED0029 0x0029 RESERVED
|
||
RESERVED002A 0x002A RESERVED
|
||
RESERVED002B 0x002B RESERVED
|
||
RESERVED002C 0x002C RESERVED
|
||
RESERVED002D 0x002D RESERVED
|
||
RESERVED002E 0x002E RESERVED
|
||
RESERVED002F 0x002F RESERVED
|
||
RESERVED0030 0x0030 RESERVED
|
||
OSCCAL 0x0031 Oscillator Calibration Register
|
||
OSCCAL.CAL7 7 Oscillator Calibration Value 7
|
||
OSCCAL.CAL6 6 Oscillator Calibration Value 6
|
||
OSCCAL.CAL5 5 Oscillator Calibration Value 5
|
||
OSCCAL.CAL4 4 Oscillator Calibration Value 4
|
||
OSCCAL.CAL3 3 Oscillator Calibration Value 3
|
||
OSCCAL.CAL2 2 Oscillator Calibration Value 2
|
||
OSCCAL.CAL1 1 Oscillator Calibration Value 1
|
||
OSCCAL.CAL0 0 Oscillator Calibration Value 0
|
||
TCNT0 0x0032 Timer Counter 0
|
||
TCCR0 0x0033 Timer/Counter0 Control Register
|
||
TCCR0.CS02 2 Clock Select0, Bit 2
|
||
TCCR0.CS01 1 Clock Select0, Bit 1
|
||
TCCR0.CS00 0 Clock Select0, Bit 0
|
||
MCUSR 0x0034 MCU Status Register
|
||
MCUSR.WDRF 3 Watchdog Reset Flag
|
||
MCUSR.BORF 2 Brown-out Reset Flag
|
||
MCUSR.EXTRF 1 EXTernal Reset Flag
|
||
MCUSR.PORF 0 Power-on Reset Flag
|
||
MCUCR 0x0035 MCU Control Register
|
||
MCUCR.PUD 6 Pull-up Disable
|
||
MCUCR.SE 5 Sleep Enable
|
||
MCUCR.SM 4 Sleep Mode
|
||
MCUCR.ISC01 1 Interrupt Sense Control0 Bit 1
|
||
MCUCR.ISC00 0 Interrupt Sense Control0 Bit 0
|
||
RESERVED0036 0x0036 RESERVED
|
||
RESERVED0037 0x0037 RESERVED
|
||
TIFR 0x0038 Timer/Counter Interrupt Flag Register
|
||
TIFR.TOV0 1 Timer/Counter0 Overflow Flag
|
||
TIMSK 0x0039 Timer/Counter Interrupt Mask Register
|
||
TIMSK.TOIE0 1 Timer/Counter0 Overflow Interrupt Enable
|
||
GIFR 0x003A General Interrupt Flag Register
|
||
GIFR.INTF0 6 External Interrupt Flag0
|
||
GIFR.PCIF 5 Pin Change Interrupt Flag
|
||
GIMSK 0x003B General Interrupt Mask Register
|
||
GIMSK.INT0 6 External Interrupt Request 0 Enable
|
||
GIMSK.PCIE 5 Pin Change Interrupt Enable
|
||
RESERVED003C 0x003C RESERVED
|
||
RESERVED003D 0x003D RESERVED
|
||
RESERVED003E 0x003E RESERVED
|
||
SREG 0x003F Status Register
|
||
SREG.I 7 Global Interrupt Enable
|
||
SREG.T 6 Bit Copy Storage
|
||
SREG.H 5 Half Carry Flag
|
||
SREG.S 4 Sign Bit
|
||
SREG.V 3 Two's Complement Overflow Flag
|
||
SREG.N 2 Negative Flag
|
||
SREG.Z 1 Zero Flag
|
||
SREG.C 0 Carry Flag
|
||
|
||
.ATmega168P
|
||
; doc8025.pdf
|
||
;
|
||
|
||
RAM=1024
|
||
ROM=16384
|
||
EEPROM=512
|
||
|
||
|
||
; MEMORY MAP
|
||
area DATA GPWR_ 0x0000:0x0020 General Purpose Working Registers
|
||
area DATA FSR_ 0x0020:0x0060 I/O registers
|
||
area DATA I_SRAM 0x0060:0x0160 Internal SRAM
|
||
|
||
; Interrupt and reset vector assignments
|
||
entry __RESET 0x0000 Hardware Pin
|
||
entry INT0_ 0x0002 External Interrupt Request 0
|
||
entry INT1_ 0x0004 External Interrupt Request 1
|
||
entry PCINT0 0x0006 Pin Change Interrupt Request 0
|
||
entry PCINT1 0x0008 Pin Change Interrupt Request 1
|
||
entry PCINT2 0x000A Pin Change Interrupt Request 2
|
||
entry WDT 0x000C Watchdog Time-out
|
||
entry TIMER2_COMPA 0x000E Timer/Counter2 Comapare Match A
|
||
entry TIMER2_COMPB 0x0010 Timer/Counter2 Comapare Match B
|
||
entry TIMER2_OVF 0x0012 Timer/Counter2 Overflow
|
||
entry TIMER1_CAPT 0x0014 Timer/Counter1 Capture Event
|
||
entry TIMER1_COMPA 0x0016 Timer/Counter1 Comapare Match A
|
||
entry TIMER1_COMPB 0x0018 Timer/Counter1 Comapare Match B
|
||
entry TIMER1_OVF 0x001A Timer/Counter1 Overflow
|
||
entry TIMER0_COMPA 0x001C Timer/Counter0 Comapare Match A
|
||
entry TIMER0_COMPB 0x001E Timer/Counter0 Comapare Match B
|
||
entry TIMER0_OVF 0x0020 Timer/Counter0 Overflow
|
||
entry SPI_STC 0x0022 SPI Serial Transfer Complete
|
||
entry USART_RX 0x0024 USART RX Complete
|
||
entry USART_UDRE 0x0026 USART Data register empty
|
||
entry USART_TX 0x0028 USART TX Complete
|
||
entry ADC 0x002A ADC Conversion Complete
|
||
entry EEREADY 0x002C EEPROM Ready
|
||
|
||
; INPUT/OUTPUT PORTS
|
||
UDR0 0x00A6
|
||
UBRR0H 0x00A5
|
||
UBRR0L 0x00A4
|
||
UCSR0C 0x00A2
|
||
UCSR0C.UMSEL01 7
|
||
UCSR0C.UMSEL00 6
|
||
UCSR0C.UPM01 5
|
||
UCSR0C.UPM00 4
|
||
UCSR0C.USBS0 3
|
||
UCSR0C.UCSZ01 2
|
||
UCSR0C._UDORD0 1
|
||
UCSR0C.UCSZ00 0
|
||
UCSR0B 0x00A1
|
||
UCSR0B.RXCIE0 7
|
||
UCSR0B.TXCIE0 6
|
||
UCSR0B.UDRIE0 5
|
||
UCSR0B.RXEN0 4
|
||
UCSR0B.TXEN0 3
|
||
UCSR0B.UCSZ02 2
|
||
UCSR0B.RXB80 1
|
||
UCSR0B.TXB80 0
|
||
UCSR0A 0x00A0
|
||
UCSR0A.RXC0 7
|
||
UCSR0A.TXC0 6
|
||
UCSR0A.UDRE0 5
|
||
UCSR0A.FE0 4
|
||
UCSR0A.DOR0 3
|
||
UCSR0A.UPE0 2
|
||
UCSR0A.U2X0 1
|
||
UCSR0A.MPCM0 0
|
||
TWAMR 0x009D
|
||
TWAMR.TWAM6 7
|
||
TWAMR.TWAM5 6
|
||
TWAMR.TWAM4 5
|
||
TWAMR.TWAM3 4
|
||
TWAMR.TWAM2 3
|
||
TWAMR.TWAM1 2
|
||
TWAMR.TWAM0 1
|
||
TWCR 0x009C
|
||
TWCR.TWINT 7
|
||
TWCR.TWEA 6
|
||
TWCR.TWSTA 5
|
||
TWCR.TWSTO 4
|
||
TWCR.TWWC 3
|
||
TWCR.TWEN 2
|
||
TWCR.TWIE 0
|
||
TWDR 0x009B
|
||
TWAR 0x009A
|
||
TWAR.TWA6 7
|
||
TWAR.TWA5 6
|
||
TWAR.TWA4 5
|
||
TWAR.TWA3 4
|
||
TWAR.TWA2 3
|
||
TWAR.TWA1 2
|
||
TWAR.TWA0 1
|
||
TWAR.TWGCE 0
|
||
TWSR 0x0099
|
||
TWSR.TWS7 7
|
||
TWSR.TWS6 6
|
||
TWSR.TWS5 5
|
||
TWSR.TWS4 4
|
||
TWSR.TWS3 3
|
||
TWSR.TWPS1 1
|
||
TWSR.TWPS0 0
|
||
TWBR 0x0098
|
||
ASSR 0x0096
|
||
ASSR.EXCLK 6
|
||
ASSR.AS2 5
|
||
ASSR.TCN2UB 4
|
||
ASSR.OCR2AUB 3
|
||
ASSR.OCR2BUB 2
|
||
ASSR.TCR2AUB 1
|
||
ASSR.TCR2BUB 0
|
||
OCR2B 0x0094
|
||
OCR2A 0x0093
|
||
TCNT2 0x0092
|
||
TCCR2B 0x0091
|
||
TCCR2B.FOC2A 7
|
||
TCCR2B.FOC2B 6
|
||
TCCR2B.WGM22 3
|
||
TCCR2B.CS22 2
|
||
TCCR2B.CS21 1
|
||
TCCR2B.CS20 0
|
||
TCCR2A 0x0090
|
||
TCCR2A.COM2A1 7
|
||
TCCR2A.COM2A0 6
|
||
TCCR2A.COM2B1 5
|
||
TCCR2A.COM2B0 4
|
||
TCCR2A.WGM21 1
|
||
TCCR2A.WGM20 0
|
||
OCR1BH 0x006B
|
||
OCR1BH.Timer_Counter1 7
|
||
OCR1BH.Output 5
|
||
OCR1BH.Compare 4
|
||
OCR1BH.Register 3
|
||
OCR1BH.B 2
|
||
OCR1BH.High 1
|
||
OCR1BH.Byte 0
|
||
OCR1BL 0x006A
|
||
OCR1BL.Timer_Counter1 7
|
||
OCR1BL.Output 5
|
||
OCR1BL.Compare 4
|
||
OCR1BL.Register 3
|
||
OCR1BL.B 2
|
||
OCR1BL.Low 1
|
||
OCR1BL.Byte 0
|
||
OCR1AH 0x0069
|
||
OCR1AH.Timer_Counter1 7
|
||
OCR1AH.Output 5
|
||
OCR1AH.Compare 4
|
||
OCR1AH.Register 3
|
||
OCR1AH.A 2
|
||
OCR1AH.High 1
|
||
OCR1AH.Byte 0
|
||
OCR1AL 0x0068
|
||
OCR1AL.Timer_Counter1 7
|
||
OCR1AL.Output 5
|
||
OCR1AL.Compare 4
|
||
OCR1AL.Register 3
|
||
OCR1AL.A 2
|
||
OCR1AL.Low 1
|
||
OCR1AL.Byte 0
|
||
ICR1H 0x0067
|
||
ICR1H.Timer_Counter1 7
|
||
ICR1H.Input 5
|
||
ICR1H.Capture 4
|
||
ICR1H.Register 3
|
||
ICR1H.High 2
|
||
ICR1H.Byte 1
|
||
ICR1H.136 0
|
||
ICR1L 0x0066
|
||
ICR1L.Timer_Counter1 7
|
||
ICR1L.Input 5
|
||
ICR1L.Capture 4
|
||
ICR1L.Register 3
|
||
ICR1L.Low 2
|
||
ICR1L.Byte 1
|
||
ICR1L.136 0
|
||
TCNT1H 0x0065
|
||
TCNT1L 0x0064
|
||
TCCR1C 0x0062
|
||
TCCR1C.FOC1A 7
|
||
TCCR1C.FOC1B 6
|
||
TCCR1B 0x0061
|
||
TCCR1B.ICNC1 7
|
||
TCCR1B.ICES1 6
|
||
TCCR1B.WGM13 4
|
||
TCCR1B.WGM12 3
|
||
TCCR1B.CS12 2
|
||
TCCR1B.CS11 1
|
||
TCCR1B.CS10 0
|
||
TCCR1A 0x0060
|
||
TCCR1A.COM1A1 7
|
||
TCCR1A.COM1A0 6
|
||
TCCR1A.COM1B1 5
|
||
TCCR1A.COM1B0 4
|
||
TCCR1A.WGM11 1
|
||
TCCR1A.WGM10 0
|
||
DIDR1 0x005F
|
||
DIDR1.AIN1D 1
|
||
DIDR1.AIN0D 0
|
||
DIDR0 0x005E
|
||
DIDR0.ADC5D 5
|
||
DIDR0.ADC4D 4
|
||
DIDR0.ADC3D 3
|
||
DIDR0.ADC2D 2
|
||
DIDR0.ADC1D 1
|
||
DIDR0.ADC0D 0
|
||
ADMUX 0x005C
|
||
ADMUX.REFS1 7
|
||
ADMUX.REFS0 6
|
||
ADMUX.ADLAR 5
|
||
ADMUX.MUX3 3
|
||
ADMUX.MUX2 2
|
||
ADMUX.MUX1 1
|
||
ADMUX.MUX0 0
|
||
ADCSRB 0x005B
|
||
ADCSRB.ACME 6
|
||
ADCSRB.ADTS2 2
|
||
ADCSRB.ADTS1 1
|
||
ADCSRB.ADTS0 0
|
||
ADCSRA 0x005A
|
||
ADCSRA.ADEN 7
|
||
ADCSRA.ADSC 6
|
||
ADCSRA.ADATE 5
|
||
ADCSRA.ADIF 4
|
||
ADCSRA.ADIE 3
|
||
ADCSRA.ADPS2 2
|
||
ADCSRA.ADPS1 1
|
||
ADCSRA.ADPS0 0
|
||
ADCH 0x0059
|
||
ADCL 0x0058
|
||
TIMSK2 0x0050
|
||
TIMSK2.OCIE2B 2
|
||
TIMSK2.OCIE2A 1
|
||
TIMSK2.TOIE2 0
|
||
TIMSK1 0x004F
|
||
TIMSK1.ICIE1 5
|
||
TIMSK1.OCIE1B 2
|
||
TIMSK1.OCIE1A 1
|
||
TIMSK1.TOIE1 0
|
||
TIMSK0 0x004E
|
||
TIMSK0.OCIE0B 2
|
||
TIMSK0.OCIE0A 1
|
||
TIMSK0.TOIE0 0
|
||
PCMSK2 0x004D
|
||
PCMSK2.PCINT23 7
|
||
PCMSK2.PCINT22 6
|
||
PCMSK2.PCINT21 5
|
||
PCMSK2.PCINT20 4
|
||
PCMSK2.PCINT19 3
|
||
PCMSK2.PCINT18 2
|
||
PCMSK2.PCINT17 1
|
||
PCMSK2.PCINT16 0
|
||
PCMSK1 0x004C
|
||
PCMSK1.PCINT14 6
|
||
PCMSK1.PCINT13 5
|
||
PCMSK1.PCINT12 4
|
||
PCMSK1.PCINT11 3
|
||
PCMSK1.PCINT10 2
|
||
PCMSK1.PCINT9 1
|
||
PCMSK1.PCINT8 0
|
||
PCMSK0 0x004B
|
||
PCMSK0.PCINT7 7
|
||
PCMSK0.PCINT6 6
|
||
PCMSK0.PCINT5 5
|
||
PCMSK0.PCINT4 4
|
||
PCMSK0.PCINT3 3
|
||
PCMSK0.PCINT2 2
|
||
PCMSK0.PCINT1 1
|
||
PCMSK0.PCINT0 0
|
||
EICRA 0x0049
|
||
EICRA.ISC11 3
|
||
EICRA.ISC10 2
|
||
EICRA.ISC01 1
|
||
EICRA.ISC00 0
|
||
PCICR 0x0048
|
||
PCICR.PCIE2 2
|
||
PCICR.PCIE1 1
|
||
PCICR.PCIE0 0
|
||
OSCCAL 0x0046
|
||
PRR 0x0044
|
||
PRR.PRTWI 7
|
||
PRR.PRTIM2 6
|
||
PRR.PRTIM0 5
|
||
PRR.PRTIM1 3
|
||
PRR.PRSPI 2
|
||
PRR.PRUSART0 1
|
||
PRR.PRADC 0
|
||
CLKPR 0x0041
|
||
CLKPR.CLKPCE 7
|
||
CLKPR.CLKPS3 3
|
||
CLKPR.CLKPS2 2
|
||
CLKPR.CLKPS1 1
|
||
CLKPR.CLKPS0 0
|
||
WDTCSR 0x0040
|
||
WDTCSR.WDIF 7
|
||
WDTCSR.WDIE 6
|
||
WDTCSR.WDP3 5
|
||
WDTCSR.WDCE 4
|
||
WDTCSR.WDE 3
|
||
WDTCSR.WDP2 2
|
||
WDTCSR.WDP1 1
|
||
WDTCSR.WDP0 0
|
||
SREG 0x003F
|
||
SREG.I 7
|
||
SREG.T 6
|
||
SREG.H 5
|
||
SREG.S 4
|
||
SREG.V 3
|
||
SREG.N 2
|
||
SREG.Z 1
|
||
SREG.C 0
|
||
SPH 0x003E
|
||
SPH.(SP10) 2
|
||
SPH.5. 1
|
||
SPH.SP9 0
|
||
SPL 0x003D
|
||
SPL.SP7 7
|
||
SPL.SP6 6
|
||
SPL.SP5 5
|
||
SPL.SP4 4
|
||
SPL.SP3 3
|
||
SPL.SP2 2
|
||
SPL.SP1 1
|
||
SPL.SP0 0
|
||
SPMCSR 0x0037
|
||
SPMCSR.SPMIE 7
|
||
SPMCSR.(RWWSB)5. 6
|
||
SPMCSR.(RWWSRE)5. 4
|
||
SPMCSR.BLBSET 3
|
||
SPMCSR.PGWRT 2
|
||
SPMCSR.PGERS 1
|
||
SPMCSR.SELFPRGEN 0
|
||
MCUCR 0x0035
|
||
MCUCR.BODS 6
|
||
MCUCR.BODSE 5
|
||
MCUCR.PUD 4
|
||
MCUCR.IVSEL 1
|
||
MCUCR.IVCE 0
|
||
MCUSR 0x0034
|
||
MCUSR.WDRF 3
|
||
MCUSR.BORF 2
|
||
MCUSR.EXTRF 1
|
||
MCUSR.PORF 0
|
||
SMCR 0x0033
|
||
SMCR.SM2 3
|
||
SMCR.SM1 2
|
||
SMCR.SM0 1
|
||
SMCR.SE 0
|
||
ACSR 0x0030
|
||
ACSR.ACD 7
|
||
ACSR.ACBG 6
|
||
ACSR.ACO 5
|
||
ACSR.ACI 4
|
||
ACSR.ACIE 3
|
||
ACSR.ACIC 2
|
||
ACSR.ACIS1 1
|
||
ACSR.ACIS0 0
|
||
SPDR 0x002E
|
||
SPSR 0x002D
|
||
SPSR.SPIF 7
|
||
SPSR.WCOL 6
|
||
SPSR.SPI2X 0
|
||
SPCR 0x002C
|
||
SPCR.SPIE 7
|
||
SPCR.SPE 6
|
||
SPCR.DORD 5
|
||
SPCR.MSTR 4
|
||
SPCR.CPOL 3
|
||
SPCR.CPHA 2
|
||
SPCR.SPR1 1
|
||
SPCR.SPR0 0
|
||
GPIOR2 0x002B
|
||
GPIOR1 0x002A
|
||
OCR0B 0x0028
|
||
OCR0A 0x0027
|
||
TCNT0 0x0026
|
||
TCCR0B 0x0025
|
||
TCCR0B.FOC0A 7
|
||
TCCR0B.FOC0B 6
|
||
TCCR0B.WGM02 3
|
||
TCCR0B.CS02 2
|
||
TCCR0B.CS01 1
|
||
TCCR0B.CS00 0
|
||
TCCR0A 0x0024
|
||
TCCR0A.COM0A1 7
|
||
TCCR0A.COM0A0 6
|
||
TCCR0A.COM0B1 5
|
||
TCCR0A.COM0B0 4
|
||
TCCR0A.WGM01 1
|
||
TCCR0A.WGM00 0
|
||
GTCCR 0x0023
|
||
GTCCR.TSM 7
|
||
GTCCR.PSRASY 1
|
||
GTCCR.PSRSYNC 0
|
||
EEARH 0x0022
|
||
EEARL 0x0021
|
||
EEDR 0x0020
|
||
EECR 0x001F
|
||
EECR.EEPM1 5
|
||
EECR.EEPM0 4
|
||
EECR.EERIE 3
|
||
EECR.EEMPE 2
|
||
EECR.EEPE 1
|
||
EECR.EERE 0
|
||
GPIOR0 0x001E
|
||
EIMSK 0x001D
|
||
EIMSK.INT1 1
|
||
EIMSK.INT0 0
|
||
EIFR 0x001C
|
||
EIFR.INTF1 1
|
||
EIFR.INTF0 0
|
||
PCIFR 0x001B
|
||
PCIFR.PCIF2 2
|
||
PCIFR.PCIF1 1
|
||
PCIFR.PCIF0 0
|
||
TIFR2 0x0017
|
||
TIFR2.OCF2B 2
|
||
TIFR2.OCF2A 1
|
||
TIFR2.TOV2 0
|
||
TIFR1 0x0016
|
||
TIFR1.ICF1 5
|
||
TIFR1.OCF1B 2
|
||
TIFR1.OCF1A 1
|
||
TIFR1.TOV1 0
|
||
TIFR0 0x0015
|
||
TIFR0.OCF0B 2
|
||
TIFR0.OCF0A 1
|
||
TIFR0.TOV0 0
|
||
PORTD 0x000B
|
||
PORTD.PORTD7 7
|
||
PORTD.PORTD6 6
|
||
PORTD.PORTD5 5
|
||
PORTD.PORTD4 4
|
||
PORTD.PORTD3 3
|
||
PORTD.PORTD2 2
|
||
PORTD.PORTD1 1
|
||
PORTD.PORTD0 0
|
||
DDRD 0x000A
|
||
DDRD.DDD7 7
|
||
DDRD.DDD6 6
|
||
DDRD.DDD5 5
|
||
DDRD.DDD4 4
|
||
DDRD.DDD3 3
|
||
DDRD.DDD2 2
|
||
DDRD.DDD1 1
|
||
DDRD.DDD0 0
|
||
PIND 0x0009
|
||
PIND.PIND7 7
|
||
PIND.PIND6 6
|
||
PIND.PIND5 5
|
||
PIND.PIND4 4
|
||
PIND.PIND3 3
|
||
PIND.PIND2 2
|
||
PIND.PIND1 1
|
||
PIND.PIND0 0
|
||
PORTC 0x0008
|
||
PORTC.PORTC6 6
|
||
PORTC.PORTC5 5
|
||
PORTC.PORTC4 4
|
||
PORTC.PORTC3 3
|
||
PORTC.PORTC2 2
|
||
PORTC.PORTC1 1
|
||
PORTC.PORTC0 0
|
||
DDRC 0x0007
|
||
DDRC.DDC6 6
|
||
DDRC.DDC5 5
|
||
DDRC.DDC4 4
|
||
DDRC.DDC3 3
|
||
DDRC.DDC2 2
|
||
DDRC.DDC1 1
|
||
DDRC.DDC0 0
|
||
PINC 0x0006
|
||
PINC.PINC6 6
|
||
PINC.PINC5 5
|
||
PINC.PINC4 4
|
||
PINC.PINC3 3
|
||
PINC.PINC2 2
|
||
PINC.PINC1 1
|
||
PINC.PINC0 0
|
||
PORTB 0x0005
|
||
PORTB.PORTB7 7
|
||
PORTB.PORTB6 6
|
||
PORTB.PORTB5 5
|
||
PORTB.PORTB4 4
|
||
PORTB.PORTB3 3
|
||
PORTB.PORTB2 2
|
||
PORTB.PORTB1 1
|
||
PORTB.PORTB0 0
|
||
DDRB 0x0004
|
||
DDRB.DDB7 7
|
||
DDRB.DDB6 6
|
||
DDRB.DDB5 5
|
||
DDRB.DDB4 4
|
||
DDRB.DDB3 3
|
||
DDRB.DDB2 2
|
||
DDRB.DDB1 1
|
||
DDRB.DDB0 0
|
||
PINB 0x0003
|
||
PINB.PINB7 7
|
||
PINB.PINB6 6
|
||
PINB.PINB5 5
|
||
PINB.PINB4 4
|
||
PINB.PINB3 3
|
||
PINB.PINB2 2
|
||
PINB.PINB1 1
|
||
PINB.PINB0 0
|
||
|
||
.ATtiny2313
|
||
SUBARCH=25
|
||
; doc2543.pdf
|
||
;
|
||
|
||
RAM=128
|
||
ROM=2048
|
||
EEPROM=128
|
||
|
||
|
||
; MEMORY MAP
|
||
area DATA GPWR_ 0x0000:0x0020 General Purpose Working Registers
|
||
area DATA FSR_ 0x0020:0x0060 I/O registers
|
||
area DATA I_SRAM 0x0060:0x00E0 Internal SRAM
|
||
|
||
|
||
; Interrupt and reset vector assignments
|
||
entry __RESET 0x0000 Hardware Pin
|
||
entry INT0_ 0x0001 External Interrupt Request 0
|
||
entry INT1_ 0x0002 External Interrupt Request 1
|
||
entry TIMER1_CAPT 0x0003 Timer/Counter1 Capture Event
|
||
entry TIMER1_COMPA 0x0004 Timer/Counter1 Compare Match A
|
||
entry TIMER1_OVF 0x0005 Timer/Counter1 Overflow
|
||
entry TIMER0_OVF 0x0006 Timer/Counter0 Overflow
|
||
entry USART0_RX 0x0007 USART0, Rx Complete
|
||
entry USART0_UDRE 0x0008 USART0 Data Register Empty
|
||
entry USART0_TX 0x0009 USART0, Tx Complete
|
||
entry ANALOG_COMP 0x000A Analog Comparator
|
||
entry PCINT0 0x000B Pin Change Interrupt Request 0
|
||
entry TIMER1_COMPB 0x000C Timer/Counter1 Compare Match B
|
||
entry TIMER0_COMPA 0x000D Timer/Counter0 Compare Match A
|
||
entry TIMER0_COMPB 0x000E Timer/Counter0 Compare Match B
|
||
entry USI_START 0x000F USI Start Condition
|
||
entry USI_OVERFLOW 0x0010 USI Overflow
|
||
entry EE_READY 0x0011 EEPROM Ready
|
||
entry WDT_OVERFLOW 0x0012 Watchdog Timer Overflow
|
||
|
||
|
||
; INPUT/OUTPUT PORTS
|
||
RESERVED0000 0x0000 RESERVED
|
||
DIDR 0x0001 Digital Input Disable Register
|
||
DIDR.AIND0 1 AIN0 Digital Input Disable
|
||
DIDR.AIND1 2 AIN1 Digital Input Disable
|
||
UBRRH 0x0002 USART Baud Rate Registers High
|
||
UCSRC 0x0003 USART Control and Status Register C
|
||
UCSRC.UMSEL 6 USART Mode Select
|
||
UCSRC.UPM1 5 Parity Mode 1
|
||
UCSRC.UPM0 4 Parity Mode 0
|
||
UCSRC.USBS 3 Stop Bit Select
|
||
UCSRC.UCSZ1 2 Character Size 1
|
||
UCSRC.UCSZ0 1 Character Size 0
|
||
UCSRC.UCPOL 0 Clock Polarity
|
||
RESERVED0004 0x0004 RESERVED
|
||
RESERVED0005 0x0005 RESERVED
|
||
RESERVED0006 0x0006 RESERVED
|
||
RESERVED0007 0x0007 RESERVED
|
||
ACSR 0x0008 Analog Comparator Control and Status Register
|
||
ACSR.ACD 7 Analog Comparator Disable
|
||
ACSR.ACBG 6 Analog Comparator Bandgap Select
|
||
ACSR.ACO 5 Analog Comparator Output
|
||
ACSR.ACI 4 Analog Comparator Interrupt Flag
|
||
ACSR.ACIE 3 Analog Comparator Interrupt Enable
|
||
ACSR.ACIC 2 Analog Comparator Input Capture Enable
|
||
ACSR.ACIS1 1 Analog Comparator Interrupt Mode Select 1
|
||
ACSR.ACIS0 0 Analog Comparator Interrupt Mode Select 0
|
||
UBRRL 0x0009 USART Baud Rate Register
|
||
UBRRL.UBRR7 7
|
||
UBRRL.UBRR6 6
|
||
UBRRL.UBRR5 5
|
||
UBRRL.UBRR4 4
|
||
UBRRL.UBRR3 3
|
||
UBRRL.UBRR2 2
|
||
UBRRL.UBRR1 1
|
||
UBRRL.UBRR0 0
|
||
UCSRB 0x000A USART Control and Status Register
|
||
UCSRB.RXCIE 7 RX Complete Interrupt Enable
|
||
UCSRB.TXCIE 6 TX Complete Interrupt Enable
|
||
UCSRB.UDRIE 5 USART Data Register Empty Interrupt Enable
|
||
UCSRB.RXEN 4 Receiver Enable
|
||
UCSRB.TXEN 3 Transmitter Enable
|
||
UCSRB.UCSZ2 2 Character Size
|
||
UCSRB.RXB8 1 Receive Data Bit 8
|
||
UCSRB.TXB8 0 Transmit Data Bit8
|
||
UCSRA 0x000B USART Control and Status Register
|
||
UCSRA.RXC 7 USART Receive Complete
|
||
UCSRA.TXC 6 USART Transmit Complete
|
||
UCSRA.UDRE 5 USART Data Register Empty
|
||
UCSRA.FE 4 Frame Error
|
||
UCSRA.DOR 3 Data OverRun
|
||
UCSRA.UPE 2 Parity Error
|
||
UCSRA.U2X 1 Double the USART Transmission Speed
|
||
UCSRA.MPCM 0 Multi-Processor Communication Mode
|
||
UDR 0x000C USART I/O Data Register
|
||
USICR 0x000D USI Control Register
|
||
USICR.USISIE 7 Start Condition Interrupt Enable
|
||
USICR.USIOIE 6 Counter Overflow Interrupt Enable
|
||
USICR.USIWM1 5 Wire Mode 1
|
||
USICR.USIWM0 4 Wire Mode 0
|
||
USICR.USICS1 3 Clock Source Select 1
|
||
USICR.USICS0 2 Clock Source Select 0
|
||
USICR.USICLK 1 Clock Strobe
|
||
USICR.USITC 0 Toggle Clock Port Pin
|
||
USISR 0x000E USI Status Register
|
||
USISR.USISIF 7 Start Condition Interrupt Flag
|
||
USISR.USIOIF 6 Counter Overflow Interrupt Flag
|
||
USISR.USIPF 5 Stop Condition Flag
|
||
USISR.USIDC 4 Data Output Collision
|
||
USISR.USICNT3 3 Counter Value 3
|
||
USISR.USICNT2 2 Counter Value 2
|
||
USISR.USICNT1 1 Counter Value 1
|
||
USISR.USICNT0 0 Counter Value 0
|
||
USIDR 0x000F USI Data Register
|
||
PIND 0x0010 Port D Input Pins Address
|
||
PIND.PIND7 7
|
||
PIND.PIND6 6
|
||
PIND.PIND5 5
|
||
PIND.PIND4 4
|
||
PIND.PIND3 3
|
||
PIND.PIND2 2
|
||
PIND.PIND1 1
|
||
PIND.PIND0 0
|
||
DDRD 0x0011 Port D Data Direction Register
|
||
DDRD.DDD7 7 Port D Data Direction Register bit 7
|
||
DDRD.DDD6 6 Port D Data Direction Register bit 6
|
||
DDRD.DDD5 5 Port D Data Direction Register bit 5
|
||
DDRD.DDD4 4 Port D Data Direction Register bit 4
|
||
DDRD.DDD3 3 Port D Data Direction Register bit 3
|
||
DDRD.DDD2 2 Port D Data Direction Register bit 2
|
||
DDRD.DDD1 1 Port D Data Direction Register bit 1
|
||
DDRD.DDD0 0 Port D Data Direction Register bit 0
|
||
PORTD 0x0012 Port D Data Register
|
||
PORTD.PORTD7 7 Port D Data Register bit 7
|
||
PORTD.PORTD6 6 Port D Data Register bit 6
|
||
PORTD.PORTD5 5 Port D Data Register bit 5
|
||
PORTD.PORTD4 4 Port D Data Register bit 4
|
||
PORTD.PORTD3 3 Port D Data Register bit 3
|
||
PORTD.PORTD2 2 Port D Data Register bit 2
|
||
PORTD.PORTD1 1 Port D Data Register bit 1
|
||
PORTD.PORTD0 0 Port D Data Register bit 0
|
||
GPIOR0 0x0013 General Purpose I/O Register 0
|
||
GPIOR1 0x0014 General Purpose I/O Register 0
|
||
GPIOR2 0x0015 General Purpose I/O Register 0
|
||
PINB 0x0016 Port B Input Pins Address
|
||
PINB.PINB7 7
|
||
PINB.PINB6 6
|
||
PINB.PINB5 5
|
||
PINB.PINB4 4
|
||
PINB.PINB3 3
|
||
PINB.PINB2 2
|
||
PINB.PINB1 1
|
||
PINB.PINB0 0
|
||
DDRB 0x0017 Port B Data Direction Register
|
||
DDRB.DDB7 7 Port B Data Direction Register bit 7
|
||
DDRB.DDB6 6 Port B Data Direction Register bit 6
|
||
DDRB.DDB5 5 Port B Data Direction Register bit 5
|
||
DDRB.DDB4 4 Port B Data Direction Register bit 4
|
||
DDRB.DDB3 3 Port B Data Direction Register bit 3
|
||
DDRB.DDB2 2 Port B Data Direction Register bit 2
|
||
DDRB.DDB1 1 Port B Data Direction Register bit 1
|
||
DDRB.DDB0 0 Port B Data Direction Register bit 0
|
||
PORTB 0x0018 Port B Data Register
|
||
PORTB.PORTB7 7 Port B Data Register bit 7
|
||
PORTB.PORTB6 6 Port B Data Register bit 6
|
||
PORTB.PORTB5 5 Port B Data Register bit 5
|
||
PORTB.PORTB4 4 Port B Data Register bit 4
|
||
PORTB.PORTB3 3 Port B Data Register bit 3
|
||
PORTB.PORTB2 2 Port B Data Register bit 2
|
||
PORTB.PORTB1 1 Port B Data Register bit 1
|
||
PORTB.PORTB0 0 Port B Data Register bit 0
|
||
PINA 0x0019 Port A Input Pins Address
|
||
PINA.PINA7 7
|
||
PINA.PINA6 6
|
||
PINA.PINA5 5
|
||
PINA.PINA4 4
|
||
PINA.PINA3 3
|
||
PINA.PINA2 2
|
||
PINA.PINA1 1
|
||
PINA.PINA0 0
|
||
DDRA 0x001A Port A Data Direction Register
|
||
DDRA.DDA7 7 Port A Data Direction Register bit 7
|
||
DDRA.DDA6 6 Port A Data Direction Register bit 6
|
||
DDRA.DDA5 5 Port A Data Direction Register bit 5
|
||
DDRA.DDA4 4 Port A Data Direction Register bit 4
|
||
DDRA.DDA3 3 Port A Data Direction Register bit 3
|
||
DDRA.DDA2 2 Port A Data Direction Register bit 2
|
||
DDRA.DDA1 1 Port A Data Direction Register bit 1
|
||
DDRA.DDA0 0 Port A Data Direction Register bit 0
|
||
PORTA 0x001B Port A Data Register
|
||
PORTA.PORTA7 7 Port A Data Register bit 7
|
||
PORTA.PORTA6 6 Port A Data Register bit 6
|
||
PORTA.PORTA5 5 Port A Data Register bit 5
|
||
PORTA.PORTA4 4 Port A Data Register bit 4
|
||
PORTA.PORTA3 3 Port A Data Register bit 3
|
||
PORTA.PORTA2 2 Port A Data Register bit 2
|
||
PORTA.PORTA1 1 Port A Data Register bit 1
|
||
PORTA.PORTA0 0 Port A Data Register bit 0
|
||
EECR 0x001C EEPROM Control Register
|
||
EECR.EERIE 3 EEPROM Ready Interrupt Enable
|
||
EECR.EEMWE 2 EEPROM Master Write Enable
|
||
EECR.EEWE 1 EEPROM Write Enable
|
||
EECR.EERE 0 EEPROM Read Enable
|
||
EEDR 0x001D EEPROM Data Register
|
||
EEAR 0x001E EEPROM Address Register
|
||
EEAR.EEAR7 7
|
||
EEAR.EEAR6 6
|
||
EEAR.EEAR5 5
|
||
EEAR.EEAR4 4
|
||
EEAR.EEAR3 3
|
||
EEAR.EEAR2 2
|
||
EEAR.EEAR1 1
|
||
EEAR.EEAR0 0
|
||
RESERVED001F 0x001F RESERVED
|
||
PCMSK 0x0020 Pin Change Mask Register 0
|
||
PCMSK.PCINT7 7 Pin Change Enable Mask 7
|
||
PCMSK.PCINT6 6 Pin Change Enable Mask 6
|
||
PCMSK.PCINT5 5 Pin Change Enable Mask 5
|
||
PCMSK.PCINT4 4 Pin Change Enable Mask 4
|
||
PCMSK.PCINT3 3 Pin Change Enable Mask 3
|
||
PCMSK.PCINT2 2 Pin Change Enable Mask 2
|
||
PCMSK.PCINT1 1 Pin Change Enable Mask 1
|
||
PCMSK.PCINT0 0 Pin Change Enable Mask 0
|
||
WDTCSR 0x0021 Watchdog Timer Control Register
|
||
WDTCSR.WDIF 7 Watchdog Interrupt Flag
|
||
WDTCSR.WDIE 6 Watchdog Interrupt Enable
|
||
WDTCSR.WDP3 5 Watchdog Timer Prescaler 3
|
||
WDTCSR.WDCE 4 Watchdog Change Enable
|
||
WDTCSR.WDE 3 Watchdog Enable
|
||
WDTCSR.WDP2 2 Watchdog Timer Prescaler 2
|
||
WDTCSR.WDP1 1 Watchdog Timer Prescaler 1
|
||
WDTCSR.WDP0 0 Watchdog Timer Prescaler 0
|
||
TCCR1C 0x0022 Timer/Counter1 Control Register C
|
||
TCCR1C.FOC1A 7 Force Output Compare for Channel A
|
||
TCCR1C.FOC1B 6 Force Output Compare for Channel B
|
||
GTCCR 0x0023 General Timer/Counter Control Register
|
||
GTCCR.PSR10 1 Prescaler Reset Timer/Counter1 and Timer/Counter0
|
||
ICR1L 0x0024 Input Capture Register Low Byte
|
||
ICR1H 0x0025 Input Capture Register High Byte
|
||
CLKPR 0x0026 Clock Prescale Register
|
||
CLKPR.CPCE 7 Clock Prescaler Change Enable
|
||
CLKPR.CLKPS3 3 Clock Prescaler Select Bit 3
|
||
CLKPR.CLKPS2 2 Clock Prescaler Select Bit 2
|
||
CLKPR.CLKPS1 1 Clock Prescaler Select Bit 1
|
||
CLKPR.CLKPS0 0 Clock Prescaler Select Bit 0
|
||
RESERVED0027 0x0027 RESERVED
|
||
OCR1BL 0x0028 Output Compare Register B Low Byte
|
||
OCR1BH 0x0029 Output Compare Register B High Byte
|
||
OCR1AL 0x002A Output Compare Register A Low Byte
|
||
OCR1AH 0x002B Output Compare Register A High Byte
|
||
TCNT1L 0x002C Counter Register Low Byte
|
||
TCNT1H 0x002D Counter Register High Byte
|
||
TCCR1B 0x002E Timer/Counter1 Control Register B
|
||
TCCR1B.ICNC1 7 Input Capture Noise Canceler
|
||
TCCR1B.ICES1 6 Input CaptureEdgeSelect
|
||
TCCR1B.WGM13 4 Waveform Generation Mode 3
|
||
TCCR1B.WGM12 3 Waveform Generation Mode 2
|
||
TCCR1B.CS12 2 Clock Select 2
|
||
TCCR1B.CS11 1 Clock Select 1
|
||
TCCR1B.CS10 0 Clock Select 0
|
||
TCCR1A 0x002F Timer/Counter1 Control Register A
|
||
TCCR1A.COM1A1 7 Compare Output Mode for Channel A 1
|
||
TCCR1A.COM1A0 6 Compare Output Mode for Channel A 0
|
||
TCCR1A.COM1B1 5 Compare Output Mode for Channel B 1
|
||
TCCR1A.COM1B0 4 Compare Output Mode for Channel B 0
|
||
TCCR1A.WGM11 1 Waveform Generation Mode 1
|
||
TCCR1A.WGM10 0 Waveform Generation Mode 0
|
||
TCCR0A 0x0030 Timer/Counter0 Control Register A
|
||
TCCR0A.COM0A1 7 Compare Output Mode for Channel A 1
|
||
TCCR0A.COM0A0 6 Compare Output Mode for Channel A 0
|
||
TCCR0A.COM0B1 5 Compare Output Mode for Channel B 1
|
||
TCCR0A.COM0B0 4 Compare Output Mode for Channel B 0
|
||
TCCR0A.WGM01 1 Waveform Generation Mode 1
|
||
TCCR0A.WGM00 0 Waveform Generation Mode 0
|
||
OSCCAL 0x0031 Oscillator Calibration Register
|
||
OSCCAL.CAL6 6 Oscillator Calibration Value 6
|
||
OSCCAL.CAL5 5 Oscillator Calibration Value 5
|
||
OSCCAL.CAL4 4 Oscillator Calibration Value 4
|
||
OSCCAL.CAL3 3 Oscillator Calibration Value 3
|
||
OSCCAL.CAL2 2 Oscillator Calibration Value 2
|
||
OSCCAL.CAL1 1 Oscillator Calibration Value 1
|
||
OSCCAL.CAL0 0 Oscillator Calibration Value 0
|
||
TCNT0 0x0032 Timer/Counter0
|
||
TCCR0B 0x0033 Timer/Counter Control Register
|
||
TCCR0B.FOC0A 7 Force Output Compare A
|
||
TCCR0B.FOC0B 6 Force Output Compare B
|
||
TCCR0B.WGM02 3 Waveform Generation Mode
|
||
TCCR0B.CS02 2 Clock Select 2
|
||
TCCR0B.CS01 1 Clock Select 1
|
||
TCCR0B.CS00 0 Clock Select 0
|
||
MCUCSR 0x0034 MCU Control and Status Register
|
||
MCUCSR.WDRF 3 Watchdog Reset Flag
|
||
MCUCSR.BORF 2 Brown-out Reset Flag
|
||
MCUCSR.EXTRF 1 External Reset Flag
|
||
MCUCSR.PORF 0 Power-On Reset Flag
|
||
MCUCR 0x0035 MCU Control Register
|
||
MCUCR.PUD 7 Pull-up Disable
|
||
MCUCR.SM1 6 Sleep Mode Select Bit 1
|
||
MCUCR.SE 5 SleepEnable
|
||
MCUCR.SM0 4 Sleep Mode Select Bit 0
|
||
MCUCR.ISC11 3 Interrupt Sense Control 1 Bit 1
|
||
MCUCR.ISC10 2 Interrupt Sense Control 1 Bit 0
|
||
MCUCR.ISC01 1 Interrupt Sense Control 0 Bit 1
|
||
MCUCR.ISC00 0 Interrupt Sense Control 0 Bit 0
|
||
OCR0A 0x0036 Timer/Counter0 Compare Register A
|
||
SPMCSR 0x0037 Store Program Memory Control Register
|
||
SPMCSR.CTPB 4 Clear Temporary Page Buffer
|
||
SPMCSR.RFLB 3 Read Fuse and Lock Bits
|
||
SPMCSR.PGWRT 2 Page Write
|
||
SPMCSR.PGERS 1 Page Erase
|
||
SPMCSR.SELFPRGEN 0 Self Programming Enable
|
||
TIFR 0x0038 Timer/Counter Interrupt Flag Register
|
||
TIFR.TOV1 7 Timer/Counter1 Overflow Flag
|
||
TIFR.OCF1A 6 Timer/Counter1, Output Compare A Match Flag
|
||
TIFR.OCF1B 5 Timer/Counter1, Output Compare B Match Flag
|
||
TIFR.ICF1 3 Timer/Counter1, Input Capture Flag
|
||
TIFR.OCF0B 2 Timer/Counter0, Output Compare B Match Flag
|
||
TIFR.TOV0 1 Timer/Counter0 Overflow Flag
|
||
TIFR.OCF0A 0 Timer/Counter0, Output Compare A Match Flag
|
||
TIMSK 0x0039 Timer/Counter Interrupt Mask Register
|
||
TIMSK.TOIE1 7 Timer/Counter1, Overflow Interrupt Enable
|
||
TIMSK.OCIE1A 6 Timer/Counter1, Output Compare A Match Interrupt Enable
|
||
TIMSK.OCIE1B 5 Timer/Counter1, Output Compare B Match Interrupt Enable
|
||
TIMSK.ICIE1 3 Timer/Counter1, Input Capture Interrupt Enable
|
||
TIMSK.OCIE0A 2 Timer/Counter0, Output Compare A Match Interrupt Enable
|
||
TIMSK.TOIE0 1 Timer/Counter0 Overflow Interrupt Enable
|
||
TIMSK.OCIE0B 0 Timer/Counter0, Output Compare B Match Interrupt Enable
|
||
EIFR 0x003A External Interrupt Flag Register
|
||
EIFR.INTF1 7 External Interrupt Flag 1
|
||
EIFR.INTF0 6 External Interrupt Flag 0
|
||
EIFR.PCIF 5 Pin Change Interrupt Flag
|
||
GIMSK 0x003B External Interrupt Mask Register
|
||
GIMSK.INT1 7 External Interrupt Request 1 Enable
|
||
GIMSK.INT0 6 External Interrupt Request 0 Enable
|
||
GIMSK.PCIE 5 Pin Change Interrupt Request Enable
|
||
OCR0B 0x003C Output Compare Register B Low Byte
|
||
SPL 0x003D Stack Pointer Register Low
|
||
SPL.SP7 7
|
||
SPL.SP6 6
|
||
SPL.SP5 5
|
||
SPL.SP4 4
|
||
SPL.SP3 3
|
||
SPL.SP2 2
|
||
SPL.SP1 1
|
||
SPL.SP0 0
|
||
RESERVED003E 0x003E RESERVED
|
||
SREG 0x003F Status Register
|
||
SREG.I 7 Global Interrupt Enable
|
||
SREG.T 6 Bit Copy Storage
|
||
SREG.H 5 Half Carry Flag
|
||
SREG.S 4 Sign Bit
|
||
SREG.V 3 Two's Complement Overflow Flag
|
||
SREG.N 2 Negative Flag
|
||
SREG.Z 1 Zero Flag
|
||
SREG.C 0 CarryFlag
|
||
|
||
|
||
.ATtiny2313A
|
||
SUBARCH=25
|
||
; doc8246.pdf
|
||
;
|
||
|
||
RAM=128
|
||
ROM=2048
|
||
EEPROM=128
|
||
|
||
|
||
; MEMORY MAP
|
||
area DATA GPWR_ 0x0000:0x0020 General Purpose Working Registers
|
||
area DATA FSR_ 0x0020:0x0060 I/O registers
|
||
area DATA I_SRAM 0x0060:0x00E0 Internal SRAM
|
||
|
||
|
||
; Interrupt and reset vector assignments
|
||
entry __RESET 0x0000 Hardware Pin
|
||
entry INT0_ 0x0001 External Interrupt Request 0
|
||
entry INT1_ 0x0002 External Interrupt Request 1
|
||
entry TIMER1_CAPT 0x0003 Timer/Counter1 Capture Event
|
||
entry TIMER1_COMPA 0x0004 Timer/Counter1 Compare Match A
|
||
entry TIMER1_OVF 0x0005 Timer/Counter1 Overflow
|
||
entry TIMER0_OVF 0x0006 Timer/Counter0 Overflow
|
||
entry USART0_RX 0x0007 USART0, Rx Complete
|
||
entry USART0_UDRE 0x0008 USART0 Data Register Empty
|
||
entry USART0_TX 0x0009 USART0, Tx Complete
|
||
entry ANALOG_COMP 0x000A Analog Comparator
|
||
entry PCINT0 0x000B Pin Change Interrupt Request 0
|
||
entry TIMER1_COMPB 0x000C Timer/Counter1 Compare Match B
|
||
entry TIMER0_COMPA 0x000D Timer/Counter0 Compare Match A
|
||
entry TIMER0_COMPB 0x000E Timer/Counter0 Compare Match B
|
||
entry USI_START 0x000F USI Start Condition
|
||
entry USI_OVERFLOW 0x0010 USI Overflow
|
||
entry EE_READY 0x0011 EEPROM Ready
|
||
entry WDT_OVERFLOW 0x0012 Watchdog Timer Overflow
|
||
entry PCINT1 0x0013 Pin Change Interrupt Request 1
|
||
entry PCINT2 0x0014 Pin Change Interrupt Request 2
|
||
|
||
|
||
; INPUT/OUTPUT PORTS
|
||
USIBR 0x0000 USI Buffer Register
|
||
DIDR 0x0001 Digital Input Disable Register
|
||
DIDR.AIND0 1 AIN0 Digital Input Disable
|
||
DIDR.AIND1 2 AIN1 Digital Input Disable
|
||
UBRRH 0x0002 USART Baud Rate Registers High
|
||
UCSRC 0x0003 USART Control and Status Register C
|
||
UCSRC.UMSEL1 7 USART Mode Select 1
|
||
UCSRC.UMSEL0 6 USART Mode Select 0
|
||
UCSRC.UPM1 5 Parity Mode 1
|
||
UCSRC.UPM0 4 Parity Mode 0
|
||
UCSRC.USBS 3 Stop Bit Select
|
||
UCSRC.UCSZ1 2 Character Size 1
|
||
UCSRC.UCSZ0 1 Character Size 0
|
||
UCSRC.UCPOL 0 Clock Polarity
|
||
PCMSK1 0x0004 Pin Change Mask Register 1
|
||
PCMSK1.PCINT10 2 Pin Change Enable Mask 10
|
||
PCMSK1.PCINT9 1 Pin Change Enable Mask 9
|
||
PCMSK1.PCINT8 0 Pin Change Enable Mask 8
|
||
PCMSK2 0x0005 Pin Change Mask Register 2
|
||
PCMSK2.PCINT17 6 Pin Change Enable Mask 17
|
||
PCMSK2.PCINT16 5 Pin Change Enable Mask 16
|
||
PCMSK2.PCINT15 4 Pin Change Enable Mask 15
|
||
PCMSK2.PCINT14 3 Pin Change Enable Mask 14
|
||
PCMSK2.PCINT13 2 Pin Change Enable Mask 13
|
||
PCMSK2.PCINT12 1 Pin Change Enable Mask 12
|
||
PCMSK2.PCINT11 0 Pin Change Enable Mask 11
|
||
PRR 0x0006 Power Reduction Register
|
||
PRR.PRTIM1 3 Power Reduction Timer/Counter1
|
||
PRR.PRTIM0 2 Power Reduction Timer/Counter0
|
||
PRR.PRUSI 1 Power Reduction USI
|
||
PRR.PRUSART 0 Power Reduction USART
|
||
BODCR 0x0007 Brown-Out Detector Control Register
|
||
BODCR.BODS 1 BOD Sleep
|
||
BODCR.BODSE 0 BOD Sleep Enable
|
||
ACSR 0x0008 Analog Comparator Control and Status Register
|
||
ACSR.ACD 7 Analog Comparator Disable
|
||
ACSR.ACBG 6 Analog Comparator Bandgap Select
|
||
ACSR.ACO 5 Analog Comparator Output
|
||
ACSR.ACI 4 Analog Comparator Interrupt Flag
|
||
ACSR.ACIE 3 Analog Comparator Interrupt Enable
|
||
ACSR.ACIC 2 Analog Comparator Input Capture Enable
|
||
ACSR.ACIS1 1 Analog Comparator Interrupt Mode Select 1
|
||
ACSR.ACIS0 0 Analog Comparator Interrupt Mode Select 0
|
||
UBRRL 0x0009 USART Baud Rate Register
|
||
UBRRL.UBRR7 7
|
||
UBRRL.UBRR6 6
|
||
UBRRL.UBRR5 5
|
||
UBRRL.UBRR4 4
|
||
UBRRL.UBRR3 3
|
||
UBRRL.UBRR2 2
|
||
UBRRL.UBRR1 1
|
||
UBRRL.UBRR0 0
|
||
UCSRB 0x000A USART Control and Status Register
|
||
UCSRB.RXCIE 7 RX Complete Interrupt Enable
|
||
UCSRB.TXCIE 6 TX Complete Interrupt Enable
|
||
UCSRB.UDRIE 5 USART Data Register Empty Interrupt Enable
|
||
UCSRB.RXEN 4 Receiver Enable
|
||
UCSRB.TXEN 3 Transmitter Enable
|
||
UCSRB.UCSZ2 2 Character Size
|
||
UCSRB.RXB8 1 Receive Data Bit 8
|
||
UCSRB.TXB8 0 Transmit Data Bit8
|
||
UCSRA 0x000B USART Control and Status Register
|
||
UCSRA.RXC 7 USART Receive Complete
|
||
UCSRA.TXC 6 USART Transmit Complete
|
||
UCSRA.UDRE 5 USART Data Register Empty
|
||
UCSRA.FE 4 Frame Error
|
||
UCSRA.DOR 3 Data OverRun
|
||
UCSRA.UPE 2 Parity Error
|
||
UCSRA.U2X 1 Double the USART Transmission Speed
|
||
UCSRA.MPCM 0 Multi-Processor Communication Mode
|
||
UDR 0x000C USART I/O Data Register
|
||
USICR 0x000D USI Control Register
|
||
USICR.USISIE 7 Start Condition Interrupt Enable
|
||
USICR.USIOIE 6 Counter Overflow Interrupt Enable
|
||
USICR.USIWM1 5 Wire Mode 1
|
||
USICR.USIWM0 4 Wire Mode 0
|
||
USICR.USICS1 3 Clock Source Select 1
|
||
USICR.USICS0 2 Clock Source Select 0
|
||
USICR.USICLK 1 Clock Strobe
|
||
USICR.USITC 0 Toggle Clock Port Pin
|
||
USISR 0x000E USI Status Register
|
||
USISR.USISIF 7 Start Condition Interrupt Flag
|
||
USISR.USIOIF 6 Counter Overflow Interrupt Flag
|
||
USISR.USIPF 5 Stop Condition Flag
|
||
USISR.USIDC 4 Data Output Collision
|
||
USISR.USICNT3 3 Counter Value 3
|
||
USISR.USICNT2 2 Counter Value 2
|
||
USISR.USICNT1 1 Counter Value 1
|
||
USISR.USICNT0 0 Counter Value 0
|
||
USIDR 0x000F USI Data Register
|
||
PIND 0x0010 Port D Input Pins Address
|
||
PIND.PIND7 7
|
||
PIND.PIND6 6
|
||
PIND.PIND5 5
|
||
PIND.PIND4 4
|
||
PIND.PIND3 3
|
||
PIND.PIND2 2
|
||
PIND.PIND1 1
|
||
PIND.PIND0 0
|
||
DDRD 0x0011 Port D Data Direction Register
|
||
DDRD.DDD7 7 Port D Data Direction Register bit 7
|
||
DDRD.DDD6 6 Port D Data Direction Register bit 6
|
||
DDRD.DDD5 5 Port D Data Direction Register bit 5
|
||
DDRD.DDD4 4 Port D Data Direction Register bit 4
|
||
DDRD.DDD3 3 Port D Data Direction Register bit 3
|
||
DDRD.DDD2 2 Port D Data Direction Register bit 2
|
||
DDRD.DDD1 1 Port D Data Direction Register bit 1
|
||
DDRD.DDD0 0 Port D Data Direction Register bit 0
|
||
PORTD 0x0012 Port D Data Register
|
||
PORTD.PORTD7 7 Port D Data Register bit 7
|
||
PORTD.PORTD6 6 Port D Data Register bit 6
|
||
PORTD.PORTD5 5 Port D Data Register bit 5
|
||
PORTD.PORTD4 4 Port D Data Register bit 4
|
||
PORTD.PORTD3 3 Port D Data Register bit 3
|
||
PORTD.PORTD2 2 Port D Data Register bit 2
|
||
PORTD.PORTD1 1 Port D Data Register bit 1
|
||
PORTD.PORTD0 0 Port D Data Register bit 0
|
||
GPIOR0 0x0013 General Purpose I/O Register 0
|
||
GPIOR1 0x0014 General Purpose I/O Register 0
|
||
GPIOR2 0x0015 General Purpose I/O Register 0
|
||
PINB 0x0016 Port B Input Pins Address
|
||
PINB.PINB7 7
|
||
PINB.PINB6 6
|
||
PINB.PINB5 5
|
||
PINB.PINB4 4
|
||
PINB.PINB3 3
|
||
PINB.PINB2 2
|
||
PINB.PINB1 1
|
||
PINB.PINB0 0
|
||
DDRB 0x0017 Port B Data Direction Register
|
||
DDRB.DDB7 7 Port B Data Direction Register bit 7
|
||
DDRB.DDB6 6 Port B Data Direction Register bit 6
|
||
DDRB.DDB5 5 Port B Data Direction Register bit 5
|
||
DDRB.DDB4 4 Port B Data Direction Register bit 4
|
||
DDRB.DDB3 3 Port B Data Direction Register bit 3
|
||
DDRB.DDB2 2 Port B Data Direction Register bit 2
|
||
DDRB.DDB1 1 Port B Data Direction Register bit 1
|
||
DDRB.DDB0 0 Port B Data Direction Register bit 0
|
||
PORTB 0x0018 Port B Data Register
|
||
PORTB.PORTB7 7 Port B Data Register bit 7
|
||
PORTB.PORTB6 6 Port B Data Register bit 6
|
||
PORTB.PORTB5 5 Port B Data Register bit 5
|
||
PORTB.PORTB4 4 Port B Data Register bit 4
|
||
PORTB.PORTB3 3 Port B Data Register bit 3
|
||
PORTB.PORTB2 2 Port B Data Register bit 2
|
||
PORTB.PORTB1 1 Port B Data Register bit 1
|
||
PORTB.PORTB0 0 Port B Data Register bit 0
|
||
PINA 0x0019 Port A Input Pins Address
|
||
PINA.PINA7 7
|
||
PINA.PINA6 6
|
||
PINA.PINA5 5
|
||
PINA.PINA4 4
|
||
PINA.PINA3 3
|
||
PINA.PINA2 2
|
||
PINA.PINA1 1
|
||
PINA.PINA0 0
|
||
DDRA 0x001A Port A Data Direction Register
|
||
DDRA.DDA7 7 Port A Data Direction Register bit 7
|
||
DDRA.DDA6 6 Port A Data Direction Register bit 6
|
||
DDRA.DDA5 5 Port A Data Direction Register bit 5
|
||
DDRA.DDA4 4 Port A Data Direction Register bit 4
|
||
DDRA.DDA3 3 Port A Data Direction Register bit 3
|
||
DDRA.DDA2 2 Port A Data Direction Register bit 2
|
||
DDRA.DDA1 1 Port A Data Direction Register bit 1
|
||
DDRA.DDA0 0 Port A Data Direction Register bit 0
|
||
PORTA 0x001B Port A Data Register
|
||
PORTA.PORTA7 7 Port A Data Register bit 7
|
||
PORTA.PORTA6 6 Port A Data Register bit 6
|
||
PORTA.PORTA5 5 Port A Data Register bit 5
|
||
PORTA.PORTA4 4 Port A Data Register bit 4
|
||
PORTA.PORTA3 3 Port A Data Register bit 3
|
||
PORTA.PORTA2 2 Port A Data Register bit 2
|
||
PORTA.PORTA1 1 Port A Data Register bit 1
|
||
PORTA.PORTA0 0 Port A Data Register bit 0
|
||
EECR 0x001C EEPROM Control Register
|
||
EECR.EERIE 3 EEPROM Ready Interrupt Enable
|
||
EECR.EEMWE 2 EEPROM Master Write Enable
|
||
EECR.EEWE 1 EEPROM Write Enable
|
||
EECR.EERE 0 EEPROM Read Enable
|
||
EEDR 0x001D EEPROM Data Register
|
||
EEAR 0x001E EEPROM Address Register
|
||
EEAR.EEAR7 7
|
||
EEAR.EEAR6 6
|
||
EEAR.EEAR5 5
|
||
EEAR.EEAR4 4
|
||
EEAR.EEAR3 3
|
||
EEAR.EEAR2 2
|
||
EEAR.EEAR1 1
|
||
EEAR.EEAR0 0
|
||
RESERVED001F 0x001F RESERVED
|
||
PCMSK0 0x0020 Pin Change Mask Register 0
|
||
PCMSK0.PCINT7 7 Pin Change Enable Mask 7
|
||
PCMSK0.PCINT6 6 Pin Change Enable Mask 6
|
||
PCMSK0.PCINT5 5 Pin Change Enable Mask 5
|
||
PCMSK0.PCINT4 4 Pin Change Enable Mask 4
|
||
PCMSK0.PCINT3 3 Pin Change Enable Mask 3
|
||
PCMSK0.PCINT2 2 Pin Change Enable Mask 2
|
||
PCMSK0.PCINT1 1 Pin Change Enable Mask 1
|
||
PCMSK0.PCINT0 0 Pin Change Enable Mask 0
|
||
WDTCSR 0x0021 Watchdog Timer Control Register
|
||
WDTCSR.WDIF 7 Watchdog Interrupt Flag
|
||
WDTCSR.WDIE 6 Watchdog Interrupt Enable
|
||
WDTCSR.WDP3 5 Watchdog Timer Prescaler 3
|
||
WDTCSR.WDCE 4 Watchdog Change Enable
|
||
WDTCSR.WDE 3 Watchdog Enable
|
||
WDTCSR.WDP2 2 Watchdog Timer Prescaler 2
|
||
WDTCSR.WDP1 1 Watchdog Timer Prescaler 1
|
||
WDTCSR.WDP0 0 Watchdog Timer Prescaler 0
|
||
TCCR1C 0x0022 Timer/Counter1 Control Register C
|
||
TCCR1C.FOC1A 7 Force Output Compare for Channel A
|
||
TCCR1C.FOC1B 6 Force Output Compare for Channel B
|
||
GTCCR 0x0023 General Timer/Counter Control Register
|
||
GTCCR.PSR10 1 Prescaler Reset Timer/Counter1 and Timer/Counter0
|
||
ICR1L 0x0024 Input Capture Register Low Byte
|
||
ICR1H 0x0025 Input Capture Register High Byte
|
||
CLKPR 0x0026 Clock Prescale Register
|
||
CLKPR.CPCE 7 Clock Prescaler Change Enable
|
||
CLKPR.CLKPS3 3 Clock Prescaler Select Bit 3
|
||
CLKPR.CLKPS2 2 Clock Prescaler Select Bit 2
|
||
CLKPR.CLKPS1 1 Clock Prescaler Select Bit 1
|
||
CLKPR.CLKPS0 0 Clock Prescaler Select Bit 0
|
||
RESERVED0027 0x0027 RESERVED
|
||
OCR1BL 0x0028 Output Compare Register B Low Byte
|
||
OCR1BH 0x0029 Output Compare Register B High Byte
|
||
OCR1AL 0x002A Output Compare Register A Low Byte
|
||
OCR1AH 0x002B Output Compare Register A High Byte
|
||
TCNT1L 0x002C Counter Register Low Byte
|
||
TCNT1H 0x002D Counter Register High Byte
|
||
TCCR1B 0x002E Timer/Counter1 Control Register B
|
||
TCCR1B.ICNC1 7 Input Capture Noise Canceler
|
||
TCCR1B.ICES1 6 Input CaptureEdgeSelect
|
||
TCCR1B.WGM13 4 Waveform Generation Mode 3
|
||
TCCR1B.WGM12 3 Waveform Generation Mode 2
|
||
TCCR1B.CS12 2 Clock Select 2
|
||
TCCR1B.CS11 1 Clock Select 1
|
||
TCCR1B.CS10 0 Clock Select 0
|
||
TCCR1A 0x002F Timer/Counter1 Control Register A
|
||
TCCR1A.COM1A1 7 Compare Output Mode for Channel A 1
|
||
TCCR1A.COM1A0 6 Compare Output Mode for Channel A 0
|
||
TCCR1A.COM1B1 5 Compare Output Mode for Channel B 1
|
||
TCCR1A.COM1B0 4 Compare Output Mode for Channel B 0
|
||
TCCR1A.WGM11 1 Waveform Generation Mode 1
|
||
TCCR1A.WGM10 0 Waveform Generation Mode 0
|
||
TCCR0A 0x0030 Timer/Counter0 Control Register A
|
||
TCCR0A.COM0A1 7 Compare Output Mode for Channel A 1
|
||
TCCR0A.COM0A0 6 Compare Output Mode for Channel A 0
|
||
TCCR0A.COM0B1 5 Compare Output Mode for Channel B 1
|
||
TCCR0A.COM0B0 4 Compare Output Mode for Channel B 0
|
||
TCCR0A.WGM01 1 Waveform Generation Mode 1
|
||
TCCR0A.WGM00 0 Waveform Generation Mode 0
|
||
OSCCAL 0x0031 Oscillator Calibration Register
|
||
OSCCAL.CAL6 6 Oscillator Calibration Value 6
|
||
OSCCAL.CAL5 5 Oscillator Calibration Value 5
|
||
OSCCAL.CAL4 4 Oscillator Calibration Value 4
|
||
OSCCAL.CAL3 3 Oscillator Calibration Value 3
|
||
OSCCAL.CAL2 2 Oscillator Calibration Value 2
|
||
OSCCAL.CAL1 1 Oscillator Calibration Value 1
|
||
OSCCAL.CAL0 0 Oscillator Calibration Value 0
|
||
TCNT0 0x0032 Timer/Counter0
|
||
TCCR0B 0x0033 Timer/Counter Control Register
|
||
TCCR0B.FOC0A 7 Force Output Compare A
|
||
TCCR0B.FOC0B 6 Force Output Compare B
|
||
TCCR0B.WGM02 3 Waveform Generation Mode
|
||
TCCR0B.CS02 2 Clock Select 2
|
||
TCCR0B.CS01 1 Clock Select 1
|
||
TCCR0B.CS00 0 Clock Select 0
|
||
MCUCSR 0x0034 MCU Control and Status Register
|
||
MCUCSR.WDRF 3 Watchdog Reset Flag
|
||
MCUCSR.BORF 2 Brown-out Reset Flag
|
||
MCUCSR.EXTRF 1 External Reset Flag
|
||
MCUCSR.PORF 0 Power-On Reset Flag
|
||
MCUCR 0x0035 MCU Control Register
|
||
MCUCR.PUD 7 Pull-up Disable
|
||
MCUCR.SM1 6 Sleep Mode Select Bit 1
|
||
MCUCR.SE 5 SleepEnable
|
||
MCUCR.SM0 4 Sleep Mode Select Bit 0
|
||
MCUCR.ISC11 3 Interrupt Sense Control 1 Bit 1
|
||
MCUCR.ISC10 2 Interrupt Sense Control 1 Bit 0
|
||
MCUCR.ISC01 1 Interrupt Sense Control 0 Bit 1
|
||
MCUCR.ISC00 0 Interrupt Sense Control 0 Bit 0
|
||
OCR0A 0x0036 Timer/Counter0 Compare Register A
|
||
SPMCSR 0x0037 Store Program Memory Control Register
|
||
SPMCSR.RSIG 5 Read Device Signature Imprint Table
|
||
SPMCSR.CTPB 4 Clear Temporary Page Buffer
|
||
SPMCSR.RFLB 3 Read Fuse and Lock Bits
|
||
SPMCSR.PGWRT 2 Page Write
|
||
SPMCSR.PGERS 1 Page Erase
|
||
SPMCSR.SPMEN 0 Self Programming Enable
|
||
TIFR 0x0038 Timer/Counter Interrupt Flag Register
|
||
TIFR.TOV1 7 Timer/Counter1 Overflow Flag
|
||
TIFR.OCF1A 6 Timer/Counter1, Output Compare A Match Flag
|
||
TIFR.OCF1B 5 Timer/Counter1, Output Compare B Match Flag
|
||
TIFR.ICF1 3 Timer/Counter1, Input Capture Flag
|
||
TIFR.OCF0B 2 Timer/Counter0, Output Compare B Match Flag
|
||
TIFR.TOV0 1 Timer/Counter0 Overflow Flag
|
||
TIFR.OCF0A 0 Timer/Counter0, Output Compare A Match Flag
|
||
TIMSK 0x0039 Timer/Counter Interrupt Mask Register
|
||
TIMSK.TOIE1 7 Timer/Counter1, Overflow Interrupt Enable
|
||
TIMSK.OCIE1A 6 Timer/Counter1, Output Compare A Match Interrupt Enable
|
||
TIMSK.OCIE1B 5 Timer/Counter1, Output Compare B Match Interrupt Enable
|
||
TIMSK.ICIE1 3 Timer/Counter1, Input Capture Interrupt Enable
|
||
TIMSK.OCIE0A 2 Timer/Counter0, Output Compare A Match Interrupt Enable
|
||
TIMSK.TOIE0 1 Timer/Counter0 Overflow Interrupt Enable
|
||
TIMSK.OCIE0B 0 Timer/Counter0, Output Compare B Match Interrupt Enable
|
||
EIFR 0x003A External Interrupt Flag Register
|
||
EIFR.INTF1 7 External Interrupt Flag 1
|
||
EIFR.INTF0 6 External Interrupt Flag 0
|
||
EIFR.PCIF0 5 Pin Change Interrupt Flag 0
|
||
EIFR.PCIF2 4 Pin Change Interrupt Flag 2
|
||
EIFR.PCIF1 3 Pin Change Interrupt Flag 1
|
||
GIMSK 0x003B External Interrupt Mask Register
|
||
GIMSK.INT1 7 External Interrupt Request 1 Enable
|
||
GIMSK.INT0 6 External Interrupt Request 0 Enable
|
||
GIMSK.PCIE0 5 Pin Change Interrupt Request Enable 0
|
||
GIMSL.PCIE2 4 Pin Change Interrupt Request Enable 2
|
||
GIMSL.PCIE1 3 Pin Change Interrupt Request Enable 1
|
||
OCR0B 0x003C Output Compare Register B Low Byte
|
||
SPL 0x003D Stack Pointer Register Low
|
||
SPL.SP7 7
|
||
SPL.SP6 6
|
||
SPL.SP5 5
|
||
SPL.SP4 4
|
||
SPL.SP3 3
|
||
SPL.SP2 2
|
||
SPL.SP1 1
|
||
SPL.SP0 0
|
||
RESERVED003E 0x003E RESERVED
|
||
SREG 0x003F Status Register
|
||
SREG.I 7 Global Interrupt Enable
|
||
SREG.T 6 Bit Copy Storage
|
||
SREG.H 5 Half Carry Flag
|
||
SREG.S 4 Sign Bit
|
||
SREG.V 3 Two's Complement Overflow Flag
|
||
SREG.N 2 Negative Flag
|
||
SREG.Z 1 Zero Flag
|
||
SREG.C 0 CarryFlag
|