257 lines
25 KiB
C++
257 lines
25 KiB
C++
/*
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* Interactive disassembler (IDA).
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* Copyright (c) 1990-98 by Ilfak Guilfanov.
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* ALL RIGHTS RESERVED.
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* E-mail: ig@estar.msk.su
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* FIDO: 2:5020/209
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*
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*
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* TMS320C6xx - VLIW (very long instruction word) architecture
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*
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*/
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#include "tms6.hpp"
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const instruc_t Instructions[] =
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{
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// Original TMS320C62x instructions
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{ "", 0 }, // Unknown Operation
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{ "ABS", CF_USE1|CF_CHG2 }, // Absolute value
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{ "ADD", CF_USE1|CF_USE2|CF_CHG3 }, // Integer addition without saturation (signed)
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{ "ADDU", CF_USE1|CF_USE2|CF_CHG3 }, // Integer addition without saturation (unsigned)
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{ "ADDAB", CF_USE1|CF_USE2|CF_CHG3 }, // Integer addition using addressing mode (byte)
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{ "ADDAH", CF_USE1|CF_USE2|CF_CHG3 }, // Integer addition using addressing mode (halfword)
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{ "ADDAW", CF_USE1|CF_USE2|CF_CHG3 }, // Integer addition using addressing mode (word)
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{ "ADDK", CF_USE1|CF_CHG2 }, // Integer addition 16bit signed constant
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{ "ADD2", CF_USE1|CF_USE2|CF_CHG3 }, // Two 16bit Integer adds on register halves
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{ "AND", CF_USE1|CF_USE2|CF_CHG3 }, // Logical AND
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{ "B", CF_USE1 }, // Branch
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{ "CLR", CF_USE1|CF_USE2|CF_CHG3 }, // Clear a bit field
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{ "CMPEQ", CF_USE1|CF_USE2|CF_CHG3 }, // Compare for equality
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{ "CMPGT", CF_USE1|CF_USE2|CF_CHG3 }, // Compare for greater than (signed)
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{ "CMPGTU", CF_USE1|CF_USE2|CF_CHG3 }, // Compare for greater than (unsigned)
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{ "CMPLT", CF_USE1|CF_USE2|CF_CHG3 }, // Compare for less than (signed)
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{ "CMPLTU", CF_USE1|CF_USE2|CF_CHG3 }, // Compare for less than (unsigned)
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{ "EXT", CF_USE1|CF_USE2|CF_CHG3 }, // Extract and sign-extend a bit filed
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{ "EXTU", CF_USE1|CF_USE2|CF_CHG3 }, // Extract an unsigned bit field
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{ "IDLE", CF_STOP }, // Multicycle NOP with no termination until interrupt
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{ "LDB", CF_USE1|CF_CHG2 }, // Load from memory (signed 8bit)
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{ "LDBU", CF_USE1|CF_CHG2 }, // Load from memory (unsigned 8bit)
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{ "LDH", CF_USE1|CF_CHG2 }, // Load from memory (signed 16bit)
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{ "LDHU", CF_USE1|CF_CHG2 }, // Load from memory (unsigned 16bit)
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{ "LDW", CF_USE1|CF_CHG2 }, // Load from memory (32bit)
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{ "LMBD", CF_USE1|CF_USE2|CF_CHG3 }, // Leftmost bit detection
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{ "MPY", CF_USE1|CF_USE2|CF_CHG3 }, // Signed Integer Multiply (LSB16 x LSB16)
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{ "MPYU", CF_USE1|CF_USE2|CF_CHG3 }, // Unsigned Integer Multiply (LSB16 x LSB16)
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{ "MPYUS", CF_USE1|CF_USE2|CF_CHG3 }, // Integer Multiply Signed*Unsigned (LSB16 x LSB16)
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{ "MPYSU", CF_USE1|CF_USE2|CF_CHG3 }, // Integer Multiply Unsigned*Signed (LSB16 x LSB16)
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{ "MPYH", CF_USE1|CF_USE2|CF_CHG3 }, // Signed Integer Multiply (MSB16 x MSB16)
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{ "MPYHU", CF_USE1|CF_USE2|CF_CHG3 }, // Unsigned Integer Multiply (MSB16 x MSB16)
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{ "MPYHUS", CF_USE1|CF_USE2|CF_CHG3 }, // Integer Multiply Unsigned*Signed (MSB16 x MSB16)
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{ "MPYHSU", CF_USE1|CF_USE2|CF_CHG3 }, // Integer Multiply Signed*Unsigned (MSB16 x MSB16)
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{ "MPYHL", CF_USE1|CF_USE2|CF_CHG3 }, // Signed Integer Multiply (MSB16 x LSB16)
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{ "MPYHLU", CF_USE1|CF_USE2|CF_CHG3 }, // Unsigned Integer Multiply (MSB16 x LSB16)
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{ "MPYHULS", CF_USE1|CF_USE2|CF_CHG3 }, // Integer Multiply Signed*Unsigned (MSB16 x LSB16)
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{ "MPYHSLU", CF_USE1|CF_USE2|CF_CHG3 }, // Integer Multiply Unsigned*Signed (MSB16 x LSB16)
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{ "MPYLH", CF_USE1|CF_USE2|CF_CHG3 }, // Signed Integer Multiply (LSB16 x MB16)
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{ "MPYLHU", CF_USE1|CF_USE2|CF_CHG3 }, // Unsigned Integer Multiply (LSB16 x MSB16)
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{ "MPYLUHS", CF_USE1|CF_USE2|CF_CHG3 }, // Integer Multiply Signed*Unsigned (LSB16 x MSB16)
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{ "MPYLSHU", CF_USE1|CF_USE2|CF_CHG3 }, // Integer Multiply Unsigned*Signed (LSB16 x MSB16)
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{ "MV", CF_USE1|CF_CHG2 }, // Move from register to register
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{ "MVC", CF_USE1|CF_CHG2 }, // Move between the control file & register file
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{ "MVK", CF_USE1|CF_CHG2 }, // Move a 16bit signed constant into register
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{ "MVKH", CF_USE1|CF_CHG2 }, // Move a 16bit constant into the upper bits of a register
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{ "MVKLH", CF_USE1|CF_CHG2 }, // Move a 16bit constant into the upper bits of a register
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{ "NEG", CF_USE1|CF_CHG2 }, // Negate
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{ "NOP", CF_USE1 }, // No operation
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{ "NORM", CF_USE1|CF_CHG2 }, // Normalize
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{ "NOT", CF_USE1|CF_CHG2 }, // Bitwise NOT
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{ "OR", CF_USE1|CF_USE2|CF_CHG3 }, // Logical or
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{ "SADD", CF_USE1|CF_USE2|CF_CHG3 }, // Integer addition with saturation
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{ "SAT", CF_USE1|CF_CHG2 }, // Saturate 40bit value to 32bits
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{ "SET", CF_USE1|CF_USE2|CF_CHG3 }, // Set a bit field
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{ "SHL", CF_USE1|CF_USE2|CF_CHG3 }, // Arithmetic shift left
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{ "SHR", CF_USE1|CF_USE2|CF_CHG3 }, // Arithmetic shift right
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{ "SHRU", CF_USE1|CF_USE2|CF_CHG3 }, // Logical shift left
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{ "SMPY", CF_USE1|CF_USE2|CF_CHG3 }, // Integer multiply with left shift & saturation (LSB16*LSB16)
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{ "SMPYHL", CF_USE1|CF_USE2|CF_CHG3 }, // Integer multiply with left shift & saturation (MSB16*LSB16)
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{ "SMPYLH", CF_USE1|CF_USE2|CF_CHG3 }, // Integer multiply with left shift & saturation (LSB16*MSB16)
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{ "SMPYH", CF_USE1|CF_USE2|CF_CHG3 }, // Integer multiply with left shift & saturation (MSB16*MSB16)
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{ "SSHL", CF_USE1|CF_USE2|CF_CHG3 }, // Shift left with saturation
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{ "SSUB", CF_USE1|CF_USE2|CF_CHG3 }, // Integer substraction with saturation
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{ "STB", CF_USE1|CF_CHG2 }, // Store to memory (signed 8bit)
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{ "STBU", CF_USE1|CF_CHG2 }, // Store to memory (unsigned 8bit)
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{ "STH", CF_USE1|CF_CHG2 }, // Store to memory (signed 16bit)
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{ "STHU", CF_USE1|CF_CHG2 }, // Store to memory (unsigned 16bit)
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{ "STW", CF_USE1|CF_CHG2 }, // Store to memory (32bit)
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{ "SUB", CF_USE1|CF_USE2|CF_CHG3 }, // Integer substaraction without saturation (signed)
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{ "SUBU", CF_USE1|CF_USE2|CF_CHG3 }, // Integer substaraction without saturation (unsigned)
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{ "SUBAB", CF_USE1|CF_USE2|CF_CHG3 }, // Integer subtraction using addressing mode (byte)
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{ "SUBAH", CF_USE1|CF_USE2|CF_CHG3 }, // Integer subtraction using addressing mode (halfword)
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{ "SUBAW", CF_USE1|CF_USE2|CF_CHG3 }, // Integer subtraction using addressing mode (word)
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{ "SUBC", CF_USE1|CF_USE2|CF_CHG3 }, // Conditional subtract & shift (for division)
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{ "SUB2", CF_USE1|CF_USE2|CF_CHG3 }, // Two 16bit integer subtractions on register halves
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{ "XOR", CF_USE1|CF_USE2|CF_CHG3 }, // Exclusive OR
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{ "ZERO", CF_CHG1 }, // Zero a register
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// New TMS320C674x instructions
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{ "ABS2", CF_USE1|CF_CHG2 }, // Absolute Value With Saturation, Signed, Packed 16-bit
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{ "ABSDP", CF_USE1|CF_CHG2 }, // Absolute Value, Double-Precision Floating-Point
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{ "ABSSP", CF_USE1|CF_CHG2 }, // Absolute Value, Single-Precision Floating-Point
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{ "ADD4", CF_USE1|CF_USE2|CF_CHG3 }, // Add Without Saturation, Four 8-Bit Pairs for Four 8-Bit Results
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{ "ADDAD", CF_USE1|CF_USE2|CF_CHG3 }, // Add Using Doubleword Addressing Mode
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{ "ADDDP", CF_USE1|CF_USE2|CF_CHG3 }, // Add Two Double-Precision Floating-Point Values
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{ "ADDKPC", CF_USE1|CF_CHG2|CF_USE3 }, // Add Signed 7-bit Constant to Program Counter
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{ "ADDSP", CF_USE1|CF_USE2|CF_CHG3 }, // Add Two Single-Precision Floating-Point Values
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{ "ADDSUB", CF_USE1|CF_USE2|CF_CHG3 }, // Parallel ADD and SUB Operations On Common Inputs
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{ "ADDSUB2", CF_USE1|CF_USE2|CF_CHG3 }, // Parallel ADD2 and SUB2 Operations On Common Inputs
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{ "ANDN", CF_USE1|CF_USE2|CF_CHG3 }, // Bitwise AND Invert
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{ "AVG2", CF_USE1|CF_USE2|CF_CHG3 }, // Average, Signed, Packed 16-bit
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{ "AVGU4", CF_USE1|CF_USE2|CF_CHG3 }, // Average, Unsigned, Packed 16-bit
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{ "BDEC", CF_USE1|CF_CHG2 }, // Branch and Decrement
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{ "BITC4", CF_USE1|CF_CHG2 }, // Bit Count, Packed 8-bit
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{ "BITR", CF_USE1|CF_CHG2 }, // Bit Reverse
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{ "BNOP", CF_USE1|CF_USE2 }, // Branch With NOP
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{ "BPOS", CF_USE1|CF_CHG2 }, // Branch Positive
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{ "CALLP", CF_USE1|CF_CHG2 }, // Call Using a Displacement
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{ "CMPEQ2", CF_USE1|CF_USE2|CF_CHG3 }, // Compare for Equality, Packed 16-bit
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{ "CMPEQ4", CF_USE1|CF_USE2|CF_CHG3 }, // Compare for Equality, Packed 8-bit
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{ "CMPEQDP", CF_USE1|CF_USE2|CF_CHG3 }, // Compare for Equality, Double-Precision Floating-Point Values
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{ "CMPEQSP", CF_USE1|CF_USE2|CF_CHG3 }, // Compare for Equality, Single-Precision Floating-Point Values
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{ "CMPGT2", CF_USE1|CF_USE2|CF_CHG3 }, // Compare for Greater Than, Packed 16-bit
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{ "CMPGTDP", CF_USE1|CF_USE2|CF_CHG3 }, // Compare for Greater Than, Double-Precision Floating-Point Values
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{ "CMPGTSP", CF_USE1|CF_USE2|CF_CHG3 }, // Compare for Greater Than, Single-Precision Floating-Point Values
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{ "CMPGTU4", CF_USE1|CF_USE2|CF_CHG3 }, // Compare for Greater Than, Unsigned, Packed 8-bit
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{ "CMPLT2", CF_USE1|CF_USE2|CF_CHG3 }, // Compare for Less Than, Packed 16-bit
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{ "CMPLTDP", CF_USE1|CF_USE2|CF_CHG3 }, // Compare for Less Than, Double-Precision Floating-Point Values
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{ "CMPLTSP", CF_USE1|CF_USE2|CF_CHG3 }, // Compare for Less Than, Single-Precision Floating-Point Values
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{ "CMPLTU4", CF_USE1|CF_USE2|CF_CHG3 }, // Compare for Less Than, Unsigned, Packed 8-bit
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{ "CMPY", CF_USE1|CF_USE2|CF_CHG3 }, // Complex Multiply Two Pairs, Signed, Packed 16-bit
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{ "CMPYR", CF_USE1|CF_USE2|CF_CHG3 }, // Complex Multiply Two Pairs, Signed, Packed 16-bit With Rounding
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{ "CMPYR1", CF_USE1|CF_USE2|CF_CHG3 }, // Complex Multiply Two Pairs, Signed, Packed 16-bit With Rounding
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{ "DDOTP4", CF_USE1|CF_USE2|CF_CHG3 }, // Double Dot Product, Signed, Packed 16-Bit and Signed, Packed 8-Bit
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{ "DDOTPH2", CF_USE1|CF_USE2|CF_CHG3 }, // Double Dot Product, Two Pairs, Signed, Packed 16-Bit
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{ "DDOTPH2R", CF_USE1|CF_USE2|CF_CHG3 }, // Double Dot Product With Rounding, Two Pairs, Signed, Packed 16-Bit
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{ "DDOTPL2", CF_USE1|CF_USE2|CF_CHG3 }, // Double Dot Product, Two Pairs, Signed, Packed 16-Bit
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{ "DDOTPL2R", CF_USE1|CF_USE2|CF_CHG3 }, // Double Dot Product With Rounding, Two Pairs, Signed Packed 16-Bit
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{ "DEAL", CF_USE1|CF_CHG2 }, // Deinterleave and Pack
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{ "DINT", 0 }, // Disable Interrupts and Save Previous Enable State
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{ "DMV", CF_USE1|CF_USE2|CF_CHG3 }, // Move Two Independent Registers to Register Pair
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{ "DOTP2", CF_USE1|CF_USE2|CF_CHG3 }, // Dot Product, Signed, Packed 16-Bit
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{ "DOTPN2", CF_USE1|CF_USE2|CF_CHG3 }, // Dot Product With Negate, Signed, Packed 16-Bit
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{ "DOTPNRSU2", CF_USE1|CF_USE2|CF_CHG3 }, // Dot Product With Negate, Shift and Round, Signed by Unsigned, Packed 16-Bit
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{ "DOTPNRUS2", CF_USE1|CF_USE2|CF_CHG3 }, // Dot Product With Negate, Shift and Round, Unsigned by Signed, Packed 16-Bit
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{ "DOTPRSU2", CF_USE1|CF_USE2|CF_CHG3 }, // Dot Product With Shift and Round, Signed by Unsigned, Packed 16-Bit
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{ "DOTPRUS2", CF_USE1|CF_USE2|CF_CHG3 }, // Dot Product With Shift and Round, Unsigned by Signed, Packed 16-Bit
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{ "DOTPSU4", CF_USE1|CF_USE2|CF_CHG3 }, // Dot Product, Signed by Unsigned, Packed 8-Bit
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{ "DOTPU4", CF_USE1|CF_USE2|CF_CHG3 }, // Dot Product, Unsigned, Packed 8-Bit
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{ "DOTPUS4", CF_USE1|CF_USE2|CF_CHG3 }, // Dot Product, Unsigned by Signed, Packed 8-Bit
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{ "DPACK2", CF_USE1|CF_USE2|CF_CHG3 }, // Parallel PACK2 and PACKH2 Operations
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{ "DPACKX2", CF_USE1|CF_USE2|CF_CHG3 }, // Parallel PACKLH2 Operations
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{ "DPINT", CF_USE1|CF_CHG2 }, // Convert Double-Precision Floating-Point Value to Integer
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{ "DPSP", CF_USE1|CF_CHG2 }, // Convert Double-Precision Floating-Point Value to Single-Precision Floating-Point Value
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{ "DPTRUNC", CF_USE1|CF_CHG2 }, // Convert Double-Precision Floating-Point Value to Integer With Truncation
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{ "GMPY", CF_USE1|CF_USE2|CF_CHG3 }, // Galois Field Multiply
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{ "GMPY4", CF_USE1|CF_USE2|CF_CHG3 }, // Galois Field Multiply, Packed 8-Bit
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{ "INTDP", CF_USE1|CF_CHG2 }, // Convert Signed Integer to Double-Precision Floating-Point Value
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{ "INTDPU", CF_USE1|CF_CHG2 }, // Convert Unsigned Integer to Double-Precision Floating-Point Value
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{ "INTSP", CF_USE1|CF_CHG2 }, // Convert Signed Integer to Single-Precision Floating-Point Value
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{ "INTSPU", CF_USE1|CF_CHG2 }, // Convert Unsigned Integer to Single-Precision Floating-Point Value
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{ "LDDW", CF_USE1|CF_CHG2 }, // Load Doubleword From Memory With a 5-Bit Unsigned Constant Offset or Register Offset
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{ "LDNDW", CF_USE1|CF_CHG2 }, // Load Nonaligned Doubleword From Memory With Constant or Register Offset
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{ "LDNW", CF_USE1|CF_CHG2 }, // Load Nonaligned Word From Memory With Constant or Register Offset
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{ "MAX2", CF_USE1|CF_USE2|CF_CHG3 }, // Maximum, Signed, Packed 16-Bit
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{ "MAXU4", CF_USE1|CF_USE2|CF_CHG3 }, // Maximum, Unsigned, Packed 8-Bit
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{ "MIN2", CF_USE1|CF_USE2|CF_CHG3 }, // Minimum, Signed, Packed 16-Bit
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{ "MINU4", CF_USE1|CF_USE2|CF_CHG3 }, // Minimum, Unsigned, Packed 8-Bit
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{ "MPY2", CF_USE1|CF_USE2|CF_CHG3 }, // Multiply Signed by Signed, 16 LSB x 16 LSB and 16 MSB x 16 MSB
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{ "MPY2IR", CF_USE1|CF_USE2|CF_CHG3 }, // Multiply Two 16-Bit x 32-Bit, Shifted by 15 to Produce a Rounded 32-Bit Result
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{ "MPY32", CF_USE1|CF_USE2|CF_CHG3 }, // Multiply Signed 32-Bit x Signed 32-Bit Into 32-Bit Result
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{ "MPY32SU", CF_USE1|CF_USE2|CF_CHG3 }, // Multiply Signed 32-Bit x Unsigned 32-Bit Into Signed 64-Bit Result
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{ "MPY32U", CF_USE1|CF_USE2|CF_CHG3 }, // Multiply Unsigned 32-Bit x Unsigned 32-Bit Into Unsigned 64-Bit Result
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{ "MPY32US", CF_USE1|CF_USE2|CF_CHG3 }, // Multiply Unsigned 32-Bit x Signed 32-Bit Into Signed 64-Bit Result
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{ "MPYDP", CF_USE1|CF_USE2|CF_CHG3 }, // Multiply Two Double-Precision Floating-Point Values
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{ "MPYHI", CF_USE1|CF_USE2|CF_CHG3 }, // Multiply 16 MSB x 32-Bit Into 64-Bit Result
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{ "MPYHIR", CF_USE1|CF_USE2|CF_CHG3 }, // Multiply 16 MSB x 32-Bit, Shifted by 15 to Produce a Rounded 32-Bit Result
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{ "MPYI", CF_USE1|CF_USE2|CF_CHG3 }, // Multiply 32-Bit x 32-Bit Into 32-Bit Result
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{ "MPYID", CF_USE1|CF_USE2|CF_CHG3 }, // Multiply 32-Bit x 32-Bit Into 64-Bit Result
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{ "MPYIH", CF_USE1|CF_USE2|CF_CHG3 }, // Multiply 32-Bit x 16-MSB Into 64-Bit Result
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{ "MPYIHR", CF_USE1|CF_USE2|CF_CHG3 }, // Multiply 32-Bit x 16 MSB, Shifted by 15 to Produce a Rounded 32-Bit Result
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{ "MPYIL", CF_USE1|CF_USE2|CF_CHG3 }, // Multiply 32-Bit x 16 LSB Into 64-Bit Result
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{ "MPYILR", CF_USE1|CF_USE2|CF_CHG3 }, // Multiply 32-Bit x 16 LSB, Shifted by 15 to Produce a Rounded 32-Bit Result
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{ "MPYLI", CF_USE1|CF_USE2|CF_CHG3 }, // Multiply 16 LSB x 32-Bit Into 64-Bit Result
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{ "MPYLIR", CF_USE1|CF_USE2|CF_CHG3 }, // Multiply 16 LSB x 32-Bit, Shifted by 15 to Produce a Rounded 32-Bit Result
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{ "MPYSP", CF_USE1|CF_USE2|CF_CHG3 }, // Multiply Two Single-Precision Floating-Point Values
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{ "MPYSP2DP", CF_USE1|CF_USE2|CF_CHG3 }, // Multiply Two Single-Precision Floating-Point Values for Double-Precision Result
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{ "MPYSPDP", CF_USE1|CF_USE2|CF_CHG3 }, // Multiply Single-Precision Floating-Point Value x Double-Precision Floating-Point Value
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{ "MPYSU4", CF_USE1|CF_USE2|CF_CHG3 }, // Multiply Signed x Unsigned, Four 8-Bit Pairs for Four 8-Bit Results
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{ "MPYU4", CF_USE1|CF_USE2|CF_CHG3 }, // Multiply Unsigned x Unsigned, Four 8-Bit Pairs for Four 8-Bit Results
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{ "MPYUS4", CF_USE1|CF_USE2|CF_CHG3 }, // Multiply Unsigned x Signed, Four 8-Bit Pairs for Four 8-Bit Results
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{ "MVD", CF_USE1|CF_CHG2 }, // Move From Register to Register, Delayed
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{ "MVKL", CF_USE1|CF_CHG2 }, // Move Signed Constant Into Register and Sign Extend
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{ "PACK2", CF_USE1|CF_USE2|CF_CHG3 }, // Pack Two 16 LSBs Into Upper and Lower Register Halves
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{ "PACKH2", CF_USE1|CF_USE2|CF_CHG3 }, // Pack Two 16 MSBs Into Upper and Lower Register Halves
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{ "PACKH4", CF_USE1|CF_USE2|CF_CHG3 }, // Pack Four High Bytes Into Four 8-Bit Halfwords
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{ "PACKHL2", CF_USE1|CF_USE2|CF_CHG3 }, // Pack 16 MSB Into Upper and 16 LSB Into Lower Register Halves
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{ "PACKL4", CF_USE1|CF_USE2|CF_CHG3 }, // Pack Four Low Bytes Into Four 8-Bit Halfwords
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{ "PACKLH2", CF_USE1|CF_USE2|CF_CHG3 }, // Pack 16 LSB Into Upper and 16 MSB Into Lower Register Halves
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{ "RCPDP", CF_USE1|CF_CHG2 }, // Double-Precision Floating-Point Reciprocal Approximation
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{ "RCPSP", CF_USE1|CF_CHG2 }, // Single-Precision Floating-Point Reciprocal Approximation
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{ "RINT", 0 }, // Restore Previous Enable State
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{ "ROTL", CF_USE1|CF_USE2|CF_CHG3 }, // Rotate Left
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{ "RPACK2", CF_USE1|CF_USE2|CF_CHG3 }, // Shift With Saturation and Pack Two 16 MSBs Into Upper and Lower Register Halves
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{ "RSQRDP", CF_USE1|CF_CHG2 }, // Double-Precision Floating-Point Square-Root Reciprocal Approximation
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{ "RSQRSP", CF_USE1|CF_CHG2 }, // Single-Precision Floating-Point Square-Root Reciprocal Approximation
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{ "SADD2", CF_USE1|CF_USE2|CF_CHG3 }, // Add Two Signed 16-Bit Integers on Upper and Lower Register Halves With Saturation
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{ "SADDSU2", CF_USE1|CF_USE2|CF_CHG3 }, // Add Two Signed and Unsigned 16-Bit Integers on Register Halves With Saturation
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{ "SADDSUB", CF_USE1|CF_USE2|CF_CHG3 }, // Parallel SADD and SSUB Operations On Common Inputs
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{ "SADDSUB2", CF_USE1|CF_USE2|CF_CHG3 }, // Parallel SADD2 and SSUB2 Operations On Common Inputs
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{ "SADDU4", CF_USE1|CF_USE2|CF_CHG3 }, // Add With Saturation, Four Unsigned 8-Bit Pairs for Four 8-Bit Results
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{ "SADDUS2", CF_USE1|CF_USE2|CF_CHG3 }, // Add Two Unsigned and Signed 16-Bit Integers on Register Halves With Saturation
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{ "SHFL", CF_USE1|CF_CHG2 }, // Shuffle
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{ "SHFL3", CF_USE1|CF_USE2|CF_CHG3 }, // 3-Way Bit Interleave On Three 16-Bit Values Into a 48-Bit Result
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{ "SHLMB", CF_USE1|CF_USE2|CF_CHG3 }, // Shift Left and Merge Byte
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{ "SHR2", CF_USE1|CF_USE2|CF_CHG3 }, // Arithmetic Shift Right, Signed, Packed 16-Bit
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{ "SHRMB", CF_USE1|CF_USE2|CF_CHG3 }, // Shift Right and Merge Byte
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{ "SHRU2", CF_USE1|CF_USE2|CF_CHG3 }, // Arithmetic Shift Right, Unsigned, Packed 16-Bit
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{ "SMPY2", CF_USE1|CF_USE2|CF_CHG3 }, // Multiply Signed by Signed, 16 LSB x 16 LSB and 16 MSB x 16 MSB With Left Shift and Saturation
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{ "SMPY32", CF_USE1|CF_USE2|CF_CHG3 }, // Multiply Signed 32-Bit x Signed 32-Bit Into 64-Bit Result With Left Shift and Saturation
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{ "SPACK2", CF_USE1|CF_USE2|CF_CHG3 }, // Saturate and Pack Two 16 LSBs Into Upper and Lower Register Halves
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{ "SPACKU4", CF_USE1|CF_USE2|CF_CHG3 }, // Saturate and Pack Four Signed 16-Bit Integers Into Four Unsigned 8-Bit Halfwords
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{ "SPDP", CF_USE1|CF_CHG2 }, // Convert Single-Precision Floating-Point Value to Double-Precision Floating-Point Value
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{ "SPINT", CF_USE1|CF_CHG2 }, // Convert Single-Precision Floating-Point Value to Integer
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{ "SPKERNEL", CF_USE1 }, // Software Pipelined Loop (SPLOOP) Buffer Operation Code Boundary
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{ "SPKERNELR", 0 }, // Software Pipelined Loop (SPLOOP) Buffer Operation Code Boundary
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{ "SPLOOP", CF_USE1 }, // Software Pipelined Loop (SPLOOP) Buffer Operation
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{ "SPLOOPD", CF_USE1 }, // Software Pipelined Loop (SPLOOP) Buffer Operation With Delayed Testing
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{ "SPLOOPW", CF_USE1 }, // Software Pipelined Loop (SPLOOP) Buffer Operation With Delayed Testing and No Epilog
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{ "SPMASK", CF_USE1 }, // Software Pipelined Loop (SPLOOP) Buffer Operation Load/Execution Control
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{ "SPMASKR", CF_USE1 }, // Software Pipelined Loop (SPLOOP) Buffer Operation Load/Execution Control
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{ "SPTRUNC", CF_USE1|CF_CHG2 }, // Convert Single-Precision Floating-Point Value to Integer With Truncation
|
|
{ "SSHVL", CF_USE1|CF_USE2|CF_CHG3 }, // Variable Shift Left
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|
{ "SSHVR", CF_USE1|CF_USE2|CF_CHG3 }, // Variable Shift Right
|
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{ "SSUB2", CF_USE1|CF_USE2|CF_CHG3 }, // Subtract Two Signed 16-Bit Integers on Upper and Lower Register Halves With Saturation
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|
{ "STDW", CF_USE1|CF_CHG2 }, // Store Doubleword to Memory With a 5-Bit Unsigned Constant Offset or Register Offset
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{ "STNDW", CF_USE1|CF_CHG2 }, // Store Nonaligned Doubleword to Memory With a 5-Bit Unsigned Constant Offset or Register Offset
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{ "STNW", CF_USE1|CF_CHG2 }, // Store Nonaligned Word to Memory With a 5-Bit Unsigned Constant Offset or Register Offset
|
|
{ "SUB4", CF_USE1|CF_USE2|CF_CHG3 }, // Subtract Without Saturation, Four 8-Bit Pairs for Four 8-Bit Results
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{ "SUBABS4", CF_USE1|CF_USE2|CF_CHG3 }, // Subtract With Absolute Value, Four 8-Bit Pairs for Four 8-Bit Results
|
|
{ "SUBDP", CF_USE1|CF_USE2|CF_CHG3 }, // Subtract Two Double-Precision Floating-Point Values
|
|
{ "SUBSP", CF_USE1|CF_USE2|CF_CHG3 }, // Subtract Two Single-Precision Floating-Point Values
|
|
{ "SWAP2", CF_USE1|CF_CHG2 }, // Swap Bytes in Upper and Lower Register Halves
|
|
{ "SWAP4", CF_USE1|CF_CHG2 }, // Swap Byte Pairs in Upper and Lower Register Halves
|
|
{ "SWE", 0 }, // Software Exception
|
|
{ "SWENR", 0 }, // Software Exception, No Return
|
|
{ "UNPKHU4", CF_USE1|CF_CHG2 }, // Unpack 16 MSB Into Two Lower 8-Bit Halfwords of Upper and Lower Register Halves
|
|
{ "UNPKLU4", CF_USE1|CF_CHG2 }, // Unpack 16 LSB Into Two Lower 8-Bit Halfwords of Upper and Lower Register Halves
|
|
{ "XORMPY", CF_USE1|CF_USE2|CF_CHG3 }, // Galois Field Multiply With Zero Polynomial
|
|
{ "XPND2", CF_USE1|CF_CHG2 }, // Expand Bits to Packed 16-Bit Masks
|
|
{ "XPND4", CF_USE1|CF_CHG2 }, // Expand Bits to Packed 8-Bit Masks
|
|
|
|
};
|
|
|
|
CASSERT(qnumber(Instructions) == TMS6_last);
|