436 lines
12 KiB
C++
436 lines
12 KiB
C++
/*
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* Interactive disassembler (IDA).
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* Copyright (c) 1990-99 by Ilfak Guilfanov.
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* ALL RIGHTS RESERVED.
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* E-mail: ig@datarescue.com
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*
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*
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*/
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#include "tms320c54.hpp"
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#include <segregs.hpp>
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#include <frame.hpp>
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//------------------------------------------------------------------------
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ea_t calc_code_mem(const insn_t &insn, ea_t ea, bool is_near)
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{
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ea_t rv;
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if ( is_near )
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{
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sel_t xpc = get_sreg(insn.ea, XPC);
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if ( xpc == BADSEL )
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xpc = 0;
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rv = ((xpc & 0x7F) << 16) | (ea & 0xFFFF);
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}
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else
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{
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rv = to_ea(insn.cs, ea);
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}
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return use_mapping(rv);
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}
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//------------------------------------------------------------------------
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ea_t tms320c54_t::calc_data_mem(const insn_t &insn, ea_t ea, bool is_mem) const
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{
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ea_t rv;
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if ( is_mem )
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{
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sel_t dp = get_sreg(insn.ea, DP);
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if ( dp == BADSEL )
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return BADSEL;
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rv = ((dp & 0x1FF) << 7) | (ea & 0x7F);
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}
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else
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{
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rv = ea;
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}
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rv += dataseg;
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return use_mapping(rv);
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}
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//----------------------------------------------------------------------
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regnum_t tms320c54_t::get_mapped_register(ea_t ea) const
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{
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if ( idpflags & TMS320C54_MMR )
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{
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switch ( ea-dataseg )
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{
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case 0x00: return IMR;
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case 0x01: return IFR;
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case 0x06: return ST0;
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case 0x07: return ST1;
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case 0x08: return AL;
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case 0x09: return AH;
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case 0x0A: return AG;
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case 0x0B: return BL;
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case 0x0C: return BH;
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case 0x0D: return BG;
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case 0x0E: return T;
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case 0x0F: return TRN;
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case 0x10: return AR0;
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case 0x11: return AR1;
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case 0x12: return AR2;
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case 0x13: return AR3;
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case 0x14: return AR4;
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case 0x15: return AR5;
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case 0x16: return AR6;
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case 0x17: return AR7;
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case 0x18: return SP;
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case 0x19: return BK;
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case 0x1A: return BRC;
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case 0x1B: return RSA;
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case 0x1C: return REA;
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case 0x1D: return PMST;
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case 0x1E: return XPC;
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default: return rnone;
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}
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}
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else
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return rnone;
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}
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//----------------------------------------------------------------------
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static void process_imm(const insn_t &insn, const op_t &x, flags_t F)
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{
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set_immd(insn.ea);
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if ( is_defarg(F, x.n) )
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return; // if already defined by user
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switch ( insn.itype )
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{
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case TMS320C54_cmpm:
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case TMS320C54_bitf:
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case TMS320C54_andm:
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case TMS320C54_orm:
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case TMS320C54_xorm:
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case TMS320C54_addm:
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case TMS320C54_st:
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case TMS320C54_stm:
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case TMS320C54_rpt:
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case TMS320C54_ld3:
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case TMS320C54_mpy2:
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case TMS320C54_rptz:
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case TMS320C54_add3:
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case TMS320C54_sub3:
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case TMS320C54_and3:
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case TMS320C54_or3:
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case TMS320C54_xor3:
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case TMS320C54_mac2:
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op_num(insn.ea, x.n);
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}
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}
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//----------------------------------------------------------------------
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void tms320c54_t::handle_operand(const insn_t &insn, const op_t &x, flags_t F, bool use)
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{
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switch ( x.type )
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{
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case o_bit:
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case o_reg:
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case o_cond8:
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case o_cond2:
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return;
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case o_near:
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case o_far:
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{
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if ( insn.itype != TMS320C54_rptb && insn.itype != TMS320C54_rptbd )
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{
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cref_t ftype = fl_JN;
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ea_t ea = calc_code_mem(insn, x.addr, x.type == o_near);
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if ( has_insn_feature(insn.itype, CF_CALL) )
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{
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if ( !func_does_return(ea) )
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flow = false;
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ftype = fl_CN;
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}
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#ifndef TMS320C54_NO_NAME_NO_REF
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if ( x.dtype == dt_byte )
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insn.add_dref(ea, x.offb, dr_R);
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else
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insn.add_cref(ea, x.offb, ftype);
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#endif
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}
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#ifndef TMS320C54_NO_NAME_NO_REF
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else // evaluate RPTB[D] loops as dref
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insn.add_dref(calc_code_mem(insn, x.addr), x.offb, dr_I);
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#endif
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}
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break;
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case o_imm:
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QASSERT(10113, use);
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process_imm(insn, x, F);
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#ifndef TMS320C54_NO_NAME_NO_REF
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if ( op_adds_xrefs(F, x.n) )
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insn.add_off_drefs(x, dr_O, x.Signed ? OOF_SIGNED : 0);
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#endif
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break;
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case o_mem:
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case o_farmem:
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case o_mmr:
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{
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ea_t ea = calc_data_mem(insn, x.addr, x.type == o_mem);
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if ( ea != BADADDR )
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{
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#ifndef TMS320C54_NO_NAME_NO_REF
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insn.add_dref(ea, x.offb, use ? dr_R : dr_W);
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#endif
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insn.create_op_data(ea, x);
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}
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}
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break;
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case o_local: // local variables
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if ( may_create_stkvars()
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&& (get_func(insn.ea) != NULL)
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&& insn.create_stkvar(x, x.addr, STKVAR_VALID_SIZE) )
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{
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op_stkvar(insn.ea, x.n);
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}
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break;
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case o_displ:
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set_immd(insn.ea);
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break;
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default:
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warning("interr: emu2 address:%a operand:%d type:%d", insn.ea, x.n, x.type);
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}
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}
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//----------------------------------------------------------------------
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// is the previous instruction a delayed jump ?
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//
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// The following array shows all delayed instructions (xxx[D])
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// who are required to always stop.
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//
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// Z = 1 : delay instruction bit
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//
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// BRANCH INSTRUCTIONS
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//
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// TMS320C54_bd, // Branch Unconditionally 1111 00Z0 0111 0011 16-bit constant B[D] pmad
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// TMS320C54_baccd, // Branch to Location Specified by Accumulator 1111 01ZS 1110 0010 BACC[D] src
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// TMS320C54_fbd, // Far Branch Unconditionally 1111 10Z0 1 7bit constant=pmad(22-16) 16-bit constant=pmad(15-0) FB[D] extpmad
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// TMS320C54_fbaccd, // Far Branch to Location Specified by Accumulator 1111 01ZS 1110 0110 FBACC[D] src
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//
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// RETURN INSTRUCTIONS
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//
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// TMS320C54_fretd, // Far Return 1111 01Z0 1110 0100 FRET[D]
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// TMS320C54_freted, // Enable Interrupts and Far Return From Interrupt 1111 01Z0 1110 0101 FRETE[D]
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// TMS320C54_retd, // Return 1111 11Z0 0000 0000 RET[D]
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// TMS320C54_reted, // Enable Interrupts and Return From Interrupt 1111 01Z0 1110 1011 RETE[D]
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// TMS320C54_retfd, // Enable Interrupts and Fast Return From Interrupt 1111 01Z0 1001 1011 RETF[D]
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static bool delayed_stop(const insn_t &insn, flags_t F)
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{
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if ( !is_flow(F) )
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return false;
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if ( insn.size == 0 || insn.size > 2 )
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return false;
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int sub = 2 - insn.size; // backward offset to skip the previous 1-word instruction in the case of 2 consecutive 1-word instructions
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// first, we analyze 1-word instructions
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ea_t ea = insn.ea - sub - 1;
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if ( is_code(get_flags(ea)) )
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{
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int code = get_wide_byte(ea); // get the instruction word
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switch ( code )
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{
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case 0xF6E2: // TMS320C54_baccd, // Branch to Location Specified by Accumulator 1111 01ZS 1110 0010 BACC[D] src
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case 0xF7E2:
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case 0xF6E6: // TMS320C54_fbaccd, // Far Branch to Location Specified by Accumulator 1111 01ZS 1110 0110 FBACC[D] src
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case 0xF7E6:
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case 0xF6E4: // TMS320C54_fretd, // Far Return 1111 01Z0 1110 0100 FRET[D]
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case 0xF6E5: // TMS320C54_freted, // Enable Interrupts and Far Return From Interrupt 1111 01Z0 1110 0101 FRETE[D]
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case 0xFE00: // TMS320C54_retd, // Return 1111 11Z0 0000 0000 RET[D]
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case 0xF6EB: // TMS320C54_reted, // Enable Interrupts and Return From Interrupt 1111 01Z0 1110 1011 RETE[D]
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case 0xF69B: // TMS320C54_retfd, // Enable Interrupts and Fast Return From Interrupt 1111 01Z0 1001 1011 RETF[D]
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return true;
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}
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}
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// else, we analyze 2-word instructions
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ea = insn.ea - sub - 2;
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if ( is_code(get_flags(ea)) )
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{
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int code = get_wide_byte(ea); // get the first instruction word
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if ( code == 0xF273 // TMS320C54_bd, // Branch Unconditionally 1111 00Z0 0111 0011 16-bit constant B[D] pmad
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|| (code & 0xFF80) == 0xFA80 ) // TMS320C54_fbd, // Far Branch Unconditionally 1111 10Z0 1 7bit constant=pmad(22-16) 16-bit constant=pmad(15-0) FB[D] extpmad
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{
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return true;
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}
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}
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return false;
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}
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//----------------------------------------------------------------------
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bool is_basic_block_end(const insn_t &insn)
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{
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flags_t F = get_flags(insn.ea);
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if ( delayed_stop(insn, F) )
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return true;
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return !is_flow(get_flags(insn.ea+insn.size));
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}
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//----------------------------------------------------------------------
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static bool add_stkpnt(const insn_t &insn, sval_t delta)
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{
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func_t *pfn = get_func(insn.ea);
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if ( pfn == NULL )
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return false;
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return add_auto_stkpnt(pfn, insn.ea+insn.size, delta);
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}
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//----------------------------------------------------------------------
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static void trace_sp(const insn_t &insn)
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{
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// trace SP changes
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switch ( insn.itype )
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{
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case TMS320C54_fret:
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case TMS320C54_fretd:
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case TMS320C54_frete:
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case TMS320C54_freted:
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add_stkpnt(insn, 2);
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break;
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case TMS320C54_ret:
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case TMS320C54_retd:
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case TMS320C54_rete:
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case TMS320C54_reted:
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case TMS320C54_retf:
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case TMS320C54_retfd:
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add_stkpnt(insn, 1);
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break;
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case TMS320C54_frame:
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add_stkpnt(insn, insn.Op1.value);
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break;
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case TMS320C54_popd:
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case TMS320C54_popm:
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add_stkpnt(insn, 1);
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break;
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case TMS320C54_pshd:
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case TMS320C54_pshm:
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add_stkpnt(insn, -1);
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break;
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}
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}
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//----------------------------------------------------------------------
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int tms320c54_t::emu(const insn_t &insn)
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{
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uint32 feature = insn.get_canon_feature(ph);
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flow = (feature & CF_STOP) == 0;
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flags_t F = get_flags(insn.ea);
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if ( feature & CF_USE1 ) handle_operand(insn, insn.Op1, F, true);
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if ( feature & CF_USE2 ) handle_operand(insn, insn.Op2, F, true);
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if ( feature & CF_USE3 ) handle_operand(insn, insn.Op3, F, true);
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if ( feature & CF_CHG1 ) handle_operand(insn, insn.Op1, F, false);
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if ( feature & CF_CHG2 ) handle_operand(insn, insn.Op2, F, false);
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if ( feature & CF_CHG3 ) handle_operand(insn, insn.Op3, F, false);
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// check for CPL changes
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if ( (insn.itype == TMS320C54_rsbx1 || insn.itype == TMS320C54_ssbx1)
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&& insn.Op1.type == o_reg && insn.Op1.reg == CPL )
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{
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int value = insn.itype == TMS320C54_rsbx1 ? 0 : 1;
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split_sreg_range(get_item_end(insn.ea), CPL, value, SR_auto);
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}
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// check for DP changes
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if ( insn.itype == TMS320C54_ld2
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&& insn.Op1.type == o_imm
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&& insn.Op1.dtype == dt_byte
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&& insn.Op2.type == o_reg
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&& insn.Op2.reg == DP )
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{
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split_sreg_range(get_item_end(insn.ea), DP, insn.Op1.value & 0x1FF, SR_auto);
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}
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// determine if the next instruction should be executed
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if ( segtype(insn.ea) == SEG_XTRN )
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flow = false;
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if ( flow && delayed_stop(insn, F) )
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flow = false;
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if ( flow )
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add_cref(insn.ea, insn.ea+insn.size, fl_F);
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if ( may_trace_sp() )
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{
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if ( !flow )
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recalc_spd(insn.ea); // recalculate SP register for the next insn
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else
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trace_sp(insn);
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}
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return 1;
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}
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//----------------------------------------------------------------------
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bool tms320c54_t::create_func_frame(func_t *pfn) const
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{
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if ( pfn != NULL )
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{
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if ( pfn->frame == BADNODE )
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{
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insn_t insn;
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int regsize = 0;
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ea_t ea = pfn->start_ea;
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while ( ea < pfn->end_ea ) // check for register pushs
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{
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if ( decode_insn(&insn, ea) < 1 )
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break;
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if ( insn.itype != TMS320C54_pshm )
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break;
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if ( insn.Op1.type != o_mem && insn.Op1.type != o_mmr )
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break;
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if ( get_mapped_register(insn.Op1.addr) == rnone )
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break;
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regsize++;
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ea += insn.size;
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}
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int localsize = 0;
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while ( ea < pfn->end_ea ) // check for frame creation
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{
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if ( insn.itype == TMS320C54_frame && insn.Op1.type == o_imm )
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{
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localsize = -(int)insn.Op1.value;
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break;
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}
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ea += insn.size;
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if ( decode_insn(&insn, ea) < 1 )
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break;
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}
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add_frame(pfn, localsize+regsize, 0, 0);
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}
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}
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return 0;
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}
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//----------------------------------------------------------------------
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int idaapi tms_get_frame_retsize(const func_t * /*pfn*/)
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{
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return 1; // 1 'byte' for the return address
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}
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//----------------------------------------------------------------------
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int idaapi is_align_insn(ea_t ea)
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{
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insn_t insn;
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if ( decode_insn(&insn, ea) < 1 )
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return 0;
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switch ( insn.itype )
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{
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case TMS320C54_nop:
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break;
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default:
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return 0;
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}
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return insn.size;
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}
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