361 lines
11 KiB
C++
361 lines
11 KiB
C++
/*
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* Interactive disassembler (IDA).
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* Version 3.05
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* Copyright (c) 1990-95 by Ilfak Guilfanov.
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* ALL RIGHTS RESERVED.
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* FIDO: 2:5020/209
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* E-mail: ig@estar.msk.su
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*
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*/
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#include "tms.hpp"
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//--------------------------------------------------------------------------
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static const char *const RegNames[] =
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{
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"acc","p","bmar",
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"ar0","ar1","ar2","ar3","ar4","ar5","ar6","ar7",
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"cs","ds","dp"
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};
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//--------------------------------------------------------------------------
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const static predefined_t iregs[] =
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{
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{ 0x00, "Reserved_0", NULL },
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{ 0x01, "Reserved_1", NULL },
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{ 0x02, "Reserved_2", NULL },
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{ 0x03, "Reserved_3", NULL },
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{ 0x04, "imr", "Interrupt mask register" },
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{ 0x05, "greg", "Global memory allocation register" },
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{ 0x06, "ifr", "Interrupt flag register" },
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{ 0x07, "pmst", "Processor mode status register" },
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{ 0x08, "rptc", "Repeat counter register" },
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{ 0x09, "brcr", "Block repeat counter register" },
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{ 0x0A, "pasr", "Block repeat program address start register" },
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{ 0x0B, "paer", "Block repeat program address end register" },
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{ 0x0C, "treg0", "Temp reg - multiplicand" },
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{ 0x0D, "treg1", "Temp reg - dynamic shift count (5 bits)" },
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{ 0x0E, "treg2", "Temp reg - bit pointer in dynamic bit test (4 bits)" },
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{ 0x0F, "dbmr", "Dynamic bit manipulation register" },
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{ 0x10, "ar0", NULL },
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{ 0x11, "ar1", NULL },
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{ 0x12, "ar2", NULL },
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{ 0x13, "ar3", NULL },
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{ 0x14, "ar4", NULL },
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{ 0x15, "ar5", NULL },
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{ 0x16, "ar6", NULL },
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{ 0x17, "ar7", NULL },
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{ 0x18, "indx", "Index register" },
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{ 0x19, "arcr", "Auxiliary compare register" },
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{ 0x1A, "cbsr1", "Circular buffer 1 start" },
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{ 0x1B, "cber1", "Circular buffer 1 end" },
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{ 0x1C, "cbsr2", "Circular buffer 2 start" },
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{ 0x1D, "cber2", "Circular buffer 2 end" },
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{ 0x1E, "cbcr", "Circular buffer control register" },
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{ 0x1F, "bmar", "Block move address register" },
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{ 0x20, "drr", "Data receive register" },
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{ 0x21, "dxr", "Data transmit register" },
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{ 0x22, "spc", "Serial port control register" },
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{ 0x23, "Reserved_23", NULL },
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{ 0x24, "tim", "Timer register" },
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{ 0x25, "prd", "Period register" },
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{ 0x26, "tcr", "Timer control register" },
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{ 0x27, "Reserved_27", NULL },
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{ 0x28, "pdwsr", "Program/Data S/W Wait-State register" },
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{ 0x29, "iowsr", "I/O Port S/W Wait-State register" },
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{ 0x2A, "cwsr", "Control S/W Wait-State register" },
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{ 0x2B, "Reserved_2b", NULL },
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{ 0x2C, "Reserved_2c", NULL },
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{ 0x2D, "Reserved_2d", NULL },
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{ 0x2E, "Reserved_2e", NULL },
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{ 0x2F, "Reserved_2f", NULL },
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{ 0x30, "trcv", "TDM Data receive register" },
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{ 0x31, "tdxr", "TDM Data transmit register" },
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{ 0x32, "tspc", "TDM Serial port control register" },
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{ 0x33, "tcsr", "TDM channel select register" },
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{ 0x34, "trta", "TDM Receive/Transmit address register" },
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{ 0x35, "trad", "TDM Received address register" },
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{ 0x00, NULL, NULL }
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};
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static const predefined_t c2_iregs[] =
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{
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{ 0x00, "drr", "Data receive register" },
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{ 0x01, "dxr", "Data transmit register" },
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{ 0x02, "tim", "Timer register" },
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{ 0x03, "prd", "Period register" },
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{ 0x04, "imr", "Interrupt mask register" },
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{ 0x05, "greg", "Global memory allocation register" },
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{ 0x00, NULL, NULL }
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};
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//----------------------------------------------------------------------
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// This old-style callback only returns the processor module object.
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static ssize_t idaapi notify(void *, int msgid, va_list)
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{
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if ( msgid == processor_t::ev_get_procmod )
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return size_t(new tms320c5_t);
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return 0;
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}
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//----------------------------------------------------------------------
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ssize_t idaapi tms320c5_t::on_event(ssize_t msgid, va_list va)
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{
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int retcode = 0;
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switch ( msgid )
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{
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case processor_t::ev_newfile:
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{
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inf_set_wide_high_byte_first(true);
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segment_t *sptr = get_first_seg();
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ea_t codeseg;
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if ( sptr != NULL )
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{
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codeseg = sptr->start_ea;
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if ( codeseg-get_segm_base(sptr) == 0 )
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{
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inf_set_start_ea(sptr->start_ea);
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inf_set_start_ip(0);
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}
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}
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else
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{
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codeseg = BADADDR;
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}
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set_segm_class(sptr, "CODE");
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set_segm_name(sptr,"cseg");
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sel_t sel;
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ea_t data_start;
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segment_t *s1 = get_next_seg(codeseg);
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if ( s1 == NULL )
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{
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segment_t s;
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uint32 size = 64 * 1024L;
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s.start_ea = free_chunk(0,size,0xF);
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s.end_ea = s.start_ea + size;
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s.sel = ushort(s.start_ea >> 4);
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s.align = saRelByte;
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s.comb = scPub;
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add_segm_ex(&s, "dseg", NULL, ADDSEG_NOSREG);
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sel = s.sel;
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data_start = s.start_ea;
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}
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else
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{
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sel = s1->sel;
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data_start = s1->start_ea;
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}
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set_default_sreg_value(getseg(codeseg), rVds, sel);
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split_sreg_range(inf_get_start_ea(), rDP, 0, SR_auto);
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inf_set_nametype(NM_NAM_OFF);
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const predefined_t *ptr = isC2() ? c2_iregs : iregs;
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for ( ; ptr->name != NULL; ptr++ )
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{
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ea_t ea = data_start + ptr->addr;
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create_byte(ea,1);
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set_name(ea, ptr->name, SN_NODUMMY);
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if ( ptr->cmt != NULL )
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set_cmt(ea, ptr->cmt, true);
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}
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tmsfunny = qgetenv("TMSFIX");
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}
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break;
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case processor_t::ev_newprc:
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nprc = va_arg(va, int);
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// bool keep_cfg = va_argi(va, bool);
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break;
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case processor_t::ev_ending_undo:
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nprc = ph.get_proc_index();
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//fall through
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case processor_t::ev_oldfile:
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inf_set_wide_high_byte_first(true); // to be able to work with old bases
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break;
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case processor_t::ev_out_header:
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{
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outctx_t *ctx = va_arg(va, outctx_t *);
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header(*ctx);
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return 1;
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}
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case processor_t::ev_out_footer:
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{
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outctx_t *ctx = va_arg(va, outctx_t *);
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footer(*ctx);
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return 1;
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}
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case processor_t::ev_out_segstart:
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{
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outctx_t *ctx = va_arg(va, outctx_t *);
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segment_t *seg = va_arg(va, segment_t *);
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segstart(*ctx, seg);
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return 1;
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}
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case processor_t::ev_out_assumes:
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{
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outctx_t *ctx = va_arg(va, outctx_t *);
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tms_assumes(*ctx);
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return 1;
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}
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case processor_t::ev_ana_insn:
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{
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insn_t *out = va_arg(va, insn_t *);
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return ana(out);
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}
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case processor_t::ev_emu_insn:
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{
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const insn_t *insn = va_arg(va, const insn_t *);
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return emu(*insn) ? 1 : -1;
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}
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case processor_t::ev_out_insn:
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{
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outctx_t *ctx = va_arg(va, outctx_t *);
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out_insn(*ctx);
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return 1;
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}
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case processor_t::ev_out_operand:
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{
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outctx_t *ctx = va_arg(va, outctx_t *);
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const op_t *op = va_arg(va, const op_t *);
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return out_opnd(*ctx, *op) ? 1 : -1;
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}
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default:
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break;
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}
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return retcode;
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}
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//-----------------------------------------------------------------------
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// DSP Fixed Point COFF Assembler Version 6.20
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// Copyright (c) 1987-1991 Texas Instruments Incorporated
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//-----------------------------------------------------------------------
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static const char *const dspasm_header[] =
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{
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".mmregs",
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NULL
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};
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static const asm_t dspasm =
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{
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AS_COLON | ASH_HEXF0,
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0,
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"DSP Fixed Point COFF Assembler Version 6.20",
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0,
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dspasm_header, // header lines
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NULL, // org
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".end",
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";", // comment string
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'"', // string delimiter
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'\'', // char delimiter
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"\\\"'", // special symbols in char and string constants
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".string", // ascii string directive
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".word", // byte directive
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".long", // word directive
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NULL, // double words
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NULL, // no qwords
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NULL, // oword (16 bytes)
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NULL, // float (4 bytes)
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NULL, // double (8 bytes)
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NULL, // tbyte (10/12 bytes)
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NULL, // packed decimal real
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NULL, // arrays (#h,#d,#v,#s(...)
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".space 16*%s",// uninited arrays
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".set", // equ
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NULL, // seg prefix
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NULL, // curip
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NULL, // func_header
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NULL, // func_footer
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NULL, // public
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NULL, // weak
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NULL, // extrn
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NULL, // comm
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NULL, // get_type_name
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NULL, // align
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'(', ')', // lbrace, rbrace
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NULL, // mod
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NULL, // and
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NULL, // or
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NULL, // xor
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NULL, // not
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NULL, // shl
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NULL, // shr
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NULL, // sizeof
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};
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static const asm_t *const asms[] = { &dspasm, NULL };
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//-----------------------------------------------------------------------
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#define FAMILY "TMS320C5x series:"
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static const char *const shnames[] = { "TMS320C5", "TMS320C2", NULL };
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static const char *const lnames[] =
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{
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FAMILY"Texas Instruments TMS320C5x",
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"Texas Instruments TMS320C2x",
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NULL
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};
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//--------------------------------------------------------------------------
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static const uchar retcode_1[] = { 0x00, 0xEF };
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static const uchar retcode_2[] = { 0x00, 0xFF };
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static const uchar retcode_3[] = { 0x3A, 0xBE };
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static const uchar retcode_4[] = { 0x38, 0xBE };
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static const bytes_t retcodes[] =
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{
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{ sizeof(retcode_1), retcode_1 },
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{ sizeof(retcode_2), retcode_2 },
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{ sizeof(retcode_3), retcode_3 },
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{ sizeof(retcode_4), retcode_4 },
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{ 0, NULL }
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};
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//-----------------------------------------------------------------------
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// Processor Definition
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//-----------------------------------------------------------------------
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processor_t LPH =
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{
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IDP_INTERFACE_VERSION, // version
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PLFM_TMS, // id
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// flag
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PR_SEGS
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| PR_RNAMESOK // can use register names for byte names
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| PR_SEGTRANS,
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// flag2
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0,
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16, // 8 bits in a byte for code segments
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16, // 8 bits in a byte for other segments
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shnames,
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lnames,
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asms,
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notify,
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RegNames, // Register names
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qnumber(RegNames), // Number of registers
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rVcs, // first
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rDP, // last
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2, // size of a segment register
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rVcs,rVds,
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NULL, // No known code start sequences
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retcodes,
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0,TMS_last,
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Instructions, // instruc
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};
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