115 lines
3.8 KiB
C++
115 lines
3.8 KiB
C++
// $Id: ins.cpp,v 1.2 2000/11/06 22:11:16 jeremy Exp $
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//
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// Copyright (c) 2000 Jeremy Cooper. All rights reserved.
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//
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions
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// are met:
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//
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// 1. Redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer.
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// 2. Redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in the
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// documentation and/or other materials provided with the distribution.
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// 3. All advertising materials mentioning features or use of this software
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// must display the following acknowledgement:
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// This product includes software developed by Jeremy Cooper.
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// 4. The name of the author may not be used to endorse or promote products
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// derived from this software without specific prior written permission.
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//
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// THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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// IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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// OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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// IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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// NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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// THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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//
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// TMS320C1X processor module.
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// Software representation of TMS320C1X instructions.
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//
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#include "../idaidp.hpp"
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#include "ins.hpp"
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//
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// Names and side-effect features of all instructions.
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// Used by the emu() function to determine instruction side effects
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// and report them to the kernel.
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//
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const instruc_t Instructions[] =
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{
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// Accumulator Memory Reference Instructions
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{ "ABS", 0 },
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{ "ADD", CF_USE1 },
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{ "ADDH", CF_USE1 },
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{ "ADDS", CF_USE1 },
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{ "AND", CF_USE1 },
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{ "LAC", CF_USE1 },
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{ "LACK", CF_USE1 },
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{ "OR", CF_USE1 },
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{ "SACH", CF_CHG1 },
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{ "SACL", CF_CHG1 },
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{ "SUB", CF_USE1 },
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{ "SUBC", CF_USE1 },
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{ "SUBH", CF_USE1 },
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{ "SUBS", CF_USE1 },
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{ "XOR", CF_USE1 },
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{ "ZAC", 0 },
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{ "ZALH", CF_USE1 },
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{ "ZALS", CF_USE1 },
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// Auxiliary Register and Data Page Pointer Instructions
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{ "LAR", CF_USE1 },
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{ "LARK", CF_USE1 },
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{ "LARP", CF_USE1 },
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{ "LDP", CF_USE1 },
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{ "LDPK", CF_USE1 },
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{ "MAR", 0 }, // no memory access occurs, just ARP and AR change
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{ "SAR", CF_CHG1 },
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// T Register, P Register, and Multiply Instructions
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{ "APAC", 0 },
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{ "LT", CF_USE1 },
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{ "LTA", CF_USE1 },
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{ "LTD", CF_USE1|CF_CHG1 }, // changes [Op1 + 1]!
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{ "MPY", CF_USE1 },
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{ "MPYK", CF_USE1 },
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{ "PAC", 0 },
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{ "SPAC", 0 },
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// Branch/Call Instructions
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{ "B", CF_USE1|CF_JUMP|CF_STOP },
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{ "BANZ", CF_USE1|CF_JUMP },
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{ "BGEZ", CF_USE1|CF_JUMP },
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{ "BGZ", CF_USE1|CF_JUMP },
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{ "BIOZ", CF_USE1|CF_JUMP },
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{ "BLEZ", CF_USE1|CF_JUMP },
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{ "BLZ", CF_USE1|CF_JUMP },
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{ "BNZ", CF_USE1|CF_JUMP },
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{ "BV", CF_USE1|CF_JUMP },
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{ "BZ", CF_USE1|CF_JUMP },
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{ "CALA", CF_CALL },
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{ "CALL", CF_USE1|CF_CALL },
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{ "RET", CF_STOP },
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// Control Instructions
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{ "DINT", 0 },
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{ "EINT", 0 },
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{ "LST", CF_USE1 },
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{ "NOP", 0 },
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{ "POP", 0 },
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{ "PUSH", 0 },
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{ "ROVM", 0 },
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{ "SOVM", 0 },
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{ "SST", CF_CHG1 }, // Operates in page 1 ONLY if direct
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// I/O and Data Memory Instructions
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{ "DMOV", CF_CHG1 }, // changes [Op1 + 1]!
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{ "IN", CF_CHG1 },
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{ "OUT", CF_USE1 },
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{ "TBLR", CF_CHG1 },
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{ "TBLW", CF_USE1 },
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};
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CASSERT(qnumber(Instructions) == I__LAST);
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