651 lines
19 KiB
C++
651 lines
19 KiB
C++
// $Id: ana.cpp,v 1.13 2000/11/06 22:11:16 jeremy Exp $
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//
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// Copyright (c) 2000 Jeremy Cooper. All rights reserved.
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//
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions
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// are met:
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//
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// 1. Redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer.
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// 2. Redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in the
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// documentation and/or other materials provided with the distribution.
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// 3. All advertising materials mentioning features or use of this software
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// must display the following acknowledgement:
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// This product includes software developed by Jeremy Cooper.
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// 4. The name of the author may not be used to endorse or promote products
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// derived from this software without specific prior written permission.
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//
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// THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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// IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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// OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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// IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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// NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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// THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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//
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// TMS320C1X Processor module
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// Instruction decode.
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//
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#include "../idaidp.hpp"
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#include "tms320c1.hpp"
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#include "ins.hpp"
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#include "reg.hpp"
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//
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// After determining an instruction's opcode, ana() calls one of the
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// functions below to decode its operands.
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//
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static int ana_di(insn_t &insn, uint16); // direct/indirect instruction
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static int ana_di_shift(insn_t &insn, uint16); // direct/indirect w/ shift instruction
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static int ana_di_port(insn_t &insn, uint16); // direct/indirect to/from I/O port
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static int ana_di_aux(insn_t &insn, uint16); // direct/indirect to AR register
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static int ana_imm_1(insn_t &insn, uint16); // immediate 1 bit
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static int ana_imm_8(insn_t &insn, uint16); // immediate 8 bits
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static int ana_imm_13(insn_t &insn, uint16); // immediate 13 bits
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static int ana_imm_8_aux(insn_t &insn, uint16); // immediate 8 bits into AR register
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static int ana_flow(insn_t &insn); // flow control
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inline int ana_empty(const insn_t &insn); // no operands
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//
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// These functions in turn may call one of the functions below to help
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// decode the individual operands within the instruction.
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//
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static int ana_op_di(const insn_t &insn, op_t &, op_t &, uint16); // direct/indirect operand
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static int ana_op_narp(const insn_t &insn, op_t &, uint16); // new ARP operand
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//
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// Due to limitations that IDA's some of IDA's helper functions have,
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// they don't work well with processors whose byte size is greater
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// than 8 bits. (This processor has a 16-bit byte). Therefore we
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// have to make our own replacements for these functions.
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//
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// Simulates the effect of the IDA kernel helper function insn.get_next_byte(),
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// but works with our 16-bit byte environment.
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//
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static uint16 tms320c1x_get_next_insn_byte(insn_t &insn)
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{
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//
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// Fetch a 16 bit value from the (global) current instruction decode
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// pointer.
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//
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uint16 value = get_wide_byte(insn.ea+insn.size);
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//
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// Increment the size of the current instruction, to reflect the fact
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// that it contains the byte that we just read.
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//
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insn.size++;
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return value;
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}
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//lint -esym(714,ana)
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int idaapi ana(insn_t *_insn)
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{
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insn_t &insn = *_insn;
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//
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// Fetch the first 16 bits of the instruction.
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// (All instructions are at least 16 bits long).
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//
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uint16 opcode = tms320c1x_get_next_insn_byte(insn);
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//
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// Decode the instruction in the opcode by sifting through the
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// various instruction bit masks.
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//
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//
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// 3-bit mask instructions:
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// MPYK
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//
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switch ( opcode & ISN_3_BIT_MASK )
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{
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case ISN3_MPYK : insn.itype = I_MPYK; return ana_imm_13(insn, opcode);
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}
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//
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// 4-bit mask instructions:
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// ADD, LAC, SUB
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//
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switch ( opcode & ISN_4_BIT_MASK )
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{
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case ISN4_ADD : insn.itype = I_ADD; return ana_di_shift(insn, opcode);
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case ISN4_LAC : insn.itype = I_LAC; return ana_di_shift(insn, opcode);
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case ISN4_SUB : insn.itype = I_SUB; return ana_di_shift(insn, opcode);
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}
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//
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// 5-bit mask instructions:
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// SACH, IN, OUT
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//
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switch ( opcode & ISN_5_BIT_MASK )
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{
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case ISN5_SACH : insn.itype = I_SACH; return ana_di(insn, opcode);
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case ISN5_IN : insn.itype = I_IN; return ana_di_port(insn, opcode);
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case ISN5_OUT : insn.itype = I_OUT; return ana_di_port(insn, opcode);
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}
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//
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// 7-bit mask instructions:
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// LAR, LARK, SAR
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//
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switch ( opcode & ISN_7_BIT_MASK )
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{
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case ISN7_LAR : insn.itype = I_LAR; return ana_di_aux(insn, opcode);
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case ISN7_LARK : insn.itype = I_LARK; return ana_imm_8_aux(insn, opcode);
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case ISN7_SAR : insn.itype = I_SAR; return ana_di_aux(insn, opcode);
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}
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//
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// 8-bit mask instructions:
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// ADDH, ADDS, AND, LACK, OR, SACL, SUBC, SUBH, XOR, ZALH, LDP, MAR,
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// LT, LTA, LTD, MPY, LST, SST, DMOV, TBLR, TBLW
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//
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switch ( opcode & ISN_8_BIT_MASK )
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{
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case ISN8_ADDH : insn.itype = I_ADDH; return ana_di(insn, opcode);
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case ISN8_ADDS : insn.itype = I_ADDS; return ana_di(insn, opcode);
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case ISN8_AND : insn.itype = I_AND; return ana_di(insn, opcode);
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case ISN8_LACK : insn.itype = I_LACK; return ana_imm_8(insn, opcode);
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case ISN8_OR : insn.itype = I_OR; return ana_di(insn, opcode);
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case ISN8_SACL : insn.itype = I_SACL; return ana_di(insn, opcode);
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case ISN8_SUBC : insn.itype = I_SUBC; return ana_di(insn, opcode);
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case ISN8_SUBH : insn.itype = I_SUBH; return ana_di(insn, opcode);
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case ISN8_SUBS : insn.itype = I_SUBS; return ana_di(insn, opcode);
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case ISN8_XOR : insn.itype = I_XOR; return ana_di(insn, opcode);
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case ISN8_ZALH : insn.itype = I_ZALH; return ana_di(insn, opcode);
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case ISN8_ZALS : insn.itype = I_ZALS; return ana_di(insn, opcode);
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case ISN8_LDP : insn.itype = I_LDP; return ana_di(insn, opcode);
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case ISN8_MAR : insn.itype = I_MAR; return ana_di(insn, opcode);
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case ISN8_LT : insn.itype = I_LT; return ana_di(insn, opcode);
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case ISN8_LTA : insn.itype = I_LTA; return ana_di(insn, opcode);
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case ISN8_LTD : insn.itype = I_LTD; return ana_di(insn, opcode);
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case ISN8_MPY : insn.itype = I_MPY; return ana_di(insn, opcode);
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case ISN8_LST : insn.itype = I_LST; return ana_di(insn, opcode);
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case ISN8_SST : insn.itype = I_SST; return ana_di(insn, opcode);
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case ISN8_DMOV : insn.itype = I_DMOV; return ana_di(insn, opcode);
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case ISN8_TBLR : insn.itype = I_TBLR; return ana_di(insn, opcode);
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case ISN8_TBLW : insn.itype = I_TBLW; return ana_di(insn, opcode);
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}
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//
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// 15-bit mask instructions:
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// LARP, LDPK
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//
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switch ( opcode & ISN_15_BIT_MASK )
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{
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// LARP is a synonym for a special case of MAR
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// case ISN15_LARP: insn.itype = I_LARP; return ana_ar(opcode);
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case ISN15_LDPK: insn.itype = I_LDPK; return ana_imm_1(insn, opcode);
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}
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//
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// 16-bit mask instructions:
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// ABS, ZAC, APAC, PAC, SPAC, B, BANZ, BGEZ, BGZ, BIOZ, BLEZ, BLZ,
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// BNZ, BV, BZ, CALA, CALL, RET, DINT, EINT, NOP, POP, PUSH, ROVM,
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// SOVM
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//
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switch ( opcode & ISN_16_BIT_MASK )
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{
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case ISN16_ABS: insn.itype = I_ABS; return ana_empty(insn);
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case ISN16_ZAC: insn.itype = I_ZAC; return ana_empty(insn);
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case ISN16_APAC: insn.itype = I_APAC; return ana_empty(insn);
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case ISN16_PAC: insn.itype = I_PAC; return ana_empty(insn);
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case ISN16_SPAC: insn.itype = I_SPAC; return ana_empty(insn);
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case ISN16_B: insn.itype = I_B; return ana_flow(insn);
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case ISN16_BANZ: insn.itype = I_BANZ; return ana_flow(insn);
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case ISN16_BGEZ: insn.itype = I_BGEZ; return ana_flow(insn);
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case ISN16_BGZ: insn.itype = I_BGZ; return ana_flow(insn);
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case ISN16_BIOZ: insn.itype = I_BIOZ; return ana_flow(insn);
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case ISN16_BLEZ: insn.itype = I_BLEZ; return ana_flow(insn);
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case ISN16_BLZ: insn.itype = I_BLZ; return ana_flow(insn);
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case ISN16_BNZ: insn.itype = I_BNZ; return ana_flow(insn);
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case ISN16_BV: insn.itype = I_BV; return ana_flow(insn);
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case ISN16_BZ: insn.itype = I_BZ; return ana_flow(insn);
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case ISN16_CALA: insn.itype = I_CALA; return ana_empty(insn);
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case ISN16_CALL: insn.itype = I_CALL; return ana_flow(insn);
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case ISN16_RET: insn.itype = I_RET; return ana_empty(insn);
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case ISN16_DINT: insn.itype = I_DINT; return ana_empty(insn);
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case ISN16_EINT: insn.itype = I_EINT; return ana_empty(insn);
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case ISN16_NOP: insn.itype = I_NOP; return ana_empty(insn);
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case ISN16_POP: insn.itype = I_POP; return ana_empty(insn);
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case ISN16_PUSH: insn.itype = I_PUSH; return ana_empty(insn);
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case ISN16_ROVM: insn.itype = I_ROVM; return ana_empty(insn);
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case ISN16_SOVM: insn.itype = I_SOVM; return ana_empty(insn);
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}
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//
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// If control reaches this point, then the opcode does not represent
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// any known instruction.
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//
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return 0;
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}
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//
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// ana_empty()
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//
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// Called to decode an 'empty' instruction's operands.
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// (Very trivial, because an empty instruction has no operands).
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//
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inline int ana_empty(const insn_t &insn)
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{
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//
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// Successful decode.
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// Return the instruction size.
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//
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return insn.size;
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}
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//
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// ana_flow()
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//
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// Called to decode a flow control instruction's operands.
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// Decodes the branch address of the instruction.
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//
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// (Some flow control instructions have no arguments and are thus
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// decoded by calling ana_empty()).
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//
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static int ana_flow(insn_t &insn)
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{
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//
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// Fetch the next 16 bits from the instruction; they
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// constitute the branch address.
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//
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uint16 addr = tms320c1x_get_next_insn_byte(insn);
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//
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// Fill in the insn structure to reflect the first (and only)
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// operand of this instruction as being a reference to the CODE segment.
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//
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insn.Op1.type = o_near;
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insn.Op1.addr = addr;
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//
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// Set the operand type to reflect the size of the address
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// in the instruction. Technically this instructions address
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// value is one processor byte (16 bits), but when it comes to defining
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// operand value sizes, IDA thinks in terms of 8-bit bytes.
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// Therefore, we specify this value as a word.
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//
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insn.Op1.dtype = dt_word;
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//
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// Successful decode.
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// Return the instruction size.
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//
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return insn.size;
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}
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//
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// ana_di(opcode)
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//
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// Called to decode a direct/indirect memory reference instruction's
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// operands.
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//
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static int ana_di(insn_t &insn, uint16 opcode)
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{
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//
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// Decode the direct or indirect memory reference made
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// by the instruction as its first operand and the new arp value
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// (if it exists) as its second operand.
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//
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if ( ana_op_di(insn, insn.Op1, insn.Op2, opcode) == 0 )
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{
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//
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// The operand was invalid.
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//
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return 0;
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}
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//
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// Successful decode.
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// Return the instruction size.
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//
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return insn.size;
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}
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//
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// ana_di_shift(opcode)
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//
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// Called to decode a direct/indirect memory reference plus shift
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// instruction's operands.
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//
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static int ana_di_shift(insn_t &insn, uint16 opcode)
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{
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//
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// First, decode the direct or indirect memory reference made
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// by the instruction as its first operand, and the new arp
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// value (if it exists) as its third operand.
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//
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if ( ana_op_di(insn, insn.Op1, insn.Op3, opcode) == 0 )
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{
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//
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// The operand was invalid.
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//
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return 0;
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}
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//
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// Finally, decode the shift value as the instruction's second operand.
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//
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insn.Op2.type = o_imm;
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insn.Op2.value = ISN_SHIFT(opcode);
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//
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// Successful decode.
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// Return the instruction size.
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//
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return insn.size;
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}
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//
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// ana_di_port(opcode)
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//
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// Called to decode a direct/indirect memory reference to/from I/O port
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// instruction's operands.
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//
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static int ana_di_port(insn_t &insn, uint16 opcode)
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{
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//
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// First, decode the direct or indirect memory reference made
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// by the instruction as its first operand and the new arp value
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// (if it exists) as its third operand.
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//
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if ( ana_op_di(insn, insn.Op1, insn.Op3, opcode) == 0 )
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{
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//
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// The operand was invalid.
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//
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return 0;
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}
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//
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// Next, decode the port number as the instruction's second operand.
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//
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insn.Op2.type = o_imm;
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insn.Op2.value = ISN_PORT(opcode);
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//
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// Successful decode.
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// Return the instruction size.
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//
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return insn.size;
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}
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//
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// ana_di_aux(opcode)
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//
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// Called to decode a direct/indirect memory reference to/from auxiliary
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// register instruction's operands.
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//
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static int ana_di_aux(insn_t &insn, uint16 opcode)
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{
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//
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// First, decode the auxiliary register number as the instruction's
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// first operand.
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//
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insn.Op1.type = o_reg;
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insn.Op1.reg = (ISN_AUX_AR(opcode) ? IREG_AR1 : IREG_AR0);
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//
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// Finally, decode the direct or indirect memory reference made
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// by the instruction as its second operand and the new arp
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// value (if it exists) as its third operand.
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//
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if ( ana_op_di(insn, insn.Op2, insn.Op3, opcode) == 0 )
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{
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//
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// The operand was invalid.
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//
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return 0;
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}
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//
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// Successful decode.
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// Return the instruction size.
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//
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return insn.size;
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}
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//
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// ana_imm_1(opcode)
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//
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// Called to decode a 1 bit immediate value instruction's operands.
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//
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static int ana_imm_1(insn_t &insn, uint16 opcode)
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{
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//
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// Decode the 1 bit immediate value in this instruction's opcode
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// and make an immediate value operand out of it.
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//
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insn.Op1.type = o_imm;
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insn.Op1.value = ISN_IMM1(opcode);
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insn.Op1.dtype = dt_byte; // This means an 8 bit value, rather than 16.
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//
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// Successful decode.
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// Return the instruction size.
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//
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return insn.size;
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}
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//
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// ana_imm_8(opcode)
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//
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// Called to decode an 8 bit immediate value instruction's operands.
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//
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static int ana_imm_8(insn_t &insn, uint16 opcode)
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{
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//
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// Decode the 8 bit immediate value in this instruction's opcode
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// and make an immediate value operand out of it.
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//
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insn.Op1.type = o_imm;
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insn.Op1.value = ISN_IMM8(opcode);
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insn.Op1.dtype = dt_byte; // This means an 8 bit value, rather than 16.
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//
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// Successful decode.
|
|
// Return the instruction size.
|
|
//
|
|
return insn.size;
|
|
}
|
|
|
|
//
|
|
// ana_imm_13(opcode)
|
|
//
|
|
// Called to decode a 13 bit immediate value instruction's operands.
|
|
//
|
|
static int ana_imm_13(insn_t &insn, uint16 opcode)
|
|
{
|
|
//
|
|
// Decode the 13 bit immediate value in this instruction's opcode
|
|
// and make an immediate value operand out of it.
|
|
//
|
|
insn.Op1.type = o_imm;
|
|
insn.Op1.value = ISN_IMM13(opcode);
|
|
insn.Op1.dtype = dt_word; // This means an 8 bit value, rather than 16.
|
|
|
|
//
|
|
// Successful decode.
|
|
// Return the instruction size.
|
|
//
|
|
return insn.size;
|
|
}
|
|
|
|
//
|
|
// ana_imm_8_aux(opcode)
|
|
//
|
|
// Called upon to decode an immediate 8 bit to aux register instruction's
|
|
// operands.
|
|
//
|
|
static int ana_imm_8_aux(insn_t &insn, uint16 opcode)
|
|
{
|
|
//
|
|
// Decode the AR bit of the instruction to determine which auxiliary
|
|
// register is being loaded. Make this register the first operand.
|
|
//
|
|
insn.Op1.type = o_reg;
|
|
insn.Op1.reg = (ISN_AUX_AR(opcode) ? IREG_AR1 : IREG_AR0);
|
|
|
|
//
|
|
// Next, decode the 8 bit immediate value in the instruction and
|
|
// make it the second operand.
|
|
//
|
|
insn.Op2.type = o_imm;
|
|
insn.Op2.value = ISN_IMM8(opcode);
|
|
insn.Op2.dtype = dt_word; // This means an 8 bit value, rather than 16.
|
|
|
|
//
|
|
// Successful decode.
|
|
// Return the instruction size.
|
|
//
|
|
return insn.size;
|
|
}
|
|
|
|
//
|
|
// ana_op_di(addr_op, narp_op, opcode)
|
|
//
|
|
// Decodes the direct or indirect memory reference made in the instruction
|
|
// contained in 'opcode' and places the decoded information into the operand
|
|
// address operand 'operand' and the new ARP operand 'narp_op'.
|
|
//
|
|
// Returns instruction size on successful decode, 0 on illegal condition.
|
|
//
|
|
static int ana_op_di(const insn_t &insn, op_t &addr_op, op_t &narp_op, uint16 opcode)
|
|
{
|
|
//
|
|
// Check the direct/indirect bit. This determines whether the
|
|
// opcode makes a direct memory reference via an immediate value,
|
|
// or an indirect memory reference via the current auxiliary
|
|
// register.
|
|
//
|
|
if ( ISN_DIRECT(opcode) )
|
|
{
|
|
//
|
|
// The direct bit is set. This instruction makes a direct
|
|
// memory reference to the memory location specified in its
|
|
// immediate operand.
|
|
//
|
|
addr_op.type = o_mem;
|
|
addr_op.dtype = dt_byte; // This means an 8 bit value, rather than 16.
|
|
addr_op.addr = ISN_DIR_ADDR(opcode);
|
|
}
|
|
else
|
|
{
|
|
//
|
|
// The direct bit is reset. This instruction makes an
|
|
// indirect memory reference.
|
|
//
|
|
// Determine whether this is an AR post-increment,
|
|
// post-decrement, or no change reference.
|
|
//
|
|
if ( ISN_INDIR_INCR(opcode) && ISN_INDIR_DECR(opcode) )
|
|
{
|
|
//
|
|
// Both the AR increment and AR decrement flags are
|
|
// set. This is an illegal instruction.
|
|
//
|
|
return 0;
|
|
}
|
|
else if ( ISN_INDIR_INCR(opcode) )
|
|
{
|
|
//
|
|
// The AR increment flag is set.
|
|
// This is an AR increment reference.
|
|
//
|
|
addr_op.type = o_phrase;
|
|
addr_op.phrase = IPH_AR_INCR;
|
|
}
|
|
else if ( ISN_INDIR_DECR(opcode) )
|
|
{
|
|
//
|
|
// The AR decrement flag is set.
|
|
// This is an AR decrement reference.
|
|
//
|
|
addr_op.type = o_phrase;
|
|
addr_op.phrase = IPH_AR_DECR;
|
|
}
|
|
else
|
|
{
|
|
//
|
|
// Neither the AR auto-increment or auto-decrement
|
|
// flags is set. That makes this a regular AR
|
|
// indirect reference.
|
|
//
|
|
addr_op.type = o_phrase;
|
|
addr_op.phrase = IPH_AR;
|
|
}
|
|
//
|
|
// Next, decode the auxiliary register pointer change command,
|
|
// if present, as the instruction's second operand. If no
|
|
// change is requested in this instruction, then the second operand
|
|
// will not be filled in.
|
|
//
|
|
if ( ana_op_narp(insn, narp_op, opcode) == 0 )
|
|
{
|
|
//
|
|
// The operand was invalid.
|
|
//
|
|
return 0;
|
|
}
|
|
}
|
|
|
|
//
|
|
// Successful operand decode.
|
|
// Return the instruction size.
|
|
//
|
|
return insn.size;
|
|
}
|
|
|
|
//
|
|
// ana_op_narp(operand, opcode)
|
|
//
|
|
// Decodes the 'auxiliary-register-pointer-change' command that may
|
|
// be embededded in the opcode 'opcode' and places the information
|
|
// about the change in the operand 'operand'. If the instruction does
|
|
// not have a pointer change request, then 'operand' is left alone.
|
|
//
|
|
// Returns instruction size on successful decode, 0 on illegal condition.
|
|
//
|
|
static int ana_op_narp(const insn_t &insn, op_t &op, uint16 opcode)
|
|
{
|
|
//
|
|
// Determine if the instruction contains a request
|
|
// to change the ARP register after execution.
|
|
//
|
|
if ( ISN_INDIR_NARP(opcode) )
|
|
{
|
|
//
|
|
// The instruction contains the request.
|
|
// Reflect the request in the operand provided.
|
|
//
|
|
op.type = o_reg;
|
|
if ( ISN_INDIR_ARP(opcode) )
|
|
{
|
|
// Change to AR1
|
|
op.reg = IREG_AR1;
|
|
}
|
|
else
|
|
{
|
|
// Change to AR0
|
|
op.reg = IREG_AR0;
|
|
}
|
|
}
|
|
|
|
//
|
|
// Successful operand decode.
|
|
// Return the instruction size.
|
|
//
|
|
return insn.size;
|
|
}
|
|
|