146 lines
7.6 KiB
C++
146 lines
7.6 KiB
C++
/*
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* TLCS900 processor module for IDA.
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* Copyright (c) 1998-2006 Konstantin Norvatoff, <konnor@bk.ru>
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* Freeware.
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*/
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#include "tosh.hpp"
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// Attention!!! Word instruction must be followed
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// byte instruction, used in ana.cpp
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const instruc_t Instructions[] =
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{
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{ "", 0 }, // Unknown Operation
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{ "LD", CF_USE1|CF_CHG1|CF_USE2 }, // Load data
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{ "LDW", CF_USE1|CF_CHG1|CF_USE2 }, // Load data
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{ "PUSH", CF_USE1 }, // Push data
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{ "PUSHW", CF_USE1 }, // Push data
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{ "POP", CF_USE1|CF_CHG1 }, // pop data
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{ "POPW", CF_USE1|CF_CHG1 }, // pop data
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{ "LDA", CF_USE1|CF_CHG1|CF_USE2 }, // load data from mem
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{ "LDAR", CF_USE1|CF_CHG1|CF_USE2 }, // load data from mem rel.
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{ "EX", CF_USE1|CF_CHG1|CF_USE2|CF_CHG2 }, // xchg
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{ "MIRR", CF_USE1|CF_CHG1 }, // mirror
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{ "LDI", CF_USE1|CF_USE2|CF_CHG1|CF_CHG2 }, // copy
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{ "LDIW", CF_USE1|CF_USE2|CF_CHG1|CF_CHG2 }, // copy
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{ "LDIR", CF_USE1|CF_USE2|CF_CHG1|CF_CHG2 }, // copy
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{ "LDIRW", CF_USE1|CF_USE2|CF_CHG1|CF_CHG2 }, // copy
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{ "LDD", CF_USE1|CF_USE2|CF_CHG1|CF_CHG2 }, // copy
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{ "LDDW", CF_USE1|CF_USE2|CF_CHG1|CF_CHG2 }, // copy
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{ "LDDR", CF_USE1|CF_USE2|CF_CHG1|CF_CHG2 }, // copy
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{ "LDDRW", CF_USE1|CF_USE2|CF_CHG1|CF_CHG2 }, // copy
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{ "CPI", CF_USE1|CF_USE2|CF_CHG1|CF_CHG2 }, // compare
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{ "CPIR", CF_USE1|CF_USE2|CF_CHG1|CF_CHG2 }, // compare
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{ "CPD", CF_USE1|CF_USE2|CF_CHG1|CF_CHG2 }, // compare
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{ "CPDR", CF_USE1|CF_USE2|CF_CHG1|CF_CHG2 }, // compare
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{ "ADD", CF_USE1|CF_CHG1|CF_USE2 },
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{ "ADDW", CF_USE1|CF_CHG1|CF_USE2 },
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{ "ADC", CF_USE1|CF_CHG1|CF_USE2 },
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{ "ADCW", CF_USE1|CF_CHG1|CF_USE2 },
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{ "SUB", CF_USE1|CF_CHG1|CF_USE2 },
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{ "SUBW", CF_USE1|CF_CHG1|CF_USE2 },
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{ "SBC", CF_USE1|CF_CHG1|CF_USE2 },
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{ "SBCW", CF_USE1|CF_CHG1|CF_USE2 },
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{ "CP", CF_USE1|CF_USE2 }, // cmp
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{ "CPW", CF_USE1|CF_USE2 }, // cmp
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{ "INC", CF_USE1|CF_USE2|CF_CHG2 },
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{ "INCW", CF_USE1|CF_USE2|CF_CHG2 },
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{ "DEC", CF_USE1|CF_USE2|CF_CHG2 },
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{ "DECW", CF_USE1|CF_USE2|CF_CHG2 },
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{ "NEG", CF_USE1|CF_CHG1 },
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{ "EXTZ", CF_USE1|CF_CHG1 },
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{ "EXTS", CF_USE1|CF_CHG1 },
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{ "DAA", CF_USE1|CF_CHG1 },
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{ "PAA", CF_USE1|CF_CHG1 },
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{ "CPL", CF_USE1|CF_CHG1 },
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{ "MUL", CF_USE1|CF_CHG1|CF_USE2 },
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{ "MULS", CF_USE1|CF_CHG1|CF_USE2 },
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{ "DIV", CF_USE1|CF_CHG1|CF_USE2 },
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{ "DIVS", CF_USE1|CF_CHG1|CF_USE2 },
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{ "MULA", CF_USE1|CF_CHG1 }, // rr+=(XDE)*(XHL--)
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{ "MINC1", CF_USE1|CF_USE2|CF_CHG2 },
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{ "MINC2", CF_USE1|CF_USE2|CF_CHG2 },
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{ "MINC4", CF_USE1|CF_USE2|CF_CHG2 },
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{ "MDEC1", CF_USE1|CF_USE2|CF_CHG2 },
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{ "MDEC2", CF_USE1|CF_USE2|CF_CHG2 },
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{ "MDEC4", CF_USE1|CF_USE2|CF_CHG2 },
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{ "AND", CF_USE1|CF_CHG1|CF_USE2 },
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{ "ANDW", CF_USE1|CF_CHG1|CF_USE2 },
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{ "OR", CF_USE1|CF_CHG1|CF_USE2 },
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{ "ORW", CF_USE1|CF_CHG1|CF_USE2 },
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{ "XOR", CF_USE1|CF_CHG1|CF_USE2 },
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{ "XORW", CF_USE1|CF_CHG1|CF_USE2 },
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{ "LDCF", CF_USE1|CF_USE2 },
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{ "STCF", CF_USE1|CF_USE2|CF_CHG2 },
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{ "ANDCF", CF_USE1|CF_USE2 },
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{ "ORCF", CF_USE1|CF_USE2 },
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{ "XORCF", CF_USE1|CF_USE2 },
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{ "RCF", 0 },
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{ "SCF", 0 },
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{ "CCF", 0 },
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{ "ZCF", 0 },
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{ "BIT", CF_USE1|CF_USE2 },
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{ "RES", CF_USE1|CF_USE2|CF_CHG2 },
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{ "SET", CF_USE1|CF_USE2|CF_CHG2 },
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{ "CHG", CF_USE1|CF_USE2|CF_CHG2 },
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{ "TSET", CF_USE1|CF_USE2|CF_CHG2 },
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{ "BS1F", CF_USE1|CF_CHG1|CF_USE2 },
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{ "BS1B", CF_USE1|CF_CHG1|CF_USE2 },
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{ "NOP", 0 },
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{ "EI", CF_USE1 },
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{ "DI", 0 },
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{ "SWI", CF_USE1|CF_CALL }, // interrupt
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{ "HALT", CF_STOP },
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{ "LDC", CF_USE1|CF_USE2 }, // actually changes
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{ "LDX", CF_USE1|CF_CHG1|CF_USE2 },
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{ "LINK", CF_USE1|CF_CHG1|CF_USE2|CF_HLL },
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{ "UNLK", CF_USE1|CF_CHG1|CF_HLL },
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{ "LDF", CF_USE1 }, // set reg bank
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{ "INCF", 0 },
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{ "DECF", 0 },
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{ "SCC", CF_USE1|CF_USE2|CF_CHG2 },
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{ "RLC", CF_USE1|CF_USE2|CF_CHG2 },
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{ "RLC", CF_USE1|CF_CHG1 },
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{ "RLCW", CF_USE1|CF_CHG2 },
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{ "RRC", CF_USE1|CF_USE2|CF_CHG2 },
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{ "RRC", CF_USE1|CF_CHG1 },
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{ "RRCW", CF_USE1|CF_CHG2 },
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{ "RL", CF_USE1|CF_USE2|CF_CHG2 },
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{ "RL", CF_USE1|CF_CHG1 },
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{ "RLW", CF_USE1|CF_CHG2 },
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{ "RR", CF_USE1|CF_USE2|CF_CHG2 },
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{ "RR", CF_USE1|CF_CHG1 },
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{ "RRW", CF_USE1|CF_CHG2 },
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{ "SLA", CF_USE1|CF_USE2|CF_CHG2 },
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{ "SLA", CF_USE1|CF_CHG1 },
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{ "SLAW", CF_USE1|CF_CHG2 },
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{ "SRA", CF_USE1|CF_USE2|CF_CHG2 },
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{ "SRA", CF_USE1|CF_CHG1 },
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{ "SRAW", CF_USE1|CF_CHG2 },
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{ "SLL", CF_USE1|CF_USE2|CF_CHG2 },
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{ "SLL", CF_USE1|CF_CHG1 },
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{ "SLLW", CF_USE1|CF_CHG2 },
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{ "SRL", CF_USE1|CF_USE2|CF_CHG2 },
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{ "SRL", CF_USE1|CF_CHG1 },
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{ "SRLW", CF_USE1|CF_CHG2 },
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{ "RLD", CF_USE1|CF_CHG1|CF_USE2|CF_CHG2 },
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{ "RRD", CF_USE1|CF_CHG1|CF_USE2|CF_CHG2 },
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{ "JP", CF_USE1|CF_JUMP|CF_STOP },
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{ "JP", CF_USE1|CF_USE2|CF_JUMP },
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{ "JR", CF_USE1|CF_USE2|CF_JUMP|CF_STOP },
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{ "JR", CF_USE1|CF_USE2|CF_JUMP },
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{ "JRL", CF_USE1|CF_USE2|CF_JUMP|CF_STOP },
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{ "JRL", CF_USE1|CF_USE2|CF_JUMP },
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{ "CALL", CF_USE1|CF_USE2|CF_CALL },
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{ "CALR", CF_USE1|CF_CALL },
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{ "DJNZ", CF_USE1|CF_CHG1|CF_USE2|CF_JUMP },
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{ "RET", CF_STOP },
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{ "RET", CF_USE1 },
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{ "RETD", CF_USE1|CF_STOP },
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{ "RETI", CF_STOP|CF_USE1 },
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{ "MAX", 0 }, // from IAR
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{ "NORMAL", 0 } // from IAR
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};
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CASSERT(qnumber(Instructions) == T900_last);
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