701 lines
9.4 KiB
C++
701 lines
9.4 KiB
C++
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#ifndef __ST9_HPP
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#define __ST9_HPP
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#include "../idaidp.hpp"
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#include "ins.hpp"
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#include <diskio.hpp>
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#include <frame.hpp>
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#include <segregs.hpp>
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#include <struct.hpp>
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#include "../iohandler.hpp"
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#define PROCMOD_NAME st9
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#define PROCMOD_NODE_NAME "$ st9"
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// Operand flags
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#define OP_IS_IND 0x00000001 // Operand is indirect, and should be
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// printed between ().
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#define OP_IMM_NO_SHIFT 0x00000002 // Operand is immediate, and should not
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// be prefixed by the '#' character.
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#define OP_REG_WITH_BIT 0x00000004 // Operand is register, and a bit number can be
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// found in the "value" field.
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#define OP_BIT_COMPL 0x00000008 // Bit number is a complement, and should be
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// prefixed by the '!' character.
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#define OP_DISPL_FUNC_ARG 0x00000010 // Operand is a displacement, and should be considered
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// as a function argument variable.
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// Flags for ash.uFlag
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#define UAS_ASW 0x00000001 // current assembler is ASW.
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inline bool is_ind(const op_t &op)
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{
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return (op.specflag1 & OP_IS_IND) != 0;
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}
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inline bool is_imm_no_shift(const op_t &op)
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{
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return op.type == o_imm && (op.specflag1 & OP_IMM_NO_SHIFT) != 0;
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}
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inline bool is_reg_with_bit(const op_t &op)
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{
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return op.type == o_reg && (op.specflag1 & OP_REG_WITH_BIT) != 0;
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}
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inline bool is_bit_compl(const op_t &op)
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{
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return (op.specflag1 & OP_BIT_COMPL) != 0;
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}
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// ST9+ registers :
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enum st9_registers
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{
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rR0,
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rR1,
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rR2,
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rR3,
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rR4,
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rR5,
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rR6,
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rR7,
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rR8,
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rR9,
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rR10,
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rR11,
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rR12,
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rR13,
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rR14,
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rR15,
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rR16,
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rR17,
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rR18,
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rR19,
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rR20,
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rR21,
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rR22,
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rR23,
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rR24,
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rR25,
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rR26,
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rR27,
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rR28,
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rR29,
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rR30,
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rR31,
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rR32,
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rR33,
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rR34,
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rR35,
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rR36,
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rR37,
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rR38,
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rR39,
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rR40,
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rR41,
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rR42,
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rR43,
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rR44,
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rR45,
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rR46,
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rR47,
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rR48,
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rR49,
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rR50,
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rR51,
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rR52,
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rR53,
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rR54,
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rR55,
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rR56,
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rR57,
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rR58,
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rR59,
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rR60,
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rR61,
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rR62,
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rR63,
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rR64,
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rR65,
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rR66,
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rR67,
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rR68,
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rR69,
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rR70,
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rR71,
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rR72,
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rR73,
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rR74,
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rR75,
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rR76,
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rR77,
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rR78,
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rR79,
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rR80,
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rR81,
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rR82,
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rR83,
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rR84,
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rR85,
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rR86,
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rR87,
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rR88,
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rR89,
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rR90,
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rR91,
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rR92,
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rR93,
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rR94,
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rR95,
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rR96,
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rR97,
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rR98,
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rR99,
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rR100,
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rR101,
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rR102,
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rR103,
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rR104,
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rR105,
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rR106,
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rR107,
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rR108,
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rR109,
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rR110,
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rR111,
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rR112,
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rR113,
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rR114,
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rR115,
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rR116,
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rR117,
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rR118,
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rR119,
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rR120,
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rR121,
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rR122,
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rR123,
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rR124,
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rR125,
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rR126,
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rR127,
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rR128,
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rR129,
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rR130,
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rR131,
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rR132,
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rR133,
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rR134,
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rR135,
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rR136,
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rR137,
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rR138,
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rR139,
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rR140,
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rR141,
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rR142,
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rR143,
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rR144,
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rR145,
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rR146,
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rR147,
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rR148,
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rR149,
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rR150,
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rR151,
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rR152,
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rR153,
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rR154,
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rR155,
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rR156,
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rR157,
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rR158,
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rR159,
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rR160,
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rR161,
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rR162,
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rR163,
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rR164,
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rR165,
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rR166,
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rR167,
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rR168,
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rR169,
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rR170,
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rR171,
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rR172,
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rR173,
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rR174,
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rR175,
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rR176,
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rR177,
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rR178,
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rR179,
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rR180,
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rR181,
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rR182,
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rR183,
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rR184,
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rR185,
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rR186,
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rR187,
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rR188,
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rR189,
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rR190,
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rR191,
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rR192,
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rR193,
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rR194,
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rR195,
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rR196,
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rR197,
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rR198,
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rR199,
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rR200,
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rR201,
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rR202,
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rR203,
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rR204,
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rR205,
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rR206,
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rR207,
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rR208,
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rR209,
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rR210,
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rR211,
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rR212,
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rR213,
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rR214,
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rR215,
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rR216,
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rR217,
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rR218,
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rR219,
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rR220,
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rR221,
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rR222,
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rR223,
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rR224,
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rR225,
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rR226,
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rR227,
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rR228,
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rR229,
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rR230,
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rR231,
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rR232,
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rR233,
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rR234,
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rR235,
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rR236,
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rR237,
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rR238,
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rR239,
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rR240,
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rR241,
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rR242,
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rR243,
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rR244,
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rR245,
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rR246,
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rR247,
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rR248,
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rR249,
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rR250,
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rR251,
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rR252,
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rR253,
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rR254,
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rR255,
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rRR0,
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rRR1,
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rRR2,
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rRR3,
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rRR4,
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rRR5,
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rRR6,
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rRR7,
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rRR8,
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rRR9,
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rRR10,
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rRR11,
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rRR12,
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rRR13,
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rRR14,
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rRR15,
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rRR16,
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rRR17,
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rRR18,
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rRR19,
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rRR20,
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rRR21,
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rRR22,
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rRR23,
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rRR24,
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rRR25,
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rRR26,
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rRR27,
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rRR28,
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rRR29,
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rRR30,
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rRR31,
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rRR32,
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rRR33,
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rRR34,
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rRR35,
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rRR36,
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rRR37,
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rRR38,
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rRR39,
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rRR40,
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rRR41,
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rRR42,
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rRR43,
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rRR44,
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rRR45,
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rRR46,
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rRR47,
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rRR48,
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rRR49,
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rRR50,
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rRR51,
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rRR52,
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rRR53,
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rRR54,
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rRR55,
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rRR56,
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rRR57,
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rRR58,
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rRR59,
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rRR60,
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rRR61,
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rRR62,
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rRR63,
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rRR64,
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rRR65,
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rRR66,
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rRR67,
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rRR68,
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rRR69,
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rRR70,
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rRR71,
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rRR72,
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rRR73,
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rRR74,
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rRR75,
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rRR76,
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rRR77,
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rRR78,
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rRR79,
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rRR80,
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rRR81,
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rRR82,
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rRR83,
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rRR84,
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rRR85,
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rRR86,
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rRR87,
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rRR88,
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rRR89,
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rRR90,
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rRR91,
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rRR92,
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rRR93,
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rRR94,
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rRR95,
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rRR96,
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rRR97,
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rRR98,
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rRR99,
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rRR100,
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rRR101,
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rRR102,
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rRR103,
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rRR104,
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rRR105,
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rRR106,
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rRR107,
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rRR108,
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rRR109,
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rRR110,
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rRR111,
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rRR112,
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rRR113,
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rRR114,
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rRR115,
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rRR116,
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rRR117,
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rRR118,
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rRR119,
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rRR120,
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rRR121,
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rRR122,
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rRR123,
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rRR124,
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rRR125,
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rRR126,
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rRR127,
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rRR128,
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rRR129,
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rRR130,
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rRR131,
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rRR132,
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rRR133,
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rRR134,
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rRR135,
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rRR136,
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rRR137,
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rRR138,
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rRR139,
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rRR140,
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rRR141,
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rRR142,
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rRR143,
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rRR144,
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rRR145,
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rRR146,
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rRR147,
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rRR148,
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rRR149,
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rRR150,
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rRR151,
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rRR152,
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rRR153,
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rRR154,
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rRR155,
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rRR156,
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rRR157,
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rRR158,
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rRR159,
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rRR160,
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rRR161,
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rRR162,
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rRR163,
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rRR164,
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rRR165,
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rRR166,
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rRR167,
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rRR168,
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rRR169,
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rRR170,
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rRR171,
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rRR172,
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rRR173,
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rRR174,
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rRR175,
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rRR176,
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rRR177,
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rRR178,
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rRR179,
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rRR180,
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rRR181,
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rRR182,
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rRR183,
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rRR184,
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rRR185,
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rRR186,
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rRR187,
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rRR188,
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rRR189,
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rRR190,
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rRR191,
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rRR192,
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rRR193,
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rRR194,
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rRR195,
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rRR196,
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rRR197,
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rRR198,
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rRR199,
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rRR200,
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rRR201,
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rRR202,
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rRR203,
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rRR204,
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rRR205,
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rRR206,
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rRR207,
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rRR208,
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rRR209,
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rRR210,
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rRR211,
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rRR212,
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rRR213,
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rRR214,
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rRR215,
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rRR216,
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rRR217,
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rRR218,
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rRR219,
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rRR220,
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rRR221,
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rRR222,
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rRR223,
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rRR224,
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rRR225,
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rRR226,
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rRR227,
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rRR228,
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rRR229,
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rRR230,
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rRR231,
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rRR232,
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rRR233,
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rRR234,
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rRR235,
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rRR236,
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rRR237,
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rRR238,
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rRR239,
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rRR240,
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rRR241,
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rRR242,
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rRR243,
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rRR244,
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rRR245,
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rRR246,
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rRR247,
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rRR248,
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rRR249,
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rRR250,
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rRR251,
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rRR252,
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rRR253,
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rRR254,
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rRR255,
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rr0,
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rr1,
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rr2,
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rr3,
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rr4,
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rr5,
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rr6,
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rr7,
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rr8,
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rr9,
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rr10,
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rr11,
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rr12,
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rr13,
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rr14,
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rr15,
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rrr0,
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rrr1,
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rrr2,
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rrr3,
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rrr4,
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rrr5,
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rrr6,
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rrr7,
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rrr8,
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rrr9,
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rrr10,
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rrr11,
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rrr12,
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rrr13,
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rrr14,
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rrr15,
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rRW, // register window number
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rRP, // register page
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rCSR, // code segment register
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rDPR0, rDPR1, rDPR2, rDPR3, // Data page registers
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st9_lastreg = rDPR3,
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};
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// ST9 condition codes
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enum st9_cond_codes
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{
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cUNKNOWN,
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cF, // always false
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cT, // always true
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cC, // carry
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cNC, // not carry
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cZ, // zero
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cNZ, // not zero
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cPL, // plus
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cMI, // minus
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cOV, // overflow
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cNOV, // no overflow
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cEQ, // equal
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cNE, // not equal
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cGE, // greater than or equal
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cLT, // less than
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cGT, // greater than
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cLE, // less than or equal
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cUGE, // unsigned greated than or equal
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cUL, // unsigned less than
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cUGT, // unsigned greater than
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cULE // unsigned less than or equal
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};
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enum st9_phrases ENUM_SIZE(uint8)
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{
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fPI, // post incrementation (rr)+
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fPD, // pre decrementation -(rr)
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fDISP // displacement rrx(rry)
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};
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|
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inline bool is_jmp_cc(int insn)
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{
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return insn == st9_jpcc || insn == st9_jrcc;
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}
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//------------------------------------------------------------------
|
|
struct st9_iohandler_t : public iohandler_t
|
|
{
|
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struct st9_t ±
|
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st9_iohandler_t(st9_t &_pm, netnode &nn) : iohandler_t(nn), pm(_pm) {}
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};
|
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|
|
struct st9_t : public procmod_t
|
|
{
|
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// The netnode helper.
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// Using this node we will save current configuration information in the
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// IDA database.
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netnode helper;
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st9_iohandler_t ioh = st9_iohandler_t(*this, helper);
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const char *RegNames[st9_lastreg + 1];
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qstrvec_t dynamic_rgnames; // dynamically generated names for rR1..rR255
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const char *gr_cmt = nullptr;
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int ref_dpr_id; // id of refinfo handler
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#define IDP_GR_DEC 0x0001 // print general registers in decimal format
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#define IDP_GR_HEX 0x0002 // print general registers in hexadecimal format
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#define IDP_GR_BIN 0x0004 // print general registers in binary format
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uint32 idpflags = IDP_GR_DEC;
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ushort print_style = 3;
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bool flow;
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virtual ssize_t idaapi on_event(ssize_t msgid, va_list va) override;
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const ioport_t *find_sym(ea_t address);
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void patch_general_registers();
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const char *set_idp_options(
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const char *keyword,
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int /*value_type*/,
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const void * /*value*/,
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bool idb_loaded);
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int st9_emu(const insn_t &insn);
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void handle_operand(const insn_t &insn, const op_t &op, bool lwrite);
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bool create_func_frame(func_t *pfn) const;
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void st9_assumes(outctx_t &ctx);
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void st9_footer(outctx_t &ctx) const;
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void st9_segstart(outctx_t &ctx, segment_t *Sarea) const;
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void save_idpflags() { helper.altset(-1, idpflags); }
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void load_from_idb();
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};
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extern int data_id;
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// exporting our routines
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void idaapi st9_header(outctx_t &ctx);
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int idaapi st9_ana(insn_t *insn);
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ea_t get_dest_addr(const insn_t &insn, const op_t &x);
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bool st9_is_switch(switch_info_t *si, const insn_t &insn);
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extern const char *const ConditionCodes[];
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#endif /* __ST9_HPP */
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