152 lines
11 KiB
C++
152 lines
11 KiB
C++
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#include "m32r.hpp"
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// m32r instructions definition
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const instruc_t Instructions[] =
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{
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{ "", 0 }, // Null instruction
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{ "add", CF_USE1|CF_USE2|CF_CHG1 }, // Add
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{ "add3", CF_USE2|CF_USE3|CF_CHG1 }, // Add 3-operand
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{ "addi", CF_USE1|CF_USE2|CF_CHG1 }, // Add immediate
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{ "addv", CF_USE1|CF_USE2|CF_CHG1 }, // Add with overflow checking
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{ "addv3", CF_USE2|CF_USE3|CF_CHG1 }, // Add 3-operand with overflow checking
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{ "addx", CF_USE1|CF_USE2|CF_CHG1 }, // Add with carry
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{ "and", CF_USE1|CF_USE2|CF_CHG1 }, // AND
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{ "and3", CF_USE2|CF_USE3|CF_CHG1 }, // AND 3-operand
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{ "bc", CF_USE1 }, // Branch on C-bit
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{ "beq", CF_USE1|CF_USE2|CF_USE3 }, // Branch on equal
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{ "beqz", CF_USE1|CF_USE2 }, // Branch on equal zero
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{ "bgez", CF_USE1|CF_USE2 }, // Branch on greater than or equal zero
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{ "bgtz", CF_USE1|CF_USE2 }, // Branch on greater than zero
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{ "bl", CF_USE1|CF_CALL }, // Branch and link
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{ "blez", CF_USE1|CF_USE2 }, // Branch on less than or equal zero
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{ "bltz", CF_USE1|CF_USE2 }, // Branch on less than zero
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{ "bnc", CF_USE1 }, // Branch on not C-bit
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{ "bne", CF_USE1|CF_USE2|CF_USE3 }, // Branch on not equal
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{ "bnez", CF_USE1|CF_USE2 }, // Branch on not equal zero
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{ "bra", CF_USE1|CF_STOP }, // Branch
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{ "cmp", CF_USE1|CF_USE2 }, // Compare
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{ "cmpi", CF_USE1|CF_USE2 }, // Compare immediate
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{ "cmpu", CF_USE1|CF_USE2 }, // Compare unsigned
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{ "cmpui", CF_USE1|CF_USE2 }, // Compare unsigned immediate
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{ "div", CF_USE1|CF_USE2|CF_CHG1 }, // Divide
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{ "divu", CF_USE1|CF_USE2|CF_CHG1 }, // Divide unsigned
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{ "jl", CF_USE1|CF_CALL|CF_JUMP }, // Jump and link
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{ "jmp", CF_USE1|CF_JUMP|CF_STOP }, // Jump
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{ "ld", CF_USE2|CF_CHG1 }, // Load
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{ "ld24", CF_USE2|CF_CHG1 }, // Load 24-bit immediate
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{ "ldb", CF_USE2|CF_CHG1 }, // Load byte
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{ "ldh", CF_USE2|CF_CHG1 }, // Load halfword
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{ "ldi", CF_USE2|CF_CHG1 }, // Load immediate
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{ "ldub", CF_USE2|CF_CHG1 }, // Load unsigned byte
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{ "lduh", CF_USE2|CF_CHG1 }, // Load unsigned halfword
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{ "lock", CF_USE2|CF_CHG1 }, // Load locked
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{ "machi", CF_USE1|CF_USE2 }, // Multiply-accumulate high-order halfwords
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{ "maclo", CF_USE1|CF_USE2 }, // Multiply-accumulate low-order halfwords
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{ "macwhi", CF_USE1|CF_USE2 }, // Multiply-accumulate word and high-order halfword
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{ "macwlo", CF_USE1|CF_USE2 }, // Multiply-accumulate word and low-order halfword
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{ "mul", CF_USE1|CF_USE2|CF_CHG1 }, // Multiply
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{ "mulhi", CF_USE1|CF_USE2 }, // Multiply high-order halfwords
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{ "mullo", CF_USE1|CF_USE2 }, // Multiply low-order halfwords
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{ "mulwhi", CF_USE1|CF_USE2 }, // Multiply word high-order halfwords
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{ "mulwlo", CF_USE1|CF_USE2 }, // Multiply word low-order halfwords
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{ "mv", CF_USE2|CF_CHG1 }, // Move register
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{ "mvfachi", CF_CHG1 }, // Move from accumulator high-order word
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{ "mvfaclo", CF_CHG1 }, // Move from accumulator low-order word
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{ "mvfacmi", CF_CHG1 }, // Move from accumulator middle-order word
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{ "mvfc", CF_USE2|CF_CHG1 }, // Move from control register
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{ "mvtachi", CF_USE1 }, // Move to accumulator high-order word
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{ "mvtaclo", CF_USE1 }, // Move to accumulator low-order word
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{ "mvtc", CF_USE2|CF_CHG1 }, // Move to control register
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{ "neg", CF_USE2|CF_CHG1 }, // Negate
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{ "nop", 0 }, // No operation
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{ "not", CF_USE2|CF_CHG1 }, // Logical NOT
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{ "or", CF_USE1|CF_USE2|CF_CHG1 }, // OR
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{ "or3", CF_USE2|CF_USE3|CF_CHG1 }, // OR 3-operand
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{ "push", CF_USE1 }, // Push, mnem for st reg, @-sp
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{ "pop", CF_CHG1 }, // Pop, mnem for ld reg, @sp+
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{ "rac", 0 }, // Round accumulator
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{ "rach", 0 }, // Round accumulator halfword
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{ "rem", CF_USE1|CF_USE2|CF_CHG1 }, // Remainder
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{ "remu", CF_USE1|CF_USE2|CF_CHG1 }, // Remainder unsigned
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{ "rte", CF_STOP }, // Return from EIT
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{ "seth", CF_USE2|CF_CHG1 }, // Set high-order 16-bit
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{ "sll", CF_USE1|CF_USE2|CF_CHG1 }, // Shift left logical
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{ "sll3", CF_USE2|CF_USE3|CF_CHG1 }, // Shift left logical 3-operand
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{ "slli", CF_USE1|CF_USE2|CF_CHG1 }, // Shift left logical immediate
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{ "sra", CF_USE1|CF_USE2|CF_CHG1 }, // Shirt right arithmetic
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{ "sra3", CF_USE2|CF_USE3|CF_CHG1 }, // Shirt right arithmetic 3-operand
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{ "srai", CF_USE1|CF_USE2|CF_CHG1 }, // Shirt right arithmetic immediate
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{ "srl", CF_USE1|CF_USE2|CF_CHG1 }, // Shift right logical
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{ "srl3", CF_USE2|CF_USE3|CF_CHG1 }, // Shift right logical 3-operand
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{ "srli", CF_USE1|CF_USE2|CF_CHG1 }, // Shift right logical immediate
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{ "st", CF_USE1|CF_USE2|CF_CHG1 }, // Store
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{ "stb", CF_USE1|CF_CHG2 }, // Store byte
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{ "sth", CF_USE1|CF_CHG2 }, // Store halfword
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{ "sub", CF_USE1|CF_USE2|CF_CHG1 }, // Substract
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{ "subv", CF_USE1|CF_USE2|CF_CHG1 }, // Substract with overflow checking
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{ "subx", CF_USE1|CF_USE2|CF_CHG1 }, // Substract with borrow
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{ "trap", CF_USE1 }, // Trap
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{ "unlock", CF_USE1|CF_CHG2 }, // Store unlocked
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{ "xor", CF_USE1|CF_USE2|CF_CHG1 }, // Exclusive OR
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{ "xor3", CF_USE2|CF_USE3|CF_CHG1 }, // Exclusive OR 3-operand
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// M32RX :
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{ "bcl", CF_USE1 },
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{ "bncl", CF_USE1 },
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{ "cmpeq", CF_USE1|CF_USE2 },
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{ "cmpz", CF_USE1 },
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{ "divh", CF_USE1|CF_USE2|CF_CHG1 },
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{ "jc", CF_USE1 },
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{ "jnc", CF_USE1 },
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{ "machi", CF_USE1|CF_USE2|CF_USE3|CF_CHG3 }, // 'machi' 3-operand
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{ "maclo", CF_USE1|CF_USE2|CF_USE3|CF_CHG3 }, // 'maclo' 3-operand
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{ "macwhi", CF_USE1|CF_USE2|CF_USE3|CF_CHG3 }, // 'macwhi' 3-operand
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{ "macwlo", CF_USE1|CF_USE2|CF_USE3|CF_CHG3 }, // 'macwlo' 3-operand
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{ "mulhi", CF_USE1|CF_USE2|CF_USE3|CF_CHG3 }, // 'mulhi' 3-operand
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{ "mullo", CF_USE1|CF_USE2|CF_USE3|CF_CHG3 }, // 'mullo' 3-operand
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{ "mulwhi", CF_USE1|CF_USE2|CF_USE3|CF_CHG3 }, // 'mulwhi' 3-operand
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{ "mulwlo", CF_USE1|CF_USE2|CF_USE3|CF_CHG3 }, // 'mulwlo' 3-operand
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{ "mvfachi", CF_USE2|CF_CHG1 }, // 'mvfachi' 3-operand
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{ "mvfaclo", CF_USE2|CF_CHG1 }, // 'mvfaclo' 3-operand
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{ "mvfacmi", CF_USE2|CF_CHG1 }, // 'mvfacmi' 3-operand
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{ "mvtachi", CF_USE1|CF_CHG2 }, // 'mvtachi' 3-operand
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{ "mvtaclo", CF_USE1|CF_CHG2 }, // 'mvtaclo' 3-operand
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{ "rac", CF_USE2|CF_CHG1 }, // 'rac' 3 operand
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{ "rach", CF_USE2|CF_CHG1 }, // 'rach' 3 operand
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{ "satb", CF_USE2|CF_CHG1 },
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{ "sath", CF_USE2|CF_CHG1 },
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{ "sat", CF_USE2|CF_CHG1 },
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{ "pcmpbz", CF_USE1 },
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{ "sadd", 0 },
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{ "macwu1", CF_USE1|CF_USE2 },
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{ "msblo", CF_USE1|CF_USE2 },
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{ "mulwu1", CF_USE1|CF_USE2 },
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{ "maclh1", CF_USE1|CF_USE2 },
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{ "sc", 0 },
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{ "snc", 0 },
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// Floating point
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{ "fadd", CF_CHG1|CF_USE2|CF_USE3 }, // Floating-point add
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{ "fsub", CF_CHG1|CF_USE2|CF_USE3 }, // Floating-point subtract
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{ "fmul", CF_CHG1|CF_USE2|CF_USE3 }, // Floating-point multiply
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{ "fdiv", CF_CHG1|CF_USE2|CF_USE3 }, // Floating-point divede
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{ "fmadd", CF_CHG1|CF_USE2|CF_USE3 }, // Floating-point multiply and add
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{ "fmsub", CF_CHG1|CF_USE2|CF_USE3 }, // Floating-point multiply and subtract
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{ "itof", CF_CHG1|CF_USE2 }, // Integer to float
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{ "utof", CF_CHG1|CF_USE2 }, // Unsigned integer to float
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{ "ftoi", CF_CHG1|CF_USE2 }, // Float to integer
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{ "ftos", CF_CHG1|CF_USE2 }, // Float to short
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{ "fcmp", CF_CHG1|CF_USE2|CF_USE3 }, // Floating-point compare
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{ "fcmpe", CF_CHG1|CF_USE2|CF_USE3 }, // Floating-point compare with exeption if unordered
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// Bit Operation Instructions
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{ "bset", CF_USE1|CF_CHG2 }, // Bit set
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{ "bclr", CF_USE1|CF_CHG2 }, // Bit clear
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{ "btst", CF_USE1|CF_USE2 }, // Bit test
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{ "setpsw", CF_USE1 }, // Set PSW
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{ "clrpsw", CF_USE1 }, // Clear PSW
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};
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CASSERT(qnumber(Instructions) == m32r_last);
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