129 lines
3.1 KiB
C++
129 lines
3.1 KiB
C++
/*
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* Interactive disassembler (IDA).
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* Copyright (c) 1990-2001 by Ilfak Guilfanov.
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* ALL RIGHTS RESERVED.
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* E-mail: ig@datarescue.com
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*
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*
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*/
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#include "i960.hpp"
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//----------------------------------------------------------------------
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ea_t calc_mem(const insn_t &insn, ea_t ea)
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{
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return to_ea(insn.cs, ea);
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}
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//----------------------------------------------------------------------
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void i960_t::handle_operand(const insn_t &insn, const op_t &x, bool isload)
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{
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ea_t ea;
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dref_t dref;
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if ( is_forced_operand(insn.ea, x.n) )
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return;
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switch ( x.type )
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{
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case o_reg:
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case o_phrase:
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break;
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case o_imm:
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{
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flags_t F = get_flags(insn.ea);
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QASSERT(10105, isload);
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set_immd(insn.ea);
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if ( op_adds_xrefs(F, x.n) )
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insn.add_off_drefs(x, dr_O, OOFS_IFSIGN|OOFW_IMM);
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}
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break;
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case o_mem:
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ea = calc_mem(insn, x.addr);
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insn.create_op_data(ea, x);
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dref = insn.itype == I960_lda ? dr_O : isload ? dr_R : dr_W;
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insn.add_dref(ea, x.offb, dref);
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break;
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case o_near:
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{
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cref_t ftype = fl_JN;
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ea = calc_mem(insn, x.addr);
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if ( has_insn_feature(insn.itype, CF_CALL) )
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{
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// don't add call xref to next instruction
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if ( ea == insn.ea + insn.size )
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break;
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flow = func_does_return(ea);
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ftype = fl_CN;
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}
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insn.add_cref(ea, x.offb, ftype);
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}
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break;
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case o_displ:
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{
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dref = insn.itype == I960_lda ? dr_O : isload ? dr_R : dr_W;
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set_immd(insn.ea);
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if ( x.reg == IP )
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{
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ea = insn.ea + 8 + x.addr;
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insn.add_dref(ea, x.offb, dref);
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}
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else
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{
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flags_t F = get_flags(insn.ea);
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if ( op_adds_xrefs(F, x.n) )
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insn.add_off_drefs(x, dref, OOFS_IFSIGN|OOF_SIGNED|OOF_ADDR|OOFW_32);
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}
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}
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break;
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default:
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INTERR(10364);
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}
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}
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//----------------------------------------------------------------------
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int i960_t::i960_emu(const insn_t &insn)
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{
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uint32 Feature = insn.get_canon_feature(ph);
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flow = ((Feature & CF_STOP) == 0);
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if ( Feature & CF_USE1 ) handle_operand(insn, insn.Op1, true);
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if ( Feature & CF_USE2 ) handle_operand(insn, insn.Op2, true);
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if ( Feature & CF_USE3 ) handle_operand(insn, insn.Op3, true);
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if ( Feature & CF_CHG1 ) handle_operand(insn, insn.Op1, false);
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if ( Feature & CF_CHG2 ) handle_operand(insn, insn.Op2, false);
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if ( Feature & CF_CHG3 ) handle_operand(insn, insn.Op3, false);
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//
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// Determine if the next instruction should be executed
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//
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if ( segtype(insn.ea) == SEG_XTRN )
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flow = false;
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if ( flow )
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add_cref(insn.ea,insn.ea+insn.size,fl_F);
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//
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// convert "lda imm, reg" to "lda mem, reg"
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//
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if ( insn.itype == I960_lda
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&& insn.Op1.type == o_imm
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&& !is_defarg(get_flags(insn.ea), 0)
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&& is_mapped(insn.Op1.value) )
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{
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op_plain_offset(insn.ea, 0, 0);
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}
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return 1;
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}
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//----------------------------------------------------------------------
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int idaapi is_align_insn(ea_t /*ea*/)
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{
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return false;
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}
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