168 lines
15 KiB
C++
168 lines
15 KiB
C++
/*
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* Interactive disassembler (IDA).
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* Version 3.05
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* Copyright (c) 1990-95 by Ilfak Guilfanov.
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* ALL RIGHTS RESERVED.
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* FIDO: 2:5020/209
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* E-mail: ig@estar.msk.su
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*
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*/
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#include "i860.hpp"
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const instruc_t Instructions[] =
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{
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{ "", 0 }, // Unknown Operation
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//
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// Intel 860 XP instructions
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//
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{ "adds", CF_USE1|CF_USE2|CF_CHG3 }, // Add Signed: o3 <- o1 + o2
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{ "addu", CF_USE1|CF_USE2|CF_CHG3 }, // Add Unsigned: o3 <- o1 + o2
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{ "and", CF_USE1|CF_USE2|CF_CHG3 }, // Logical AND: o3 <- o1 & o2
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{ "andh", CF_USE1|CF_USE2|CF_CHG3 }, // Logical AND High: o3 <- (o1<<16) & o2
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{ "andnot", CF_USE1|CF_USE2|CF_CHG3 }, // Logical AND NOT: o3 <- (!o1) & o2
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{ "andnoth", CF_USE1|CF_USE2|CF_CHG3 }, // Logical AND NOT High: o3 <- (!(o1<<16)) & o3
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{ "bc", CF_USE1 }, // Branch on CC
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{ "bc.t", CF_USE1 }, // Branch on CC,Taken:\nif CC then execute 1 more intruction\n jump to o1\nelse skip next instruction
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{ "bla", CF_USE1|CF_USE2|CF_CHG2|CF_USE3 }, // Branch on LCC and Add:\nLCC' <- boolean(o1+o2 < 0)\no2 += o1\nexecute 1 more instruction\nif LCC then\n LCC <- LCC'\n jump to o3\nelse LCC <- LCC'
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{ "bnc", CF_USE1 }, // Branch on NOT CC
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{ "bnc.t", CF_USE1 }, // Branch on NOT CC, Taken:\nif !CC then execute 1 more intruction\n jump to o1\nelse skip next instruction
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{ "br", CF_USE1 }, // Branch Direct Unconditionally:\nexec 1 more instruction, jump to o3
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{ "bri", CF_USE1|CF_JUMP }, // Branch Indirect Unconditionally
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{ "bte", CF_USE1|CF_USE2|CF_USE3 }, // Branch If Equal
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{ "btne", CF_USE1|CF_USE2|CF_USE3 }, // Branch If Not Equal
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{ "call", CF_USE1|CF_CALL }, // Call Subroutine
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{ "calli", CF_USE1|CF_JUMP|CF_CALL }, // Call Indirect Subroutine
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{ "fadd", CF_USE1|CF_USE2|CF_CHG3 }, // Floating-Point Add
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{ "faddp", CF_USE1|CF_USE2|CF_CHG3 }, // Add With Pixel Merge
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{ "faddz", CF_USE1|CF_USE2|CF_CHG3 }, // Add With Z Merge
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{ "famov", CF_USE1|CF_CHG2 }, // Floating-Point Adder Move
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{ "fiadd", CF_USE1|CF_USE2|CF_CHG3 }, // Long Integer Add
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{ "fisub", CF_USE1|CF_USE2|CF_CHG3 }, // Long Integer Subtract
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{ "fix", CF_USE1|CF_CHG2 }, // Floating-Point to Integer Conversion
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{ "fld", CF_USE1|CF_CHG2 }, // Floating-Point Load
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{ "flush", CF_USE1 }, // Cache Flush
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{ "fmlow.dd", CF_USE1|CF_USE2|CF_CHG3 }, // Floating-Point Multiply Low
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{ "fmul", CF_USE1|CF_USE2|CF_CHG3 }, // Floating-Point Multiply
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{ "form", CF_USE1|CF_CHG2 }, // Or with MERGE register: o2 <- o1 | MERGE; MERGE <- 0
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{ "frcp", CF_USE1|CF_CHG2 }, // Floating-Point Reciprocal: o2 <- 1 / o1
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{ "frsqr", CF_USE1|CF_CHG2 }, // Floating-Point Reciprocal Square Root: o2 <- 1 / sqrt(o1)
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{ "fst", CF_CHG1|CF_USE2 }, // Floating-Point Reciprocal Store
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{ "fsub", CF_USE1|CF_USE2|CF_CHG3 }, // Floating-Point Subtract
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{ "ftrunc", CF_USE1|CF_CHG2 }, // Floating-Point to Integer Conversion
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{ "fxfr", CF_USE1|CF_CHG2 }, // Transfer F-P to Integer Register
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{ "fzchkl", CF_USE1|CF_USE2|CF_CHG3 }, // 32-bit Z-Buffer Check
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{ "fzchks", CF_USE1|CF_USE2|CF_CHG3 }, // 16-bit Z-Buffer Check
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{ "introvr", 0 }, // Software Trap on Integer Overflow
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{ "ixfr", CF_USE1|CF_CHG2 }, // Transfer Integer to F-P Register
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{ "ld.c", CF_USE1|CF_CHG2 }, // Load from Control Register
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{ "ld", CF_USE1|CF_CHG2 }, // Load Integer
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{ "ldint", CF_USE1|CF_CHG2 }, // Load Interrupt Vector
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{ "ldio", CF_USE1|CF_CHG2 }, // Load I/O
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{ "lock", 0 }, // Begin Interlocked Sequence
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{ "or", CF_USE1|CF_USE2|CF_CHG3 }, // Logical OR
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{ "orh", CF_USE1|CF_USE2|CF_CHG3 }, // Logical OR High
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{ "pfadd", CF_USE1|CF_USE2|CF_CHG3 }, // Pipelined Floating-Point Add
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{ "pfaddp", CF_USE1|CF_USE2|CF_CHG3 }, // Pipelined Add with Pixel Merge
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{ "pfaddz", CF_USE1|CF_USE2|CF_CHG3 }, // Pipelined Add with Z Merge
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{ "pfamov", CF_USE1|CF_CHG2 }, // Pipelined Floating-Point Adder Move
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{ "pfeq", CF_USE1|CF_USE2|CF_CHG3 }, // Pipelined Floating Point Equal Compare
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{ "pfgt", CF_USE1|CF_USE2|CF_CHG3 }, // Pipelined Floating Point Greater-Than Compare
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{ "pfiadd", CF_USE1|CF_USE2|CF_CHG3 }, // Pipelined Long Integer Add
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{ "pfisub", CF_USE1|CF_USE2|CF_CHG3 }, // Pipelined Long Integer Subtract
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{ "pfix", CF_USE1|CF_CHG2 }, // Pipelined Floating-Point to Integer Conversion
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{ "pfld", CF_USE1|CF_CHG2 }, // Pipelined Floating-Point Load
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{ "pfle", CF_USE1|CF_USE2|CF_CHG3 }, // Pipelined Floating Point Less-Than or Equal Compare
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{ "pfmul", CF_USE1|CF_USE2|CF_CHG3 }, // Pipelined Floating-Point Multiply
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{ "pfmul3.dd", CF_USE1|CF_USE2|CF_CHG3 }, // Three-Stage Pipelined Floating-Point Multiply
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{ "pform", CF_USE1|CF_CHG2 }, // Pipelined Or with MERGE register
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{ "pfsub", CF_USE1|CF_USE2|CF_CHG3 }, // Pipelined Floating-Point Subtract
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{ "pftrunc", CF_USE1|CF_CHG2 }, // Pipelined Floating-Point to Integer Conversion
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{ "pfzchkl", CF_USE1|CF_USE2|CF_CHG3 }, // Pipelined 32-bit Z-Buffer Check
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{ "pfzchks", CF_USE1|CF_USE2|CF_CHG3 }, // Pipelined 16-bit Z-Buffer Check
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{ "pst.d", CF_CHG1|CF_USE2 }, // Pixel Store
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{ "scyc", CF_USE1 }, // Special Cycles
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{ "shl", CF_USE1|CF_USE2|CF_CHG3 }, // Shift Left
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{ "shr", CF_USE1|CF_USE2|CF_CHG3 }, // Shift Right
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{ "shra", CF_USE1|CF_USE2|CF_CHG3 }, // Shift Right Arithmetic
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{ "shrd", CF_USE1|CF_USE2|CF_CHG3 }, // Shift Right Double
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{ "st.c", CF_USE1|CF_CHG2 }, // Store to Control Register
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{ "st", CF_USE1|CF_CHG2 }, // Store Integer
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{ "stio", CF_USE1|CF_USE2 }, // Store I/O
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{ "subs", CF_USE1|CF_USE2|CF_CHG3 }, // Subtract Signed: o3 <- o1 - o2
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{ "subu", CF_USE1|CF_USE2|CF_CHG3 }, // Subtract Unsigned: o3 <- o1 - o2
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{ "trap", CF_USE1|CF_USE2|CF_CHG3 }, // Software Trap
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{ "unlock", 0 }, // End Interlocked Sequence
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{ "xor", CF_USE1|CF_USE2|CF_CHG3 }, // Logical Exclusive OR: o3 <- o1 ^ o2
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{ "xorh", CF_USE1|CF_USE2|CF_CHG3 }, // Logical Exclusive OR High: o3 <- (o1<<16) ^ o2
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//
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// iNTEL 860 XP Pipelined F-P instructions
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//
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{ "r2p1", CF_USE1|CF_USE2|CF_CHG3 }, // PFAM: M(KR,o2) A(o1, Mres) T:No K:No
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{ "r2pt", CF_USE1|CF_USE2|CF_CHG3 }, // PFAM: M(KR,o2) A(T, Mres) T:No K:Yes
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{ "r2ap1", CF_USE1|CF_USE2|CF_CHG3 }, // PFAM: M(KR,o2) A(o1, Ares) T:Yes K:No
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{ "r2apt", CF_USE1|CF_USE2|CF_CHG3 }, // PFAM: M(KR,o2) A(T, Ares) T:Yes K:Yes
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{ "i2p1", CF_USE1|CF_USE2|CF_CHG3 }, // PFAM: M(KI,o2) A(o1, Mres) T:No K:No
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{ "i2pt", CF_USE1|CF_USE2|CF_CHG3 }, // PFAM: M(KI,o2) A(T, Mres) T:No K:Yes
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{ "i2ap1", CF_USE1|CF_USE2|CF_CHG3 }, // PFAM: M(KI,o2) A(o1, Ares) T:Yes K:No
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{ "i2apt", CF_USE1|CF_USE2|CF_CHG3 }, // PFAM: M(KI,o2) A(T, Ares) T:Yes K:Yes
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{ "rat1p2", CF_USE1|CF_USE2|CF_CHG3 }, // PFAM: M(KR,Ares) A(o1, o2) T:Yes K:No
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{ "m12apm", CF_USE1|CF_USE2|CF_CHG3 }, // PFAM: M(o1,o2) A(Ares,Mres) T:No K:No
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{ "ra1p2", CF_USE1|CF_USE2|CF_CHG3 }, // PFAM: M(KR,Ares) A(o1, o2) T:No K:No
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{ "m12ttpa", CF_USE1|CF_USE2|CF_CHG3 }, // PFAM: M(o1,o2) A(T, Ares) T:Yes K:No
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{ "iat1p2", CF_USE1|CF_USE2|CF_CHG3 }, // PFAM: M(KI,Ares) A(o1, o2) T:Yes K:No
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{ "m12tpm", CF_USE1|CF_USE2|CF_CHG3 }, // PFAM: M(o1,o2) A(T, Mres) T:No K:No
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{ "ia1p2", CF_USE1|CF_USE2|CF_CHG3 }, // PFAM: M(KI,Ares) A(o1, o2) T:No K:No
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{ "m12tpa", CF_USE1|CF_USE2|CF_CHG3 }, // PFAM: M(o1,o2) A(T, Ares) T:No K:No
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{ "r2s1", CF_USE1|CF_USE2|CF_CHG3 }, // PFSM: M(KR,o2) A(o1, Mres) T:No K:No
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{ "r2st", CF_USE1|CF_USE2|CF_CHG3 }, // PFSM: M(KR,o2) A(T, Mres) T:No K:Yes
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{ "r2as1", CF_USE1|CF_USE2|CF_CHG3 }, // PFSM: M(KR,o2) A(o1, Ares) T:Yes K:No
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{ "r2ast", CF_USE1|CF_USE2|CF_CHG3 }, // PFSM: M(KR,o2) A(T, Ares) T:Yes K:Yes
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{ "i2s1", CF_USE1|CF_USE2|CF_CHG3 }, // PFSM: M(KI,o2) A(o1, Mres) T:No K:No
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{ "i2st", CF_USE1|CF_USE2|CF_CHG3 }, // PFSM: M(KI,o2) A(T, Mres) T:No K:Yes
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{ "i2as1", CF_USE1|CF_USE2|CF_CHG3 }, // PFSM: M(KI,o2) A(o1, Ares) T:Yes K:No
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{ "i2ast", CF_USE1|CF_USE2|CF_CHG3 }, // PFSM: M(KI,o2) A(T, Ares) T:Yes K:Yes
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{ "rat1s2", CF_USE1|CF_USE2|CF_CHG3 }, // PFSM: M(KR,Ares) A(o1, o2) T:Yes K:No
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{ "m12asm", CF_USE1|CF_USE2|CF_CHG3 }, // PFSM: M(o1,o2) A(Ares,Mres) T:No K:No
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{ "ra1s2", CF_USE1|CF_USE2|CF_CHG3 }, // PFSM: M(KR,Ares) A(o1, o2) T:No K:No
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{ "m12ttsa", CF_USE1|CF_USE2|CF_CHG3 }, // PFSM: M(o1,o2) A(T, Ares) T:Yes K:No
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{ "iat1s2", CF_USE1|CF_USE2|CF_CHG3 }, // PFSM: M(KI,Ares) A(o1, o2) T:Yes K:No
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{ "m12tsm", CF_USE1|CF_USE2|CF_CHG3 }, // PFSM: M(o1,o2) A(T, Mres) T:No K:No
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{ "ia1s2", CF_USE1|CF_USE2|CF_CHG3 }, // PFSM: M(KI,Ares) A(o1, o2) T:No K:No
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{ "m12tsa", CF_USE1|CF_USE2|CF_CHG3 }, // PFSM: M(o1,o2) A(T, Ares) T:No K:No
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{ "mr2p1", CF_USE1|CF_USE2|CF_CHG3 }, // PFMAM: M(KR,o2) A(o1, Mres) T:No K:No
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{ "mr2pt", CF_USE1|CF_USE2|CF_CHG3 }, // PFMAM: M(KR,o2) A(T, Mres) T:No K:Yes
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{ "mr2mp1", CF_USE1|CF_USE2|CF_CHG3 }, // PFMAM: M(KR,o2) A(o1, Mres) T:Yes K:No
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{ "mr2mpt", CF_USE1|CF_USE2|CF_CHG3 }, // PFMAM: M(KR,o2) A(T, Mres) T:Yes K:Yes
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{ "mi2p1", CF_USE1|CF_USE2|CF_CHG3 }, // PFMAM: M(KI,o2) A(o1, Mres) T:No K:No
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{ "mi2pt", CF_USE1|CF_USE2|CF_CHG3 }, // PFMAM: M(KI,o2) A(T, Mres) T:No K:Yes
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{ "mi2mp1", CF_USE1|CF_USE2|CF_CHG3 }, // PFMAM: M(KI,o2) A(o1, Mres) T:Yes K:No
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{ "mi2mpt", CF_USE1|CF_USE2|CF_CHG3 }, // PFMAM: M(KI,o2) A(T, Mres) T:Yes K:Yes
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{ "mrmt1p2", CF_USE1|CF_USE2|CF_CHG3 }, // PFMAM: M(KR,Mres) A(o1, o2) T:Yes K:No
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{ "mm12mpm", CF_USE1|CF_USE2|CF_CHG3 }, // PFMAM: M(o1,o2) A(Mres,Mres) T:No K:No
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{ "mrm1p2", CF_USE1|CF_USE2|CF_CHG3 }, // PFMAM: M(KR,Mres) A(o1, o2) T:No K:No
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{ "mm12ttpm", CF_USE1|CF_USE2|CF_CHG3 }, // PFMAM: M(o1,o2) A(T, Mres) T:Yes K:No
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{ "mimt1p2", CF_USE1|CF_USE2|CF_CHG3 }, // PFMAM: M(KI,Mres) A(o1, o2) T:Yes K:No
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{ "mm12tpm", CF_USE1|CF_USE2|CF_CHG3 }, // PFMAM: M(o1,o2) A(T, Mres) T:No K:No
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{ "mim1p2", CF_USE1|CF_USE2|CF_CHG3 }, // PFMAM: M(KI,Mres) A(o1, o2) T:No K:No
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{ "mr2s1", CF_USE1|CF_USE2|CF_CHG3 }, // PFMSM: M(KR,o2) A(o1, Mres) T:No K:No
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{ "mr2st", CF_USE1|CF_USE2|CF_CHG3 }, // PFMSM: M(KR,o2) A(T, Mres) T:No K:Yes
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{ "mr2ms1", CF_USE1|CF_USE2|CF_CHG3 }, // PFMSM: M(KR,o2) A(o1, Mres) T:Yes K:No
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{ "mr2mst", CF_USE1|CF_USE2|CF_CHG3 }, // PFMSM: M(KR,o2) A(T, Mres) T:Yes K:Yes
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{ "mi2s1", CF_USE1|CF_USE2|CF_CHG3 }, // PFMSM: M(KI,o2) A(o1, Mres) T:No K:No
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{ "mi2st", CF_USE1|CF_USE2|CF_CHG3 }, // PFMSM: M(KI,o2) A(T, Mres) T:No K:Yes
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{ "mi2ms1", CF_USE1|CF_USE2|CF_CHG3 }, // PFMSM: M(KI,o2) A(o1, Mres) T:Yes K:No
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{ "mi2mst", CF_USE1|CF_USE2|CF_CHG3 }, // PFMSM: M(KI,o2) A(T, Mres) T:Yes K:Yes
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{ "mrmt1s2", CF_USE1|CF_USE2|CF_CHG3 }, // PFMSM: M(KR,Mres) A(o1, o2) T:Yes K:No
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{ "mm12msm", CF_USE1|CF_USE2|CF_CHG3 }, // PFMSM: M(o1,o2) A(Mres,Mres) T:No K:No
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{ "mrm1s2", CF_USE1|CF_USE2|CF_CHG3 }, // PFMSM: M(KR,Mres) A(o1, o2) T:No K:No
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{ "mm12ttsm", CF_USE1|CF_USE2|CF_CHG3 }, // PFMSM: M(o1,o2) A(T, Mres) T:Yes K:No
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{ "mimt1s2", CF_USE1|CF_USE2|CF_CHG3 }, // PFMSM: M(KI,Mres) A(o1, o2) T:Yes K:No
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{ "mm12tsm", CF_USE1|CF_USE2|CF_CHG3 }, // PFMSM: M(o1,o2) A(T, Mres) T:No K:No
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{ "mim1s2", CF_USE1|CF_USE2|CF_CHG3 }, // PFMSM: M(KI,Mres) A(o1, o2) T:No K:No
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};
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CASSERT(qnumber(Instructions) == I860_last);
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