142 lines
4.0 KiB
C++
142 lines
4.0 KiB
C++
/*
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* Interactive disassembler (IDA).
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* Version 3.05
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* Copyright (c) 1990-95 by Ilfak Guilfanov.
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* ALL RIGHTS RESERVED.
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* FIDO: 2:5020/209
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* E-mail: ig@estar.msk.su
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*
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*/
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#ifndef __I860_HPP
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#define __I860_HPP
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#include "../idaidp.hpp"
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#include "ins.hpp"
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// Intel 860 insn.auxpref bits:
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#define aux_dual 0x1 // is dual
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#define aux_sdbl 0x2 // source double
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#define aux_rdbl 0x4 // result double
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#define _PT_860XR 0x01 // Intel 860 XR
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#define _PT_860XP 0x02 // Intel 860 XP
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#define PT_860XP _PT_860XP
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#define PT_860XR (PT_860XP | _PT_860XR)
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//------------------------------------------------------------------------
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enum i860RegNo
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{
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R_r0, R_r1, R_r2, R_r3, R_r4, R_r5, R_r6, R_r7,
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R_r8, R_r9, R_r10, R_r11, R_r12, R_r13, R_r14, R_r15,
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R_r16, R_r17, R_r18, R_r19, R_r20, R_r21, R_r22, R_r23,
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R_r24, R_r25, R_r26, R_r27, R_r28, R_r29, R_r30, R_r31,
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R_f0, R_f1, R_f2, R_f3, R_f4, R_f5, R_f6, R_f7,
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R_f8, R_f9, R_f10, R_f11, R_f12, R_f13, R_f14, R_f15,
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R_f16, R_f17, R_f18, R_f19, R_f20, R_f21, R_f22, R_f23,
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R_f24, R_f25, R_f26, R_f27, R_f28, R_f29, R_f30, R_f31,
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R_fir,
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R_psr,
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R_dirbase,
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R_db,
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R_fsr,
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R_epsr,
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R_bear,
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R_ccr,
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R_p0,
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R_p1,
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R_p2,
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R_p3,
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R_vcs,R_vds // virtual segment registers
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};
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#define bit0 (1L<<0)
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#define bit1 (1L<<1)
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#define bit2 (1L<<2)
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#define bit3 (1L<<3)
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#define bit4 (1L<<4)
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#define bit5 (1L<<5)
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#define bit6 (1L<<6)
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#define bit7 (1L<<7)
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#define bit8 (1L<<8)
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#define bit9 (1L<<9)
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#define bit10 (1L<<10)
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#define bit11 (1L<<11)
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#define bit12 (1L<<12)
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#define bit13 (1L<<13)
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#define bit14 (1L<<14)
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#define bit15 (1L<<15)
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#define bit16 (1L<<16)
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#define bit17 (1L<<17)
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#define bit18 (1L<<18)
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#define bit19 (1L<<19)
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#define bit20 (1L<<20)
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#define bit21 (1L<<21)
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#define bit22 (1L<<22)
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#define bit23 (1L<<23)
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#define bit24 (1L<<24)
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#define bit25 (1L<<25)
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#define bit26 (1L<<26)
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#define bit27 (1L<<27)
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#define bit28 (1L<<28)
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#define bit29 (1L<<29)
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#define bit30 (1L<<30)
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#define bit31 (1L<<31)
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#define Rbit bit7 // Result is double precision
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#define Sbit bit8 // Source is double precision
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#define Dbit bit9 // Dual Instruction
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#define Pbit bit10 // Pipelining
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void idaapi i860_header(outctx_t &ctx);
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int idaapi i860_ana(insn_t *_insn);
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//------------------------------------------------------------------------
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struct i860_t : public procmod_t
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{
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int pflag = 0;
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inline int is860XP(void) { return (pflag & PT_860XP) != 0; }
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uint32 code = 0;
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inline uint16 op_s1(void) { return int((code>>11)) & 31; }
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inline uint16 op_ds(void) { return int((code>>16)) & 31; }
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inline uint16 op_s2(void) { return int((code>>21)) & 31; }
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inline int isDS(void) { return (code & (Sbit|Rbit)) == Sbit; } // prec .ds
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inline int isSSDD(void) { return (code & Sbit) == (code & Rbit); } // prec .ss .dd
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inline int isSDDD(void) { return (code & Rbit) != 0; } // prec .sd .dd
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virtual ssize_t idaapi on_event(ssize_t msgid, va_list va) override;
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int op_ctl(op_t &x);
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void set_cpu(int procnum);
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void COREunit(insn_t &insn);
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int i860_ana(insn_t *_insn);
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void op_s1ni(op_t &x);
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void op_s2(op_t &x);
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void op_fs1(op_t &x);
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void op_fs2(op_t &x);
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void op_s1s(op_t &x);
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void op_s1u(op_t &x);
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void op_s1s2(op_t &x);
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void op_dest(op_t &x);
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void op_fdest(op_t &x);
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char dsize_28_0(void) const;
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char dsize_1_2(void) const;
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char dsize_10_9(void) const;
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void op_stoff(op_t &x);
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void op_bteoff(insn_t &insn, op_t &x);
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void op_lbroff(insn_t &insn, op_t &x) const;
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void op_ainc(op_t &x);
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void FPunit(insn_t &insn);
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int i860_emu(const insn_t &insn) const;
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bool handle_operand(const insn_t &insn, const op_t &x, bool isload) const;
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void i860_segstart(outctx_t &ctx, segment_t *Sarea) const;
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void i860_footer(outctx_t &ctx) const;
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};
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#endif
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