128 lines
8.2 KiB
C++
128 lines
8.2 KiB
C++
/*
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* Interactive disassembler (IDA).
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* Copyright (c) 1990-2000 by Ilfak Guilfanov.
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* ALL RIGHTS RESERVED.
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* E-mail: ig@datarescue.com
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*
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*
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*/
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#include "h8500.hpp"
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const instruc_t Instructions[] =
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{
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{ "", 0 }, // Unknown Operation
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// Data transfer
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{ "mov:g", CF_USE1|CF_CHG2 }, // B/W Move data
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{ "mov:e", CF_USE1|CF_CHG2 }, // B Move data
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{ "mov:i", CF_USE1|CF_CHG2 }, // W Move data
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{ "mov:f", CF_USE1|CF_CHG2 }, // B/W Move data
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{ "mov:l", CF_USE1|CF_CHG2 }, // B/W Move data
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{ "mov:s", CF_USE1|CF_CHG2 }, // B/W Move data
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{ "ldm", CF_USE1|CF_CHG2 }, // W Pop data from the stack to one or more registers
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{ "stm", CF_USE1|CF_CHG2 }, // W Push data from one or more registers onto the stack
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{ "xch", CF_USE1|CF_USE2|CF_CHG1|CF_CHG2 }, // W Exchange data between two general registers
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{ "swap", CF_USE1|CF_CHG1 }, // B Exchange the upper and lower bytes in a general register
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{ "movtpe", CF_USE1|CF_CHG2 }, // B Transfer data from a general register to memory
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{ "movfpe", CF_USE1|CF_CHG2 }, // B Transfer data from memory to a general register
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// Arithmetic operations
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{ "add:g", CF_USE1|CF_USE2|CF_CHG2 }, // B/W Addition
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{ "add:q", CF_USE1|CF_USE2|CF_CHG2 }, // B/W Addition
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{ "sub", CF_USE1|CF_USE2|CF_CHG2 }, // B/W Subtraction
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{ "adds", CF_USE1|CF_USE2|CF_CHG2 }, // B/W Addition
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{ "subs", CF_USE1|CF_USE2|CF_CHG2 }, // B/W Subtraction
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{ "addx", CF_USE1|CF_USE2|CF_CHG2 }, // B/W Addition with carry
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{ "subx", CF_USE1|CF_USE2|CF_CHG2 }, // B/W Subtraction with borrow
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{ "dadd", CF_USE1|CF_USE2|CF_CHG2 }, // B Decimal addition
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{ "dsub", CF_USE1|CF_USE2|CF_CHG2 }, // B Decimal subtraction
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{ "mulxu", CF_USE1|CF_USE2|CF_CHG2 }, // B/W Unsigned multiplication
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{ "divxu", CF_USE1|CF_USE2|CF_CHG2 }, // B/W Unsigned division
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{ "cmp:g", CF_USE1|CF_USE2 }, // B/W Compare data
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{ "cmp:e", CF_USE1|CF_USE2 }, // B Compare data
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{ "cmp:i", CF_USE1|CF_USE2 }, // W Compare data
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{ "exts", CF_USE1|CF_CHG1 }, // B Convert byte to word by extending the sign bit
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{ "extu", CF_USE1|CF_CHG1 }, // B Convert byte to word data by padding with zero bits
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{ "tst", CF_USE1 }, // B/W Compare with 0
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{ "neg", CF_USE1|CF_CHG1 }, // B/W Negate
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{ "clr", CF_CHG1 }, // B/W Make zero
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{ "tas", CF_USE1|CF_CHG1 }, // B Test and set
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// Logic Operations
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{ "and", CF_USE1|CF_USE2|CF_CHG2 }, // B/W Logical AND
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{ "or", CF_USE1|CF_USE2|CF_CHG2 }, // B/W Logical OR
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{ "xor", CF_USE1|CF_USE2|CF_CHG2 }, // B/W Exclusive OR
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{ "not", CF_USE1|CF_CHG1 }, // B/W Bitwise NOT
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// Shift Operations
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{ "shal", CF_USE1|CF_CHG1 }, // B/W Arithmetic shift left
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{ "shar", CF_USE1|CF_CHG1 }, // B/W Arithmetic shift right
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{ "shll", CF_USE1|CF_CHG1 }, // B/W Logical shift left
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{ "shlr", CF_USE1|CF_CHG1 }, // B/W Logical shift right
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{ "rotl", CF_USE1|CF_CHG1 }, // B/W Rotate left
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{ "rotr", CF_USE1|CF_CHG1 }, // B/W Rotate right
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{ "rotxl", CF_USE1|CF_CHG1 }, // B/W Rotate through carry left
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{ "rotxr", CF_USE1|CF_CHG1 }, // B/W Rotate through carry right
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// Bit Manipulations
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{ "bset", CF_USE1|CF_USE2|CF_CHG2 }, // B/W Test bit and set
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{ "bclr", CF_USE1|CF_USE2|CF_CHG2 }, // B/W Test bit and clear
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{ "bnot", CF_USE1|CF_USE2|CF_CHG2 }, // B/W Test bit and invert
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{ "btst", CF_USE1|CF_USE2 }, // B/W Test bit
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// Branching Instructions
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{ "bra", CF_USE1|CF_STOP }, // Branch Always
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{ "brn", CF_USE1 }, // Branch Never
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{ "bhi", CF_USE1 }, // Branch if High (C|Z = 0)
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{ "bls", CF_USE1 }, // Branch if Low or Same (C|Z = 1)
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{ "bcc", CF_USE1 }, // Branch if Carry Clear (C = 0)
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{ "bcs", CF_USE1 }, // Branch if Carry Set (C = 1)
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{ "bne", CF_USE1 }, // Branch if Not Equal (Z = 0)
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{ "beq", CF_USE1 }, // Branch if Equal (Z = 1)
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{ "bvc", CF_USE1 }, // Branch if Overflow Clear (V = 0)
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{ "bvs", CF_USE1 }, // Branch if Overflow Set (V = 1)
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{ "bpl", CF_USE1 }, // Branch if Plus (N = 0)
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{ "bmi", CF_USE1 }, // Branch if Minus (N = 1)
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{ "bge", CF_USE1 }, // Branch if Greater or Equal (N^V = 0)
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{ "blt", CF_USE1 }, // Branch if Less Than (N^V = 1)
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{ "bgt", CF_USE1 }, // Branch if Greater Than (Z|(N^V) = 0)
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{ "ble", CF_USE1 }, // Branch if Less or Equal (Z|(N^V) = 1)
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{ "jmp", CF_USE1|CF_STOP }, // Branch unconditionally (same page)
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{ "pjmp", CF_USE1|CF_STOP }, // Branch unconditionally (specified page)
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{ "bsr", CF_USE1|CF_CALL }, // Branch to subroutine (same page)
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{ "jsr", CF_USE1|CF_CALL }, // Branch to subroutine (same page)
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{ "pjsr", CF_USE1|CF_CALL }, // Branch to subroutine (specified page)
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{ "rts", CF_STOP }, // Return from subroutine (same page)
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{ "prts", CF_STOP }, // Return from subroutine (different page)
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{ "rtd", CF_USE1|CF_STOP }, // Return from subroutine (same page) and adjust SP
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{ "prtd", CF_USE1|CF_STOP }, // Return from subroutine (different page) and adjust SP
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{ "scb", CF_USE1|CF_USE2 }, // Control loop
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// System Control Instructions
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{ "trapa", CF_USE1 }, // Generate trap exception
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{ "trap/vs", 0 }, // Generate trap exception if the V bit is set
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{ "rte", CF_STOP }, // Return from exception-handling routine
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{ "link", CF_USE1|CF_USE2 }, // Create stack frame
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{ "unlk", 0 }, // Deallocate stack frame
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{ "sleep", 0 }, // Go to power-down state
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{ "ldc", CF_USE1|CF_CHG2 }, // B/W Move to control register
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{ "stc", CF_USE1|CF_CHG2 }, // B/W Move from control register
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{ "andc", CF_USE1|CF_USE2|CF_CHG2 }, // B/W Logically AND control register
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{ "orc", CF_USE1|CF_USE2|CF_CHG2 }, // B/W Logically OR control register
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{ "xorc", CF_USE1|CF_USE2|CF_CHG2 }, // B/W Logically exclusive-OR control register
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{ "nop", 0 }, // No operation
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{ "bpt", 0 }, //
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};
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CASSERT(qnumber(Instructions) == H8500_last);
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