135 lines
9.5 KiB
C++
135 lines
9.5 KiB
C++
/*
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* Interactive disassembler (IDA).
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* Copyright (c) 1990-99 by Ilfak Guilfanov.
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* ALL RIGHTS RESERVED.
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* E-mail: ig@datarescue.com
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*
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*
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*/
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#include "h8.hpp"
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const instruc_t Instructions[] =
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{
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{ "", 0 }, // Unknown Operation
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{ "add", CF_USE1|CF_USE2|CF_CHG2 }, // Add binary
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{ "adds", CF_USE1|CF_USE2|CF_CHG2 }, // Add with sign extension
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{ "addx", CF_USE1|CF_USE2|CF_CHG2 }, // Add with extend carry
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{ "and", CF_USE1|CF_USE2|CF_CHG2 }, // Logical AND
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{ "andc", CF_USE1|CF_USE2|CF_CHG2 }, // Logical AND with control register
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{ "band", CF_USE1|CF_USE2|CF_CHG2 }, // Bit AND
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{ "bra", CF_USE1|CF_STOP|CF_JUMP }, // Branch always
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{ "brn", CF_USE1 }, // Branch never
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{ "bhi", CF_USE1 }, // Branch if higher
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{ "bls", CF_USE1 }, // Branch if lower or same
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{ "bcc", CF_USE1 }, // Branch if carry clear (higher or same)
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{ "bcs", CF_USE1 }, // Branch if carry set (lower)
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{ "bne", CF_USE1 }, // Branch if not equal
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{ "beq", CF_USE1 }, // Branch if equal
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{ "bvc", CF_USE1 }, // Branch if overflow clear
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{ "bvs", CF_USE1 }, // Branch if overflow set
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{ "bpl", CF_USE1 }, // Branch if plus
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{ "bmi", CF_USE1 }, // Branch if minus
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{ "bge", CF_USE1 }, // Branch if greates or equal
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{ "blt", CF_USE1 }, // Branch if less
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{ "bgt", CF_USE1 }, // Branch if greater
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{ "ble", CF_USE1 }, // Branch if less or equal
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{ "bclr", CF_USE1|CF_USE2|CF_CHG2 }, // Bit clear
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{ "biand", CF_USE1|CF_USE2|CF_CHG2 }, // Bit invert AND
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{ "bild", CF_USE1|CF_USE2|CF_CHG2 }, // Bit invert load
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{ "bior", CF_USE1|CF_USE2|CF_CHG2 }, // Bit invert OR
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{ "bist", CF_USE1|CF_USE2|CF_CHG2 }, // Bit invert store
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{ "bixor", CF_USE1|CF_USE2|CF_CHG2 }, // Bit invert XOR
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{ "bld", CF_USE1|CF_USE2 }, // Bit load
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{ "bnot", CF_USE1|CF_USE2|CF_CHG2 }, // Bit NOT
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{ "bor", CF_USE1|CF_USE2|CF_CHG2 }, // Bit OR
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{ "bset", CF_USE1|CF_USE2|CF_CHG2 }, // Bit set
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{ "bsr", CF_USE1|CF_CALL }, // Branch to subroutine
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{ "bst", CF_USE1|CF_USE2|CF_CHG2 }, // Bit store
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{ "btst", CF_USE1|CF_USE2 }, // Bit test
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{ "bxor", CF_USE1|CF_USE2|CF_CHG2 }, // Bit XOR
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{ "clrmac", 0 }, // Clear MAC register
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{ "cmp", CF_USE1|CF_USE2 }, // Compare
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{ "daa", CF_USE1|CF_CHG1 }, // Decimal adjust add
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{ "das", CF_USE1|CF_CHG1 }, // Decimal adjust subtract
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{ "dec", CF_USE1|CF_USE2|CF_CHG2 }, // Decrement
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{ "divxs", CF_USE1|CF_USE2|CF_CHG2 }, // Divide extended as signed
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{ "divxu", CF_USE1|CF_USE2|CF_CHG2 }, // Divide extended as unsigned
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{ "eepmov", 0 }, // Move data to EEPROM
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{ "exts", CF_USE1|CF_USE2|CF_CHG2 }, // Extend as signed
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{ "extu", CF_USE1|CF_USE2|CF_CHG2 }, // Extend as unsigned
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{ "inc", CF_USE1|CF_USE2|CF_CHG2 }, // Increment
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{ "jmp", CF_USE1|CF_STOP|CF_JUMP }, // Jump
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{ "jsr", CF_USE1|CF_CALL }, // Jump to subroutine
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{ "ldc", CF_USE1|CF_CHG2 }, // Load to control register
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{ "ldm", CF_USE1|CF_CHG2 }, // Load to multiple registers
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{ "ldmac", CF_USE1|CF_CHG2 }, // Load to MAC register
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{ "mac", CF_USE1|CF_USE2 }, // Multiply and accumulate
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{ "mov", CF_USE1|CF_CHG2 }, // Move data
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{ "movfpe", CF_USE1|CF_CHG2 }, // Move from peripheral with E clock
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{ "movtpe", CF_USE1|CF_CHG2 }, // Move to peripheral with E clock
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{ "mulxs", CF_USE1|CF_USE2|CF_CHG2 }, // Multiply extend as signed
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{ "mulxu", CF_USE1|CF_USE2|CF_CHG2 }, // Multiply extend as unsigned
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{ "neg", CF_USE1|CF_CHG1 }, // Negate
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{ "nop", 0 }, // No operation
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{ "not", CF_USE1|CF_CHG1 }, // Logical complement
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{ "or", CF_USE1|CF_USE2|CF_CHG2 }, // Logical OR
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{ "orc", CF_USE1|CF_USE2|CF_CHG2 }, // Logical OR with control register
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{ "pop", CF_CHG1 }, // Pop data from stack
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{ "push", CF_USE1 }, // Push data on stack
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{ "rotl", CF_USE1|CF_USE2|CF_CHG2 }, // Rotate left
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{ "rotr", CF_USE1|CF_USE2|CF_CHG2 }, // Rotate right
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{ "rotxl", CF_USE1|CF_USE2|CF_CHG2 }, // Rotate with extend carry left
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{ "rotxr", CF_USE1|CF_USE2|CF_CHG2 }, // Rotate with extend carry right
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{ "rte", CF_STOP }, // Return from exception
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{ "rts", CF_STOP }, // Return from subroutine
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{ "shal", CF_USE1|CF_USE2|CF_CHG2 }, // Shift arithmetic left
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{ "shar", CF_USE1|CF_USE2|CF_CHG2 }, // Shift arithmetic right
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{ "shll", CF_USE1|CF_USE2|CF_CHG2 }, // Shift logical left
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{ "shlr", CF_USE1|CF_USE2|CF_CHG2 }, // Shift logical right
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{ "sleep", 0 }, // Power down mode
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{ "stc", CF_USE1|CF_CHG2 }, // Store from control register
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{ "stm", CF_USE1|CF_CHG2 }, // Store from multiple registers
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{ "stmac", CF_USE1|CF_CHG2 }, // Store from MAC register
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{ "sub", CF_USE1|CF_USE2|CF_CHG2 }, // Subtract binary
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{ "subs", CF_USE1|CF_USE2|CF_CHG2 }, // Subtract with sign extension
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{ "subx", CF_USE1|CF_USE2|CF_CHG2 }, // Subtract with extend carry
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{ "tas", CF_USE1|CF_CHG1 }, // Test and set
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{ "trapa", CF_USE1|CF_CALL }, // Trap always
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{ "xor", CF_USE1|CF_USE2|CF_CHG2 }, // Logical XOR
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{ "xorc", CF_USE1|CF_USE2|CF_CHG2 }, // Logical XOR with control register
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// H8SX
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{ "rte/l", CF_STOP|CF_USE1|CF_CHG1 }, // Returns from an exception,
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// restoring data to multiple general registers
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{ "rts/l", CF_STOP|CF_USE1|CF_CHG1 }, // Returns from a subroutine,
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// restoring data to multiple general registers
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{ "movmd", 0 }, // Transfers a data block
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{ "movsd", CF_USE1 }, // Transfers a data block with zero detection
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{ "bra/s", CF_USE1|CF_STOP }, // Branch always after the next instruction (delay slot)
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{ "mova/b", CF_USE1|CF_CHG2 }, // MOVe effective Address/B
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{ "mova/w", CF_USE1|CF_CHG2 }, // MOVe effective Address/W
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{ "mova/l", CF_USE1|CF_CHG2 }, // MOVe effective Address/L
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{ "bset/ne", CF_USE1|CF_USE2|CF_CHG2 }, // Bit SET if Not Equal
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{ "bset/eq", CF_USE1|CF_USE2|CF_CHG2 }, // Bit SET if EQual
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{ "bclr/ne", CF_USE1|CF_USE2|CF_CHG2 }, // Bit CLeaR if Not Equal
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{ "bclr/eq", CF_USE1|CF_USE2|CF_CHG2 }, // Bit CLear if EQual
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{ "bstz", CF_USE1|CF_USE2|CF_CHG2 }, // Bit STore Zero flag
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{ "bistz", CF_USE1|CF_USE2|CF_CHG2 }, // Bit Invert STore Zero flag
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{ "bfld", CF_USE1|CF_USE2|CF_USE3|CF_CHG3 }, // Bit Field LoaD
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{ "bfst", CF_USE1|CF_USE2|CF_USE3|CF_CHG3 }, // Bit Field STore
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{ "muls", CF_USE1|CF_USE2|CF_CHG2 }, // MULtiply as Signed
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{ "divs", CF_USE1|CF_USE2|CF_CHG2 }, // DIVide as Signed
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{ "mulu", CF_USE1|CF_USE2|CF_CHG2 }, // MULtiply as Unsigned
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{ "divu", CF_USE1|CF_USE2|CF_CHG2 }, // DIVide as Unsigned
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{ "muls/u", CF_USE1|CF_USE2|CF_CHG2 }, // MULtiply as Signed
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{ "mulu/u", CF_USE1|CF_USE2|CF_CHG2 }, // MULtiply as Unsigned
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{ "bra/bc", CF_USE1|CF_USE2|CF_USE3|CF_STOP }, // BRAnch if Bit Cleared
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{ "bra/bs", CF_USE1|CF_USE2|CF_USE3|CF_STOP }, // BRAnch if Bit Set
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{ "bsr/bc", CF_USE1|CF_USE2|CF_USE3|CF_CALL }, // Branch to SubRoutine if Bit Cleared
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{ "bsr/bs", CF_USE1|CF_USE2|CF_USE3|CF_CALL }, // Branch to SubRoutine if Bit Set
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};
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CASSERT(qnumber(Instructions) == H8_last);
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