145 lines
11 KiB
C++
145 lines
11 KiB
C++
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#include "dsp56k.hpp"
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const instruc_t Instructions[] =
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{
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{ "", 0 }, // Unknown Operation
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{ "abs", CF_USE1|CF_CHG1 }, // Absolute Value
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{ "adc", CF_USE1|CF_USE2|CF_CHG2 }, // Add Long with Carry
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{ "add", CF_USE1|CF_USE2|CF_CHG2 }, // Addition
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{ "addl", CF_USE1|CF_USE2|CF_CHG2 }, // Shift Left and Add
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{ "addr", CF_USE1|CF_USE2|CF_CHG2 }, // Shift Right and Add
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{ "and", CF_USE1|CF_USE2|CF_CHG2 }, // Logical AND
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{ "andi", CF_USE1|CF_USE2|CF_CHG2 }, // AND Immediate to Control Register
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{ "asl", CF_USE1|CF_CHG1 }, // Arithmetic Shift Left
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{ "asl4", CF_USE1|CF_CHG1 }, // Arithmetic Shift Left
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{ "asr", CF_USE1|CF_CHG1 }, // Arithmetic Shift Right
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{ "asr4", CF_USE1|CF_CHG1 }, // Arithmetic Shift Right
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{ "asr16", CF_USE1|CF_CHG1 }, // Arithmetic Shift Right
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{ "bfchg", CF_USE1|CF_USE2|CF_CHG2 }, // Bit Test and Change
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{ "bfclr", CF_USE1|CF_USE2|CF_CHG2 }, // Bit Test and Clear
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{ "bfset", CF_USE1|CF_USE2|CF_CHG2 }, // Bit Test and Set
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{ "bftsth", CF_USE1|CF_USE2|CF_CHG2 }, // Test Bit Field High
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{ "bftstl", CF_USE1|CF_USE2|CF_CHG2 }, // Test Bit Field Low
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{ "b", CF_USE1|CF_JUMP }, // Branch Conditionally
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{ "bchg", CF_USE1|CF_USE2|CF_CHG2 }, // Bit Test and Change
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{ "bclr", CF_USE1|CF_USE2|CF_CHG2 }, // Bit Test and Clear
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{ "bra", CF_USE1|CF_STOP|CF_JUMP }, // Branch Always
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{ "brclr", CF_USE1|CF_USE2|CF_USE3|CF_JUMP }, // Branch if Bit Clear
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{ "brk", CF_USE1 }, // Exit Current DO Loop Conditionally
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{ "brset", CF_USE1|CF_USE2|CF_USE3|CF_JUMP }, // Branch if Bit Set
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{ "bs", CF_USE1|CF_CALL }, // Branch to Subroutine Conditionally
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{ "bsclr", CF_USE1|CF_USE2|CF_USE3|CF_CALL }, // Branch to Subroutine if Bit Clear
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{ "bset", CF_USE1|CF_USE2|CF_CHG2 }, // Bit Test and Set
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{ "bsr", CF_USE1|CF_CALL }, // Branch to Subroutine
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{ "bsset", CF_USE1|CF_USE2|CF_USE3|CF_CALL }, // Branch to Subroutine if Bit Set
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{ "btst", CF_USE1|CF_USE2|CF_CHG2 }, // Bit Test on Memory and Registers
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{ "chkaau", 0 }, // Check address ALU result
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{ "clb", CF_USE1|CF_CHG2 }, // Count Leading Bits
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{ "clr", CF_USE1|CF_CHG1 }, // Clear an Operand
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{ "clr24", CF_USE1|CF_CHG1 }, // Clear 24 MS-bits of Accumulator
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{ "cmp", CF_USE1|CF_USE2 }, // Compare
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{ "cmpm", CF_USE1|CF_USE2 }, // Compare Magnitude
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{ "cmpu", CF_USE1|CF_USE2 }, // Compare Unsigned
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{ "debug", 0 }, // Enter Debug Mode
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{ "debug", 0 }, // Enter Debug Mode Conditionally
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{ "dec", CF_USE1|CF_CHG1 }, // Decrement by One
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{ "dec24", CF_USE1|CF_CHG1 }, // Decrement 24 MS-bit of Accumulator
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{ "div", CF_USE1|CF_USE2|CF_CHG2 }, // Divide Iteration
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{ "dmac", CF_USE1|CF_USE2|CF_USE3|CF_CHG3 }, // Double-Precision Multiply-Accumulate With Right Shift
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{ "do", CF_USE1|CF_USE2|CF_JUMP }, // Start Hardware Loop
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{ "do forever,", CF_USE1|CF_JUMP }, // Start Infinite Loop
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{ "dor", CF_USE1|CF_USE2|CF_JUMP }, // Start PC-Relative Hardware Loop
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{ "dor forever,", CF_USE1|CF_JUMP }, // Start PC-Relative Infinite Loop
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{ "enddo", 0 }, // Exit from Hardware Loop
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{ "eor", CF_USE1|CF_USE2|CF_CHG2 }, // Logical Exclusive OR
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{ "extract", CF_USE1|CF_USE2|CF_CHG3 }, // Extract Bit Field
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{ "extractu", CF_USE1|CF_USE2|CF_CHG3 }, // Extract Unsigned Bit Field
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{ "ext", CF_USE1|CF_CHG1 }, // Sign Extend Accumulator
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{ "illegal", 0 }, // Illegal Instruction
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{ "imac", CF_USE1|CF_USE2|CF_USE3|CF_CHG3 }, // Integer Multiply-Accumulate
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{ "impy", CF_USE1|CF_USE2|CF_USE3|CF_CHG3 }, // Integer Multiply
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{ "inc", CF_USE1|CF_CHG1 }, // Increment by One
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{ "inc24", CF_USE1|CF_CHG1 }, // Increment 24 MS-bit of Accumulator
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{ "insert", CF_USE1|CF_USE2|CF_CHG3 }, // Insert Bit Field
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{ "j", CF_USE1|CF_JUMP }, // Jump Conditionally
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{ "jclr", CF_USE1|CF_USE2|CF_USE3|CF_JUMP }, // Jump if Bit Clear
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{ "jmp", CF_USE1|CF_STOP|CF_JUMP }, // Jump
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{ "js", CF_USE1|CF_CALL }, // Jump to Subroutine Conditionally
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{ "jsclr", CF_USE1|CF_USE2|CF_USE3|CF_CALL }, // Jump to Subroutine if Bit Clear
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{ "jset", CF_USE1|CF_USE2|CF_USE3|CF_JUMP }, // Jump if Bit Set
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{ "jsr", CF_USE1|CF_CALL }, // Jump to Subroutine
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{ "jsset", CF_USE1|CF_USE2|CF_USE3|CF_CALL }, // Jump to Subroutine if Bit Set
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{ "lra", CF_USE1|CF_CHG2 }, // Load PC-Reliative Address
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{ "lsl", CF_USE1|CF_CHG1 }, // Logical Shift Left
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{ "lsr", CF_USE1|CF_CHG1 }, // Logical Shift Right
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{ "lua", CF_USE1|CF_CHG2 }, // Load Updated Address
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{ "lea", CF_USE1|CF_CHG2 }, // Load Updated Address
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{ "mac", CF_USE1|CF_USE2|CF_USE3|CF_CHG3 }, // Signed Multiply-Accumulate
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{ "maci", CF_USE1|CF_USE2|CF_USE3|CF_CHG3 }, // Signed Multiply-Accumulate With Immediate Operand
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{ "mac", CF_USE1|CF_USE2|CF_USE3|CF_CHG3 }, // Mixed Multiply-Accumulate
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{ "macr", CF_USE1|CF_USE2|CF_USE3|CF_CHG3 }, // Signed Multiply-Accumulate and Round
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{ "macri", CF_USE1|CF_USE2|CF_USE3|CF_CHG3 }, // Signed Multiply-Accumulate and Round With Immediate Operand
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{ "max", CF_USE1|CF_USE2|CF_CHG2 }, // Transfer by Signed Value
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{ "maxm", CF_USE1|CF_USE2|CF_CHG2 }, // Transfer by Magnitude
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{ "merge", CF_USE1|CF_USE2|CF_CHG2 }, // Merge Two Half Words
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{ "move", CF_USE1|CF_CHG2 }, // Move Data Register
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{ "movec", CF_USE1|CF_CHG2 }, // Move Control Register
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{ "movei", CF_USE1|CF_CHG2 }, // Move Immediate Short
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{ "movem", CF_USE1|CF_CHG2 }, // Move Program Memory
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{ "movep", CF_USE1|CF_CHG2 }, // Move Peripheral Data
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{ "moves", CF_USE1|CF_CHG2 }, // Move Absolute Short
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{ "mpy", CF_USE1|CF_USE2|CF_USE3|CF_CHG3 }, // Signed Multiply
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{ "mpyi", CF_USE1|CF_USE2|CF_USE3|CF_CHG3 }, // Signed Multiply With Immediate Operand
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{ "mpy", CF_USE1|CF_USE2|CF_USE3|CF_CHG3 }, // Mixed Multiply
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{ "mpyr", CF_USE1|CF_USE2|CF_USE3|CF_CHG3 }, // Signed Multiply and Round
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{ "mpyri", CF_USE1|CF_USE2|CF_USE3|CF_CHG3 }, // Signed Multiply and Round With Immediate Operand
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{ "neg", CF_USE1|CF_CHG1 }, // Negate Accumulator
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{ "negc", CF_USE1|CF_CHG1 }, // Negate Accumulator
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{ "nop", 0 }, // No Operation
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{ "norm", CF_USE1|CF_USE2|CF_CHG2 }, // Norm Accumulator Iteration
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{ "normf", CF_USE1|CF_USE2|CF_CHG2 }, // Fast Accumulator Normalization
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{ "not", CF_USE1|CF_CHG1 }, // Logical Complement
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{ "or", CF_USE1|CF_USE2|CF_CHG2 }, // Logical Inclusive OR
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{ "ori", CF_USE1|CF_USE2|CF_CHG2 }, // OR Immediate to Control Register
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{ "pflush", 0 }, // Program Cache Flush
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{ "pflushun", 0 }, // Program Cache Flush Unlocked Sectors
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{ "pfree", 0 }, // Program Cache Global Unlock
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{ "plock", 0 }, // Lock Instruction Cache Sector
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{ "plockr", 0 }, // Lock Instruction Cache Relative Sector
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{ "punlock", 0 }, // Unlock Instruction Cache Sector
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{ "punlockr", 0 }, // Unlock Instruction Cache Relative Sector
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{ "rep", CF_USE1 }, // Repeat Next Instruction
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{ "rep", CF_USE1 }, // Repeat Next Instruction
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{ "reset", 0 }, // Reset On-Chip Peripheral Devices
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{ "rnd", CF_USE1|CF_CHG1 }, // Round
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{ "rol", CF_USE1|CF_CHG1 }, // Rotate Left
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{ "ror", CF_USE1|CF_CHG1 }, // Rotate Right
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{ "rti", CF_STOP }, // Return from Interrupt
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{ "rts", CF_STOP }, // Return from Subroutine
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{ "sbc", CF_USE1|CF_USE2|CF_CHG2 }, // Subtract Long with Carry
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{ "stop", CF_STOP }, // Stop Processing (Low-Power Standby)
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{ "sub", CF_USE1|CF_USE2|CF_CHG2 }, // Subtract
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{ "subl", CF_USE1|CF_USE2|CF_CHG2 }, // Shift Left and Subtract
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{ "subr", CF_USE1|CF_USE2|CF_CHG2 }, // Shift Right and Subtract
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{ "swap", CF_USE1|CF_CHG1 }, // Swap Accumulator Words
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{ "t", CF_USE1|CF_USE2 }, // Transfer Conditionally
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{ "tfr", CF_USE1|CF_USE2 }, // Transfer Data ALU Register
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{ "tfr2", CF_USE1|CF_USE2|CF_CHG2 }, // Transfer Data ALU Register
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{ "tfr3", CF_USE1|CF_USE2|CF_CHG2 }, // Transfer Data ALU Register
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{ "trap", 0 }, // Software Interrupt
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{ "trap", 0 }, // Software Interrupt Conditionally
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{ "tst", CF_USE1 }, // Test an Operand
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{ "tst2", CF_USE1 }, // Test an Operand
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{ "vsl", CF_USE1|CF_USE2|CF_CHG3 }, // Viterbi Shift Left
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{ "wait", 0 }, // Wait for Interrupt or DMA Request (Low-Power Standby)
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{ "zero", 0 }, // Zero Extend Accumulator
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{ "swi", 0 }, // Software Interrupt
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{ "pmov", 0 }, // Pseudo insn
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};
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CASSERT(qnumber(Instructions) == DSP56_last);
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