362 lines
27 KiB
C++
362 lines
27 KiB
C++
/*
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* Interactive disassembler (IDA).
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* Copyright (c) 1990-98 by Ilfak Guilfanov.
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* ALL RIGHTS RESERVED.
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* E-mail: ig@estar.msk.su, ig@datarescue.com
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* FIDO: 2:5020/209
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*
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*/
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#include "arc.hpp"
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instruc_t Instructions[] =
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{
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{ "", 0 }, // Unknown Operation
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{ "ld", CF_CHG1|CF_USE2 }, // Load
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{ "lr", CF_CHG1|CF_USE2 }, // Load from auxiliary register
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{ "st", CF_USE1|CF_CHG2 }, // Store
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{ "sr", CF_USE1|CF_USE2|CF_CHG2 }, // Store to auxiliary register
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{ "flag", CF_USE1 }, // Set flags
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{ "asr", CF_CHG1|CF_USE2|CF_USE3 }, // Arithmetic shift right
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{ "lsr", CF_CHG1|CF_USE2|CF_USE3 }, // Logical shift right
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{ "sexb", CF_CHG1|CF_USE2 }, // Sign extend byte
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{ "sexw", CF_CHG1|CF_USE2 }, // Sign extend word
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{ "extb", CF_CHG1|CF_USE2 }, // Zero extend byte
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{ "extw", CF_CHG1|CF_USE2 }, // Zero extend word
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{ "ror", CF_CHG1|CF_USE2|CF_USE3 }, // Rotate right
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{ "rrc", CF_CHG1|CF_USE2 }, // Rotate right through carry
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{ "b", CF_USE1|CF_JUMP }, // Branch
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{ "bl", CF_USE1|CF_CALL }, // Branch and link
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{ "lp", CF_USE1 }, // Zero-overhead loop setup
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{ "j", CF_USE1|CF_JUMP }, // Jump
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{ "jl", CF_USE1|CF_CALL }, // Jump and link
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{ "add", CF_CHG1|CF_USE2|CF_USE3 }, // Add
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{ "adc", CF_CHG1|CF_USE2|CF_USE3 }, // Add with carry
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{ "sub", CF_CHG1|CF_USE2|CF_USE3 }, // Subtract
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{ "sbc", CF_CHG1|CF_USE2|CF_USE3 }, // Subtract with carry
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{ "and", CF_CHG1|CF_USE2|CF_USE3 }, // Logical bitwise AND
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{ "or", CF_CHG1|CF_USE2|CF_USE3 }, // Logical bitwise OR
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{ "bic", CF_CHG1|CF_USE2|CF_USE3 }, // Logical bitwise AND with invert
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{ "xor", CF_CHG1|CF_USE2|CF_USE3 }, // Logical bitwise exclusive-OR
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{ "mov", CF_CHG1|CF_USE2 }, // Move
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{ "nop", 0 }, // No operation
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{ "lsl", CF_CHG1|CF_USE2|CF_USE3 }, // Logical shift left
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{ "rlc", CF_CHG1|CF_USE2 }, // Rotate left through carry
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{ "brk", 0 }, // Breakpoint
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{ "sleep", 0 }, // Sleep until interrupt or restart
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{ "swi", 0 }, // Software interrupt
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{ "asl", CF_CHG1|CF_USE2|CF_USE3 }, // Arithmetic shift left
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{ "mul64", CF_CHG1|CF_USE2|CF_USE3 }, // Signed 32x32 multiply
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{ "mulu64", CF_CHG1|CF_USE2|CF_USE3 }, // Unsigned 32x32 multiply
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{ "max", CF_CHG1|CF_USE2|CF_USE3 }, // Maximum of two signed integers
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{ "min", CF_CHG1|CF_USE2|CF_USE3 }, // Minimum of two signed integers
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{ "swap", CF_CHG1|CF_USE2 }, // Exchange upper and lower 16 bits
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{ "norm", CF_CHG1|CF_USE2 }, // Normalize (find-first-bit)
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// ARCompact instructions
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{ "bbit0", CF_USE1|CF_USE2|CF_USE3 }, // Branch if bit cleared to 0
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{ "bbit1", CF_USE1|CF_USE2|CF_USE3 }, // Branch if bit set to 1
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{ "br", CF_USE1|CF_USE2|CF_USE3 }, // Branch on compare
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{ "pop", CF_CHG1 }, // Restore register value from stack
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{ "push", CF_USE1 }, // Store register value on stack
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{ "abs", CF_CHG1|CF_USE2 }, // Absolute value
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{ "add1", CF_CHG1|CF_USE2|CF_USE3 }, // Add with left shift by 1 bit
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{ "add2", CF_CHG1|CF_USE2|CF_USE3 }, // Add with left shift by 2 bits
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{ "add3", CF_CHG1|CF_USE2|CF_USE3 }, // Add with left shift by 3 bits
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{ "bclr", CF_CHG1|CF_USE2|CF_USE3 }, // Clear specified bit (to 0)
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{ "bmsk", CF_CHG1|CF_USE2|CF_USE3 }, // Bit Mask
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{ "bset", CF_CHG1|CF_USE2|CF_USE3 }, // Set specified bit (to 1)
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{ "btst", CF_USE1|CF_USE2 }, // Test value of specified bit
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{ "bxor", CF_CHG1|CF_USE2|CF_USE3 }, // Bit XOR
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{ "cmp", CF_USE1|CF_USE2 }, // Compare
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{ "ex", CF_CHG1|CF_USE2 }, // Atomic Exchange
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{ "mpy", CF_CHG1|CF_USE2|CF_USE3 }, // Signed 32x32 multiply (low)
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{ "mpyh", CF_CHG1|CF_USE2|CF_USE3 }, // Signed 32x32 multiply (high)
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{ "mpyhu", CF_CHG1|CF_USE2|CF_USE3 }, // Unsigned 32x32 multiply (high)
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{ "mpyu", CF_CHG1|CF_USE2|CF_USE3 }, // Unsigned 32x32 multiply (low)
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{ "neg", CF_CHG1|CF_USE2 }, // Negate
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{ "not", CF_CHG1|CF_USE2 }, // Logical bit inversion
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{ "rcmp", CF_USE1|CF_USE2 }, // Reverse Compare
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{ "rsub", CF_CHG1|CF_USE2|CF_USE3 }, // Reverse Subtraction
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{ "rtie", 0 }, // Return from Interrupt/Exception
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{ "sub1", CF_CHG1|CF_USE2|CF_USE3 }, // Subtract with left shift by 1 bit
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{ "sub2", CF_CHG1|CF_USE2|CF_USE3 }, // Subtract with left shift by 2 bits
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{ "sub3", CF_CHG1|CF_USE2|CF_USE3 }, // Subtract with left shift by 3 bits
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{ "sync", 0 }, // Synchronize
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{ "trap", CF_USE1 }, // Raise an exception
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{ "tst", CF_USE1|CF_USE2 }, // Test
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{ "unimp", 0 }, // Unimplemented instruction
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{ "abss", CF_CHG1|CF_USE2 }, // Absolute and saturate
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{ "abssw", CF_CHG1|CF_USE2 }, // Absolute and saturate of word
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{ "adds", CF_CHG1|CF_USE2|CF_USE3 }, // Add and saturate
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{ "addsdw", CF_CHG1|CF_USE2|CF_USE3 }, // Add and saturate dual word
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{ "asls", CF_CHG1|CF_USE2|CF_USE3 }, // Arithmetic shift left and saturate
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{ "asrs", CF_CHG1|CF_USE2|CF_USE3 }, // Arithmetic shift right and saturate
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{ "divaw", CF_CHG1|CF_USE2|CF_USE3 }, // Division assist
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{ "negs", CF_CHG1|CF_USE2 }, // Negate and saturate
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{ "negsw", CF_CHG1|CF_USE2 }, // Negate and saturate of word
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{ "normw", CF_CHG1|CF_USE2 }, // Normalize to 16 bits
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{ "rnd16", CF_CHG1|CF_USE2 }, // Round to word
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{ "sat16", CF_CHG1|CF_USE2 }, // Saturate to word
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{ "subs", CF_CHG1|CF_USE2|CF_USE3 }, // Subtract and saturate
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{ "subsdw", CF_CHG1|CF_USE2|CF_USE3 }, // Subtract and saturate dual word
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{ "muldw", CF_CHG1|CF_USE2|CF_USE3 }, //
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{ "muludw", CF_CHG1|CF_USE2|CF_USE3 }, //
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{ "mulrdw", CF_CHG1|CF_USE2|CF_USE3 }, //
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{ "macdw", CF_CHG1|CF_USE2|CF_USE3 }, //
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{ "macudw", CF_CHG1|CF_USE2|CF_USE3 }, //
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{ "macrdw", CF_CHG1|CF_USE2|CF_USE3 }, //
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{ "msubdw", CF_CHG1|CF_USE2|CF_USE3 }, //
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{ "mululw", CF_CHG1|CF_USE2|CF_USE3 }, //
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{ "mullw", CF_CHG1|CF_USE2|CF_USE3 }, //
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{ "mulflw", CF_CHG1|CF_USE2|CF_USE3 }, //
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{ "maclw", CF_CHG1|CF_USE2|CF_USE3 }, //
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{ "macflw", CF_CHG1|CF_USE2|CF_USE3 }, //
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{ "machulw", CF_CHG1|CF_USE2|CF_USE3 }, //
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{ "machlw", CF_CHG1|CF_USE2|CF_USE3 }, //
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{ "machflw", CF_CHG1|CF_USE2|CF_USE3 }, //
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{ "mulhlw", CF_CHG1|CF_USE2|CF_USE3 }, //
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{ "mulhflw", CF_CHG1|CF_USE2|CF_USE3 }, //
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// Major 6 compact insns
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{ "acm", CF_CHG1|CF_USE2|CF_USE3 },
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{ "addqbs", CF_CHG1|CF_USE2|CF_USE3 },
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{ "avgqb", CF_CHG1|CF_USE2|CF_USE3 },
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{ "clamp", CF_CHG1|CF_USE2|CF_USE3 },
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{ "daddh11", CF_CHG1|CF_USE2|CF_USE3 },
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{ "daddh12", CF_CHG1|CF_USE2|CF_USE3 },
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{ "daddh21", CF_CHG1|CF_USE2|CF_USE3 },
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{ "daddh22", CF_CHG1|CF_USE2|CF_USE3 },
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{ "dexcl1", CF_CHG1|CF_USE2|CF_USE3 },
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{ "dexcl2", CF_CHG1|CF_USE2|CF_USE3 },
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{ "dmulh11", CF_CHG1|CF_USE2|CF_USE3 },
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{ "dmulh12", CF_CHG1|CF_USE2|CF_USE3 },
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{ "dmulh21", CF_CHG1|CF_USE2|CF_USE3 },
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{ "dmulh22", CF_CHG1|CF_USE2|CF_USE3 },
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{ "dsubh11", CF_CHG1|CF_USE2|CF_USE3 },
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{ "dsubh12", CF_CHG1|CF_USE2|CF_USE3 },
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{ "dsubh21", CF_CHG1|CF_USE2|CF_USE3 },
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{ "dsubh22", CF_CHG1|CF_USE2|CF_USE3 },
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{ "drsubh11", CF_CHG1|CF_USE2|CF_USE3 },
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{ "drsubh12", CF_CHG1|CF_USE2|CF_USE3 },
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{ "drsubh21", CF_CHG1|CF_USE2|CF_USE3 },
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{ "drsubh22", CF_CHG1|CF_USE2|CF_USE3 },
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{ "fadd", CF_CHG1|CF_USE2|CF_USE3 },
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{ "fmul", CF_CHG1|CF_USE2|CF_USE3 },
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{ "fsub", CF_CHG1|CF_USE2|CF_USE3 },
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{ "fxtr", CF_CHG1|CF_USE2|CF_USE3 },
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{ "iaddr", CF_CHG1|CF_USE2|CF_USE3 },
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{ "mpyqb", CF_CHG1|CF_USE2|CF_USE3 },
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{ "sfxtr", CF_CHG1|CF_USE2|CF_USE3 },
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{ "pkqb", CF_CHG1|CF_USE2|CF_USE3 },
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{ "upkqb", CF_CHG1|CF_USE2|CF_USE3 },
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{ "xpkqb", CF_CHG1|CF_USE2|CF_USE3 },
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// ARCv2 only major 4 instructions
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{ "mpyw", CF_CHG1|CF_USE2|CF_USE3 }, // Signed 16x16 multiply
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{ "mpyuw", CF_CHG1|CF_USE2|CF_USE3 }, // Unsigned 16x16 multiply
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{ "bi", CF_USE1|CF_JUMP }, // Branch indexed
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{ "bih", CF_USE1|CF_JUMP }, // Branch indexed half-word
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{ "ldi", CF_CHG1|CF_USE2 }, // Load indexed
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{ "aex", CF_USE1|CF_CHG1|CF_USE2|CF_CHG2 }, // Exchange with auxiliary register
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{ "bmskn", CF_CHG1|CF_USE2|CF_USE3 }, // Bit mask negated
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{ "seteq", CF_CHG1|CF_USE2|CF_USE3 }, // Set if equal
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{ "setne", CF_CHG1|CF_USE2|CF_USE3 }, // Set if not equal
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{ "setlt", CF_CHG1|CF_USE2|CF_USE3 }, // Set if less than
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{ "setge", CF_CHG1|CF_USE2|CF_USE3 }, // Set if greater or equal
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{ "setlo", CF_CHG1|CF_USE2|CF_USE3 }, // Set if lower than
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{ "seths", CF_CHG1|CF_USE2|CF_USE3 }, // Set if higher or same
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{ "setle", CF_CHG1|CF_USE2|CF_USE3 }, // Set if less than or equal
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{ "setgt", CF_CHG1|CF_USE2|CF_USE3 }, // Set if greater than
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{ "rol", CF_CHG1|CF_USE2 }, // Rotate left
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{ "llock", CF_CHG1|CF_USE2 }, // Load locked
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{ "scond", CF_USE1|CF_CHG2 }, // Store conditional
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{ "seti", CF_USE1 }, // Set interrupt enable and priority level
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{ "clri", CF_CHG1 }, // Clear and get interrupt enable and priority level
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// ARCv2 compact prolog / epilog instructions
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{ "enter", CF_USE1|CF_JUMP }, // Function prologue sequence
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{ "leave", CF_USE1|CF_JUMP }, // Function epilogue sequence
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// ARCv2 32-bit extension major 5 DOP instructions
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{ "div", CF_CHG1|CF_USE2|CF_USE3 }, // Signed integer divsion
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{ "divu", CF_CHG1|CF_USE2|CF_USE3 }, // Unsigned integer divsion
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{ "rem", CF_CHG1|CF_USE2|CF_USE3 }, // Signed integer remainder
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{ "remu", CF_CHG1|CF_USE2|CF_USE3 }, // Unsigned integer remainder
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{ "asrsr", CF_CHG1|CF_USE2|CF_USE3 }, // Shift right rounding and saturating
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{ "valgn2h", CF_CHG1|CF_USE2|CF_USE3 }, // Two-way 16-bit vector align
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{ "setacc", CF_USE2|CF_USE3 }, // Set the accumulator
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{ "mac", CF_CHG1|CF_USE2|CF_USE3 }, // Signed 32x32 multiply accumulate
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{ "macu", CF_CHG1|CF_USE2|CF_USE3 }, // Unsigned 32x32 multiply accumulate
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{ "dmpyh", CF_CHG1|CF_USE2|CF_USE3 }, // Sum of dual signed 16x16 multiplication
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{ "dmpyhu", CF_CHG1|CF_USE2|CF_USE3 }, // Sum of dual unsigned 16x16 multiplication
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{ "dmach", CF_CHG1|CF_USE2|CF_USE3 }, // Dual signed 16x16 multiply accumulate
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{ "dmachu", CF_CHG1|CF_USE2|CF_USE3 }, // Dual unsigned 16x16 multiply accumulate
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{ "vadd2h", CF_CHG1|CF_USE2|CF_USE3 }, // Dual 16-bit addition
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{ "vadds2h", CF_CHG1|CF_USE2|CF_USE3 }, // Dual 16-bit saturating addition
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{ "vsub2h", CF_CHG1|CF_USE2|CF_USE3 }, // Dual 16-bit subtraction
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{ "vsubs2h", CF_CHG1|CF_USE2|CF_USE3 }, // Dual 16-bit saturating subtraction
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{ "vaddsub2h", CF_CHG1|CF_USE2|CF_USE3 }, // Dual 16-bit addition/subtraction
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{ "vaddsubs2h", CF_CHG1|CF_USE2|CF_USE3 }, // Dual 16-bit saturating addition/subtraction
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{ "vsubadd2h", CF_CHG1|CF_USE2|CF_USE3 }, // Dual 16-bit subtraction/addition
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{ "vsubadds2h", CF_CHG1|CF_USE2|CF_USE3 }, // Dual 16-bit saturating subtraction/addition
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{ "mpyd", CF_CHG1|CF_CHG2|CF_USE3|CF_USE4 }, // Signed 32x32 multiply (wide)
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{ "mpydu", CF_CHG1|CF_CHG2|CF_USE3|CF_USE4 }, // Unsigned 32x32 multiply (wide)
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{ "macd", CF_CHG1|CF_CHG2|CF_USE3|CF_USE4 }, // Signed 32x32 multiply accumulate (wide)
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{ "macdu", CF_CHG1|CF_CHG2|CF_USE3|CF_USE4 }, // Unsigned 32x32 multiply accumulate (wide)
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{ "vmpy2h", CF_CHG1|CF_CHG2|CF_USE3|CF_USE4 }, // Dual signed 16x16 multiply (wide)
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{ "vmpy2hf", CF_CHG1|CF_USE2|CF_USE3 }, // Dual 16x16 saturating fractional multiply
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{ "vmpy2hu", CF_CHG1|CF_CHG2|CF_USE3|CF_USE4 }, // Dual unsigned 16x16 multiply (wide)
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{ "vmpy2hfr", CF_CHG1|CF_USE2|CF_USE3 }, // Dual 16x16 saturating rounded fractional multiply
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{ "vmac2h", CF_CHG1|CF_CHG2|CF_USE3|CF_USE4 }, // Dual signed 16x16 multiply (wide)
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{ "vmac2hf", CF_CHG1|CF_USE2|CF_USE3 }, // Dual 16x16 saturating fractional multiply
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{ "vmac2hu", CF_CHG1|CF_CHG2|CF_USE3|CF_USE4 }, // Dual unsigned 16x16 multiply (wide)
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{ "vmac2hfr", CF_CHG1|CF_USE2|CF_USE3 }, // Dual 16x16 saturating rounded fractional multiply
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{ "vmpy2hwf", CF_CHG1|CF_CHG2|CF_USE3|CF_USE4 }, // Dual 16x16 saturating fractional multiply (wide)
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{ "vasl2h", CF_CHG1|CF_USE2|CF_USE3 }, // Dual 16-bit arithmetic shift left
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{ "vasls2h", CF_CHG1|CF_USE2|CF_USE3 }, // Dual 16-bit saturating arithmetic shift left
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{ "vasr2h", CF_CHG1|CF_USE2|CF_USE3 }, // Dual 16-bit arithmetic shift right
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{ "vasrs2h", CF_CHG1|CF_USE2|CF_USE3 }, // Dual 16-bit saturating arithmetic shift right
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{ "vlsr2h", CF_CHG1|CF_USE2|CF_USE3 }, // Dual 16-bit logical shift right
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{ "vasrsr2h", CF_CHG1|CF_USE2|CF_USE3 }, // Dual 16-bit saturating rounded arithmetic shift right
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{ "vadd4b", CF_CHG1|CF_USE2|CF_USE3 }, // Quad 8-bit addition
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{ "vmax2h", CF_CHG1|CF_USE2|CF_USE3 }, // Dual 16-bit maximum
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{ "vsub4b", CF_CHG1|CF_USE2|CF_USE3 }, // Quad 8-bit subtraction
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{ "vmin2h", CF_CHG1|CF_USE2|CF_USE3 }, // Dual 16-bit minimum
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{ "adcs", CF_CHG1|CF_USE2|CF_USE3 }, // Signed saturating addition with carry in
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{ "sbcs", CF_CHG1|CF_USE2|CF_USE3 }, // Signed saturating subtraction with carry in
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{ "dmpyhwf", CF_CHG1|CF_USE2|CF_USE3 }, // Fractional saturating sum of dual 16x16 signed fractional multiply
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{ "vpack2hl", CF_CHG1|CF_USE2|CF_USE3 }, // Compose lower 16-bits
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{ "vpack2hm", CF_CHG1|CF_USE2|CF_USE3 }, // Compose upper 16-bits
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{ "dmpyhf", CF_CHG1|CF_USE2|CF_USE3 }, // Saturating sum of dual 16x16 signed fractional multiply
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{ "dmpyhfr", CF_CHG1|CF_USE2|CF_USE3 }, // Saturating rounded sum of dual 16x16 signed fractional multiply
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{ "dmachf", CF_CHG1|CF_USE2|CF_USE3 }, // Saturating sum of dual 16x16 signed fractional multiply accumulate
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{ "dmachfr", CF_CHG1|CF_USE2|CF_USE3 }, // Saturating rounded sum of dual 16x16 signed fractional multiply accumulate
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{ "vperm", CF_CHG1|CF_USE2|CF_USE3 }, // Byte permutation with zero or sign extension
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{ "bspush", CF_CHG1|CF_USE2|CF_USE3 }, // Bitstream push
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// ARCv2 32-bit extension major 5 SOP instructions
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{ "swape", CF_CHG1|CF_USE2 }, // Swap byte ordering
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{ "lsl16", CF_CHG1|CF_USE2 }, // Logical shift left by 16 bits
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{ "lsr16", CF_CHG1|CF_USE2 }, // Logical shift right by 16 bits
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{ "asr16", CF_CHG1|CF_USE2 }, // Arithmetic shift right by 16 bits
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{ "asr8", CF_CHG1|CF_USE2 }, // Arithmetic shift right by 8 bits
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{ "lsr8", CF_CHG1|CF_USE2 }, // Logical shift right by 8 bits
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{ "lsl8", CF_CHG1|CF_USE2 }, // Logical shift left by 8 bits
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{ "rol8", CF_CHG1|CF_USE2 }, // Rotate left by 8 bits
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{ "ror8", CF_CHG1|CF_USE2 }, // Rotate right by 8 bits
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{ "ffs", CF_CHG1|CF_USE2 }, // Find first set bit
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{ "fls", CF_CHG1|CF_USE2 }, // Find last set bit
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{ "getacc", CF_CHG1|CF_USE2 }, // Get accumulator
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{ "normacc", CF_CHG1|CF_USE2 }, // Normalize accumulator
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{ "satf", CF_CHG1|CF_USE2 }, // Saturate according to flags
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{ "vpack2hbl", CF_CHG1|CF_USE2 }, // Pack lower bytes into lower 16 bits
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{ "vpack2hbm", CF_CHG1|CF_USE2 }, // Pack upper bytes into upper 16 bits
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{ "vpack2hblf", CF_CHG1|CF_USE2 }, // Pack upper bytes into lower 16 bits
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{ "vpack2hbmf", CF_CHG1|CF_USE2 }, // Pack lower bytes into upper 16 bits
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{ "vext2bhlf", CF_CHG1|CF_USE2 }, // Pack lower 2 bytes into upper byte of 16 bits each
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{ "vext2bhmf", CF_CHG1|CF_USE2 }, // Pack upper 2 bytes into upper byte of 16 bits each
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{ "vrep2hl", CF_CHG1|CF_USE2 }, // Repeat lower 16 bits
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{ "vrep2hm", CF_CHG1|CF_USE2 }, // Repeat upper 16 bits
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{ "vext2bhl", CF_CHG1|CF_USE2 }, // Pack lower 2 bytes into zero extended 16 bits
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{ "vext2bhm", CF_CHG1|CF_USE2 }, // Pack upper 2 bytes into zero extended 16 bits
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{ "vsext2bhl", CF_CHG1|CF_USE2 }, // Pack lower 2 bytes into sign extended 16 bits
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{ "vsext2bhm", CF_CHG1|CF_USE2 }, // Pack upper 2 bytes into sign extended 16 bits
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{ "vabs2h", CF_CHG1|CF_USE2 }, // Dual 16-bit absolute value
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{ "vabss2h", CF_CHG1|CF_USE2 }, // Dual saturating 16-bit absolute value
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{ "vneg2h", CF_CHG1|CF_USE2 }, // Dual 16-bit negation
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{ "vnegs2h", CF_CHG1|CF_USE2 }, // Dual saturating 16-bit negation
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{ "vnorm2h", CF_CHG1|CF_USE2 }, // Dual 16-bit normalization
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{ "bspeek", CF_CHG1|CF_USE2 }, // Bitstream peek
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{ "bspop", CF_CHG1|CF_USE2 }, // Bitstream pop
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{ "sqrt", CF_CHG1|CF_USE2 }, // Integer square root
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{ "sqrtf", CF_CHG1|CF_USE2 }, // Fractional square root
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// ARCv2 32-bit extension major 5 ZOP instructions
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{ "aslacc", CF_USE1 }, // Arithmetic shift of accumulator
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{ "aslsacc", CF_USE1 }, // Saturating arithmetic shift of accumulator
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{ "flagacc", CF_USE1 }, // Copy accumulator flags to status32 register
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{ "modif", CF_USE1 }, // Update address pointer
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// ARCv2 32-bit extension major 6 DOP instructions
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{ "cmpyhnfr", CF_CHG1|CF_USE2|CF_USE3 }, // Fractional 16+16 bit complex saturating rounded unshifted multiply
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{ "cmpyhfr", CF_CHG1|CF_USE2|CF_USE3 }, // Fractional 16+16 bit complex saturating rounded multiply
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{ "cmpychfr", CF_CHG1|CF_USE2|CF_USE3 }, // Fractional 16+16 bit complex saturating rounded conjugated multiply
|
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{ "vmsub2hf", CF_CHG1|CF_USE2|CF_USE3 }, // Dual 16x16 saturating fractional multiply subtract
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{ "vmsub2hfr", CF_CHG1|CF_USE2|CF_USE3 }, // Dual 16x16 saturating rounded fractional multiply subtract
|
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{ "cmpychnfr", CF_CHG1|CF_USE2|CF_USE3 }, // Fractional 16+16 bit complex saturating rounded unshifted conjugated multiply
|
|
{ "cmachnfr", CF_CHG1|CF_USE2|CF_USE3 }, // Fractional 16+16 bit complex saturating rounded unshifted multiply accumulate
|
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{ "cmachfr", CF_CHG1|CF_USE2|CF_USE3 }, // Fractional 16+16 bit complex saturating rounded unshifted accumulate
|
|
{ "cmacchnfr", CF_CHG1|CF_USE2|CF_USE3 }, // Fractional 16+16 bit complex saturating rounded conjugated multiply accumulate
|
|
{ "cmacchfr", CF_CHG1|CF_USE2|CF_USE3 }, // Fractional 16+16 bit complex saturating rounded unshifted conjugated multiply accumulate
|
|
{ "mpyf", CF_CHG1|CF_USE2|CF_USE3 }, // Signed 32-bit fractional saturating multiply
|
|
{ "mpyfr", CF_CHG1|CF_USE2|CF_USE3 }, // Signed 32-bit fractional saturating rounded multiply
|
|
{ "macf", CF_CHG1|CF_USE2|CF_USE3 }, // Signed 32-bit fractional saturating multiply accumulate
|
|
{ "macfr", CF_CHG1|CF_USE2|CF_USE3 }, // Signed 32-bit fractional saturating rounded multiply accumulate
|
|
{ "msubf", CF_CHG1|CF_USE2|CF_USE3 }, // Signed 32-bit fractional saturating multiply subtract
|
|
{ "msubfr", CF_CHG1|CF_USE2|CF_USE3 }, // Signed 32-bit fractional saturating rounded multiply subtract
|
|
{ "divf", CF_CHG1|CF_USE2|CF_USE3 }, // Signed 32-bit fractional division
|
|
{ "vmac2hnfr", CF_CHG1|CF_USE2|CF_USE3 }, // Dual signed 16-bit fractional saturating rounded multiply accumulate
|
|
{ "vmsub2hnfr", CF_CHG1|CF_USE2|CF_USE3 }, // Dual signed 16-bit fractional saturating rounded multiply subtract
|
|
{ "mpydf", CF_CHG1|CF_CHG2|CF_USE3|CF_USE4 }, // Signed 32-bit fractional multiply (wide)
|
|
{ "macdf", CF_CHG1|CF_CHG2|CF_USE3|CF_USE4 }, // Signed 32-bit fractional multiply accumulate (wide)
|
|
{ "msubwhfl", CF_CHG1|CF_USE2|CF_USE3 }, // Signed 32 x 16 (lower) fractional saturating multiply subtract
|
|
{ "msubdf", CF_CHG1|CF_CHG2|CF_USE3|CF_USE4 }, // Signed 32-bit fractional multiply subtract (wide)
|
|
{ "dmpyhbl", CF_CHG1|CF_USE2|CF_USE3 }, // Dual 16x8 signed multiply with lower two bytes
|
|
{ "dmpyhbm", CF_CHG1|CF_USE2|CF_USE3 }, // Dual 16x8 signed multiply with upper two bytes
|
|
{ "dmachbl", CF_CHG1|CF_USE2|CF_USE3 }, // Dual 16x8 signed multiply accumulate with lower two bytes
|
|
{ "dmachbm", CF_CHG1|CF_USE2|CF_USE3 }, // Dual 16x8 signed multiply accumulate with upper two bytes
|
|
{ "msubwhflr", CF_CHG1|CF_USE2|CF_USE3 }, // Signed 32 x 16 (lower) fractional saturating rounded multiply subtract
|
|
{ "cmpyhfmr", CF_CHG1|CF_USE2|CF_USE3 }, // Fractional 16+16 bit complex x 16bit real (upper) saturating rounded multiply
|
|
{ "cbflyhf0r", CF_CHG1|CF_USE2|CF_USE3 }, // Fractional 16+16 bit complex FFT butterfly, first half
|
|
{ "mpywhl", CF_CHG1|CF_USE2|CF_USE3 }, // Signed 32 x 16 (lower) multiply
|
|
{ "macwhl", CF_CHG1|CF_USE2|CF_USE3 }, // Signed 32 x 16 (lower) multiply accumulate
|
|
{ "mpywhul", CF_CHG1|CF_USE2|CF_USE3 }, // Unsigned 32 x 16 (lower) multiply
|
|
{ "macwhul", CF_CHG1|CF_USE2|CF_USE3 }, // Unsigned 32 x 16 (lower) multiply accumulate
|
|
{ "mpywhfm", CF_CHG1|CF_USE2|CF_USE3 }, // Signed 32 x 16 (upper) fractional saturating multiply
|
|
{ "mpywhfmr", CF_CHG1|CF_USE2|CF_USE3 }, // Signed 32 x 16 (upper) fractional saturating rounded multiply
|
|
{ "macwhfm", CF_CHG1|CF_USE2|CF_USE3 }, // Signed 32 x 16 (upper) fractional saturating multiply accumulate
|
|
{ "macwhfmr", CF_CHG1|CF_USE2|CF_USE3 }, // Signed 32 x 16 (upper) fractional saturating rounded multiply accumulate
|
|
{ "mpywhfl", CF_CHG1|CF_USE2|CF_USE3 }, // Signed 32 x 16 (lower) fractional saturating multiply
|
|
{ "mpywhflr", CF_CHG1|CF_USE2|CF_USE3 }, // Signed 32 x 16 (lower) fractional saturating rounded multiply
|
|
{ "macwhfl", CF_CHG1|CF_USE2|CF_USE3 }, // Signed 32 x 16 (lower) fractional saturating multiply accumulate
|
|
{ "macwhflr", CF_CHG1|CF_USE2|CF_USE3 }, // Signed 32 x 16 (lower) fractional saturating rounded multiply accumulate
|
|
{ "macwhkl", CF_CHG1|CF_USE2|CF_USE3 }, // Signed 32 x 16 (lower) 16-bit shifted multiply accumulate
|
|
{ "macwhkul", CF_CHG1|CF_USE2|CF_USE3 }, // Unsigned 32 x 16 (lower) 16-bit shifted multiply accumulate
|
|
{ "mpywhkl", CF_CHG1|CF_USE2|CF_USE3 }, // Signed 32 x 16 (lower) 16-bit shifted multiply
|
|
{ "mpywhkul", CF_CHG1|CF_USE2|CF_USE3 }, // Unsigned 32 x 16 (lower) 16-bit shifted multiply
|
|
{ "msubwhfm", CF_CHG1|CF_USE2|CF_USE3 }, // Signed 32 x 16 (upper) fractional saturating multiply subtract
|
|
{ "msubwhfmr", CF_CHG1|CF_USE2|CF_USE3 }, // Signed 32 x 16 (upper) fractional saturating rounded multiply subtract
|
|
|
|
// ARCv2 32-bit extension major 6 SOP instructions
|
|
{ "cbflyhf1r", CF_CHG1|CF_USE2 }, // Fractional 16+16 bit complex FFT butterfly, second half
|
|
|
|
{ "fscmp", CF_USE1|CF_USE2 }, // Single precision floating point compare
|
|
{ "fscmpf", CF_USE1|CF_USE2 }, // Single precision floating point compare (IEEE 754 flag generation)
|
|
{ "fsmadd", CF_CHG1|CF_USE2|CF_USE3 }, // Single precision floating point fused multiply add
|
|
{ "fsmsub", CF_CHG1|CF_USE2|CF_USE3 }, // Single precision floating point fused multiply subtract
|
|
{ "fsdiv", CF_CHG1|CF_USE2|CF_USE3 }, // Single precision floating point division
|
|
{ "fcvt32", CF_CHG1|CF_USE2 }, // Single precision floating point / integer conversion
|
|
{ "fssqrt", CF_CHG1|CF_USE2|CF_USE3 }, // Single precision floating point square root
|
|
|
|
// ARCv2 jump / execute indexed instructions
|
|
{ "jli", CF_USE1|CF_CALL }, // Jump and link
|
|
{ "ei", CF_USE1|CF_CALL }, // Execute indexed
|
|
|
|
{ "kflag", CF_USE1 }, // Set kernel flags
|
|
{ "wevt", CF_USE1 }, // Enter sleep state
|
|
};
|
|
|
|
CASSERT(qnumber(Instructions) == ARC_last);
|
|
|