update to ida 7.6, add builds
This commit is contained in:
423
idasdk76/module/tms320c55/tms320c55.hpp
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423
idasdk76/module/tms320c55/tms320c55.hpp
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/*
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* Interactive disassembler (IDA).
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* Copyright (c) 1990-99 by Ilfak Guilfanov.
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* ALL RIGHTS RESERVED.
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* E-mail: ig@datarescue.com
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*
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*
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*/
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#ifndef _TMS320C55_HPP
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#define _TMS320C55_HPP
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#include "../idaidp.hpp"
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#include <diskio.hpp>
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#include "ins.hpp"
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#include "../iohandler.hpp"
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// #define TMS320C55_NO_NAME_NO_REF
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//------------------------------------------------------------------
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enum regnum_t ENUM_SIZE(uint16)
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{
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AC0, // Accumulator
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AC1, // Accumulator
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AC2, // Accumulator
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AC3, // Accumulator
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T0, // Temporary register
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T1, // Temporary register
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T2, // Temporary register
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T3, // Temporary register
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AR0, // Auxiliary register
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AR1, // Auxiliary register
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AR2, // Auxiliary register
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AR3, // Auxiliary register
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AR4, // Auxiliary register
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AR5, // Auxiliary register
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AR6, // Auxiliary register
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AR7, // Auxiliary register
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AC0L, // Accumulator
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AC0H, // Accumulator
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AC0G, // Accumulator
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AC1L, // Accumulator
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AC1H, // Accumulator
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AC1G, // Accumulator
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AC2L, // Accumulator
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AC2H, // Accumulator
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AC2G, // Accumulator
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AC3L, // Accumulator
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AC3H, // Accumulator
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AC3G, // Accumulator
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BK03, // Circular buffer size register
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BK47, // Circular buffer size register
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BKC, // Circular buffer size register
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BRC0, // Block-repeat counter
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BRC1, // Block-repeat counter
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BRS1, // BRC1 save register
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BSA01, // Circulat buffer start address register
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BSA23, // Circulat buffer start address register
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BSA45, // Circulat buffer start address register
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BSA67, // Circulat buffer start address register
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BSAC, // Circulat buffer start address register
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CDP, // Coefficient data pointer (low part of XCDP)
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CDPH, // High part of XCDP
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CFCT, // Control-flow contect register
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CSR, // Computed single-repeat register
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DBIER0, // Debug interrupt enable register
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DBIER1, // Debug interrupt enable register
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// DP Data page register (low part of XDP)
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// DPH High part of XDP
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IER0, // Interrupt enable register
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IER1, // Interrupt enable register
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IFR0, // Interrupt flag register
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IFR1, // Interrupt flag register
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IVPD,
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IVPH,
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PC, // Program counter
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// PDP Peripheral data page register
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PMST,
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REA0, // Block-repeat end address register
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REA0L, // Block-repeat end address register
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REA0H, // Block-repeat end address register
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REA1, // Block-repeat end address register
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REA1L, // Block-repeat end address register
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REA1H, // Block-repeat end address register
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RETA, // Return address register
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RPTC, // Single-repeat counter
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RSA0, // Block-repeat start address register
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RSA0L, // Block-repeat start address register
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RSA0H, // Block-repeat start address register
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RSA1, // Block-repeat start address register
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RSA1L, // Block-repeat start address register
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RSA1H, // Block-repeat start address register
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SP, // Data stack pointer
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SPH, // High part of XSP and XSSP
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SSP, // System stack pointer
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ST0, // Status register
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ST1, // Status register
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ST0_55, // Status register
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ST1_55, // Status register
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ST2_55, // Status register
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ST3_55, // Status register
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TRN0, // Transition register
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TRN1, // Transition register
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XAR0, // Extended auxiliary register
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XAR1, // Extended auxiliary register
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XAR2, // Extended auxiliary register
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XAR3, // Extended auxiliary register
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XAR4, // Extended auxiliary register
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XAR5, // Extended auxiliary register
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XAR6, // Extended auxiliary register
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XAR7, // Extended auxiliary register
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XCDP, // Extended coefficient data pointer
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XDP, // Extended data page register
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XPC, // Extended program counter
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XSP, // Extended data stack pointer
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XSSP, // Extended system stack pointer
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// these seem to be an old way of what is now DPH/CDPH/AR0H..AR7H
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// i.e. supply bits 22:16 of the address for specific situations)
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MDP, // Main Data page pointer (direct memory access / indirect from CDP)
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MDP05, // Main Data page pointer (indirect AR[0-5])
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MDP67, // Main Data page pointer (indirect AR[6-7])
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// flags
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ACOV2,
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ACOV3,
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TC1,
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TC2,
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CARRY,
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ACOV0,
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ACOV1,
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BRAF,
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XF,
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HM,
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INTM,
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M40,
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SATD,
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SXMD,
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C16,
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FRCT,
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C54CM,
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DBGM,
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EALLOW,
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RDM,
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CDPLC,
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AR7LC,
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AR6LC,
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AR5LC,
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AR4LC,
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AR3LC,
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AR2LC,
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AR1LC,
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AR0LC,
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CAFRZ,
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CAEN,
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CACLR,
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HINT,
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CBERR,
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MPNMC,
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SATA,
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CLKOFF,
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SMUL,
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SST,
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BORROW,
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// segment registers
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ARMS, // AR indirect operands available
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CPL, // Compiler mode
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DP, // Data page pointer
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DPH, // Data page
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PDP, // Peripheral data page register
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rVcs, rVds, // virtual registers for code and data segments
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};
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//------------------------------------------------------------------
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// specific condition codes
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#define COND_A 0x0
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#define COND_B 0x8
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#define COND_GEQ 0x2
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#define COND_LT 0x3
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#define COND_NEQ 0x4
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#define COND_EQ 0x5
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#define COND_GT 0x6
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#define COND_LEQ 0x7
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#define COND4_AGEQ (COND_A | COND_GEQ)
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#define COND4_ALT (COND_A | COND_LT)
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#define COND4_ANEQ (COND_A | COND_NEQ)
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#define COND4_AEQ (COND_A | COND_EQ)
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#define COND4_AGT (COND_A | COND_GT)
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#define COND4_ALEQ (COND_A | COND_LEQ)
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#define COND4_BGEQ (COND_B | COND_GEQ)
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#define COND4_BLT (COND_B | COND_LT)
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#define COND4_BNEQ (COND_B | COND_NEQ)
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#define COND4_BEQ (COND_B | COND_EQ)
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#define COND4_BGT (COND_B | COND_GT)
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#define COND4_BLEQ (COND_B | COND_LEQ)
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#define COND8_FROM_COND4 0x40
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#define COND8_UNC 0x00
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#define COND8_NBIO 0x02
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#define COND8_BIO 0x03
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#define COND8_NC 0x08
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#define COND8_C 0x0C
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#define COND8_NTC 0x20
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#define COND8_TC 0x30
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#define COND8_AGEQ (COND8_FROM_COND4 | COND4_AGEQ)
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#define COND8_ALT (COND8_FROM_COND4 | COND4_ALT)
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#define COND8_ANEQ (COND8_FROM_COND4 | COND4_ANEQ)
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#define COND8_AEQ (COND8_FROM_COND4 | COND4_AEQ)
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#define COND8_AGT (COND8_FROM_COND4 | COND4_AGT)
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#define COND8_ALEQ (COND8_FROM_COND4 | COND4_ALEQ)
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#define COND8_ANOV 0x60
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#define COND8_AOV 0x70
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#define COND8_BGEQ (COND8_FROM_COND4 | COND4_BGEQ)
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#define COND8_BLT (COND8_FROM_COND4 | COND4_BLT)
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#define COND8_BNEQ (COND8_FROM_COND4 | COND4_BNEQ)
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#define COND8_BEQ (COND8_FROM_COND4 | COND4_BEQ)
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#define COND8_BGT (COND8_FROM_COND4 | COND4_BGT)
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#define COND8_BLEQ (COND8_FROM_COND4 | COND4_BLEQ)
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#define COND8_BNOV (COND_B | COND8_ANOV)
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#define COND8_BOV (COND_B | COND8_AOV)
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//------------------------------------------------------------------
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#define Parallel segpref // number of operands for the first line of a parallel instruction
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#define TMS_PARALLEL_BIT -1
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#define SpecialModes auxpref_u8[0]
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#define TMS_MODE_USER_PARALLEL 0x1 // user parallel bit (E) is set
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#define TMS_MODE_LR 0x2 // LR postfix
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#define TMS_MODE_CR 0x4 // CR postfix
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#define TMS_MODE_SIMULATE_USER_PARALLEL 0x8 // the instruction simulate two instructions linked by a user parallelism
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#define OpMem auxpref_u8[1]
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// complex operands
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// for o_reg, o_imm, o_mem
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#define tms_shift specval_shorts.low // operand << value
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#define TMS_OP_SHIFT_NULL 0 // no shift
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#define TMS_OP_SHIFT_TYPE 0x7FFF
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#define TMS_OP_SHIFTL_IMM 1 // operand << #...
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#define TMS_OP_SHIFTL_REG 2 // operand << reg
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#define TMS_OP_SHIFTR_IMM 3 // operand >> #...
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#define TMS_OP_EQ 4 // operand == #...
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#define TMS_OP_NEQ 5 // operand != #...
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#define TMS_OP_SHIFT_OUT 0x8000 // functions(...) << ... (default = functions(... << ...))
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#define tms_shift_value specval_shorts.high
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// for o_reg, o_mem
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#define tms_modifier specflag2
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#define TMS_MODIFIER_NULL 0
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// o_reg
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#define TMS_MODIFIER_REG 1 // *reg
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#define TMS_MODIFIER_REG_P 2 // *reg+
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#define TMS_MODIFIER_REG_M 3 // *reg-
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#define TMS_MODIFIER_REG_P_T0 4 // *(reg+T0)
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#define TMS_MODIFIER_REG_P_T1 5 // *(reg+T1)
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#define TMS_MODIFIER_REG_M_T0 6 // *(reg-T0)
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#define TMS_MODIFIER_REG_M_T1 7 // *(reg-T1)
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#define TMS_MODIFIER_REG_T0 8 // *reg(T0)
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#define TMS_MODIFIER_REG_OFFSET 9 // *reg(#value)
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#define TMS_MODIFIER_P_REG_OFFSET 10 // *+reg(#value)
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#define TMS_MODIFIER_REG_SHORT_OFFSET 11 // *reg(short(#value))
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#define TMS_MODIFIER_REG_T1 12 // *reg(T1)
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#define TMS_MODIFIER_P_REG 13 // *+reg
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#define TMS_MODIFIER_M_REG 14 // *-reg
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#define TMS_MODIFIER_REG_P_T0B 15 // *(reg+T0B)
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#define TMS_MODIFIER_REG_M_T0B 16 // *(reg-T0B)
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// o_mem, o_io
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#define TMS_MODIFIER_DMA 1 // @addr
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#define TMS_MODIFIER_ABS16 2 // *abs16(#addr)
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#define TMS_MODIFIER_PTR 3 // *(#addr)
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#define TMS_MODIFIER_MMAP 4 // mmap()
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#define TMS_MODIFIER_PORT 5 // port(#addr)
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#define TMS_MODIFIER_PORT_AT 6 // port(@addr)
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// for o_reg, o_mem, o_io
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#define tms_operator1 specflag3 // operators sorted by priority order
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#define tms_operator2 specflag4
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#define TMS_OPERATORS_SIZE 13
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#define TMS_OPERATOR_NULL 0x0000
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#define TMS_OPERATOR_T3 0x0001 // T3=xxx
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#define TMS_OPERATOR_NOT 0x0002 // !xxx
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#define TMS_OPERATOR_UNS 0x0004 // uns(xxx)
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#define TMS_OPERATOR_DBL 0x0008 // dbl(xxx)
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#define TMS_OPERATOR_RND 0x0010 // rnd(xxx)
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#define TMS_OPERATOR_PAIR 0x0020 // pair(xxx)
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#define TMS_OPERATOR_LO 0x0040 // lo(xxx)
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#define TMS_OPERATOR_HI 0x0080 // hi(xxx)
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#define TMS_OPERATOR_LB 0x0100 // low_byte(xxx)
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#define TMS_OPERATOR_HB 0x0200 // high_byte(xxx)
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#define TMS_OPERATOR_SAT 0x0400 // saturate(xxx)
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#define TMS_OPERATOR_DUAL 0x0800 // dual(xxx)
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#define TMS_OPERATOR_PORT 0x1000 // port(xxx)
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// for o_imm
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#define tms_signed specflag1
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#define tms_prefix specflag2
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// for o_mem (real address = tms_reg_h : tms_reg_p + addr)
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#define tms_regH value_shorts.low
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#define tms_regP value_shorts.high
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#define o_cond o_idpspec0
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#define o_shift o_idpspec1
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#define o_relop o_idpspec2
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#define tms_relop specflag1 // relational operator
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#define tms_relop_type specflag2 // o_reg, o_imm
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#define TMS_RELOP_REG 1 // operand << #...
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#define TMS_RELOP_IMM 2 // operand << reg
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// value will contain register or immediate
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#define o_io o_idpspec3
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//------------------------------------------------------------------
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// processor types
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typedef uchar proctype_t;
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const proctype_t TMS320C55 = 0;
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//------------------------------------------------------------------
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#define TAG_SDUAL '2' // helper.altval(ea, '2') == length of the first part of sdual instruction
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#define TMS320C55_IO 0x0001 // use I/O definitions
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#define TMS320C55_MMR 0x0002 // use memory mapped registers
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//------------------------------------------------------------------
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const char *const cfgname = "tms320c55.cfg";
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struct tms320c55_iohandler_t : public iohandler_t
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{
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struct tms320c55_t ±
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qstring errbuf;
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tms320c55_iohandler_t(tms320c55_t &_pm, netnode &nn) : iohandler_t(nn), pm(_pm) {}
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void get_cfg_filename(char *buf, size_t bufsize) override
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{
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qstrncpy(buf, cfgname, bufsize);
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}
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};
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struct mask_t;
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class bytes_c;
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struct tms320c55_t : public procmod_t
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{
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netnode helper;
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tms320c55_iohandler_t ioh = tms320c55_iohandler_t(*this, helper);
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ushort idpflags = TMS320C55_IO|TMS320C55_MMR;
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proctype_t ptype = TMS320C55; // contains processor type
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bool flow = false;
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char optional_op = -1; // ana: index of an optional operand
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ssize_t idaapi on_event(ssize_t msgid, va_list va) override;
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const char *find_sym(ea_t address);
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const char *idaapi set_idp_options(
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const char *keyword,
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int value_type,
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const void * value,
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bool idb_loaded);
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int ana(insn_t *insn);
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void process_masks(
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insn_t &insn,
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const mask_t *masks,
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ushort itype_null,
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bytes_c &bytes,
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char lbytesize = 8);
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bool process_masks_operand(
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insn_t &insn,
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const mask_t *mask,
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int64 code,
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int64 op_mask_n,
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unsigned *p_opnum,
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bool bTest);
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int emu(const insn_t &insn);
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void handle_operand(const insn_t &insn, const op_t &op, flags_t F, bool use);
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int get_mapped_register(ea_t ea) const;
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void assumes(outctx_t &ctx);
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void print_segment_register(outctx_t &ctx, int reg, sel_t value);
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void segstart(outctx_t &ctx, segment_t *seg) const;
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void footer(outctx_t &ctx) const;
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void gen_stkvar_def(outctx_t &ctx, const member_t *mptr, sval_t v) const;
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void save_idpflags() { helper.altset(-1, idpflags); }
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void load_from_idb();
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};
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extern int data_id;
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#define PROCMOD_NODE_NAME "$ tms320c54"
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#define PROCMOD_NAME tms320c55
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const char *find_sym(ea_t address);
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//------------------------------------------------------------------
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void idaapi header(outctx_t &ctx);
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void idaapi segend(outctx_t &ctx, segment_t *seg);
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void idaapi data(outctx_t &ctx);
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bool idaapi create_func_frame(func_t *pfn);
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int idaapi is_align_insn(ea_t ea);
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bool idaapi can_have_type(const op_t &op);
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ea_t calc_io_mem(const insn_t &insn, const op_t &op);
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ea_t calc_data_mem(const insn_t &insn, const op_t &op);
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inline ea_t calc_code_mem(const insn_t &insn, ea_t ea)
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{
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return to_ea(insn.cs, ea);
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}
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#endif // _TMS320C55_HPP
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