update to ida 7.6, add builds
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181
idasdk76/module/hppa/ins.cpp
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181
idasdk76/module/hppa/ins.cpp
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/* -
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* Interactive disassembler (IDA).
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* Copyright (c) 1990-2000 by Ilfak Guilfanov.
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* ALL RIGHTS RESERVED.
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* E-mail: ig@datarescue.com
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*
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*
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*/
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#include "hppa.hpp"
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/*
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#define u 1
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#define c 2
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#define o1(x) ((x & u) ? CF_USE1 : 0) | (x & c) ? CF_CHG1 : 0))
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#define o2(x) ((x & u) ? CF_USE2 : 0) | (x & c) ? CF_CHG2 : 0))
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#define o3(x) ((x & u) ? CF_USE3 : 0) | (x & c) ? CF_CHG3 : 0))
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#define OPS(x,y,z,others) (o1(x) | o2(y) | o3(z) | others)
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*/
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const instruc_t Instructions[] =
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{
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{ "", 0 }, // Unknown Operation
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{ "add", CF_USE1|CF_USE2|CF_CHG3 }, // Add
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{ "addb", CF_USE1|CF_USE2|CF_CHG2|CF_USE3 }, // Add and Branch
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{ "addi", CF_USE1|CF_USE2|CF_CHG3 }, // Add to Immediate
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{ "addib", CF_USE1|CF_USE2|CF_CHG2|CF_USE3 }, // Add Immediate and Branch
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{ "addil", CF_USE1|CF_USE2 }, // Add to Immediate Left
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{ "and", CF_USE1|CF_USE2|CF_CHG3 }, // AND
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{ "andcm", CF_USE1|CF_USE2|CF_CHG3 }, // AND complement
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{ "b", CF_USE1|CF_CHG2 }, // Branch
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{ "bb", CF_USE1|CF_USE2|CF_USE3 }, // Branch on Bit
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{ "be", CF_USE1 }, // Branch External
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{ "blr", CF_USE1|CF_CHG2|CF_CALL }, // Branch and Link Register
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{ "break", CF_USE1|CF_USE2 }, // Break
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{ "bv", CF_USE1 }, // Branch Vectored
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{ "bve", CF_USE1 }, // Branch Vectored External
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{ "cldd", CF_USE1|CF_CHG2 }, // Coprocessor Load Doubleword
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{ "cldw", CF_USE1|CF_CHG2 }, // Coprocessor Load Word
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{ "clrbts", 0 }, // Clear Branch Target Stack
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{ "cmpb", CF_USE1|CF_USE2|CF_USE3 }, // Compare and Branch
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{ "cmpclr", CF_USE1|CF_USE2|CF_CHG3 }, // Compare and Clear
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{ "cmpib", CF_USE1|CF_USE2|CF_USE3 }, // Compare Immediate and Branch
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{ "cmpiclr", CF_USE1|CF_USE2|CF_CHG3 }, // Compare Immediate and Clear
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{ "copr", 0 }, // Coprocessor Operation
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{ "cstd", CF_USE1|CF_CHG2 }, // Coprocessor Store Doubleword
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{ "cstw", CF_USE1|CF_CHG2 }, // Coprocessor Store Word
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{ "dcor", CF_USE1|CF_CHG2 }, // Decimal Correct
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{ "depd", CF_USE1|CF_USE2|CF_USE3|CF_CHG4 }, // Deposit Doubleword
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{ "depdi", CF_USE1|CF_USE2|CF_USE3|CF_CHG4 }, // Deposit Doubleword Immediate
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{ "depw", CF_USE1|CF_USE2|CF_USE3|CF_CHG4 }, // Deposit Word
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{ "depwi", CF_USE1|CF_USE2|CF_USE3|CF_CHG4 }, // Deposit Word Immediate
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{ "diag", CF_USE1 }, // Diagnose
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{ "ds", CF_USE1|CF_USE2|CF_CHG3 }, // Divide Step
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{ "extrd", CF_USE1|CF_USE2|CF_USE3|CF_CHG4 }, // Extract Doubleword
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{ "extrw", CF_USE1|CF_USE2|CF_USE3|CF_CHG4 }, // Extract Word
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{ "fdc", CF_USE1 }, // Flush Data Cache
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{ "fdce", CF_USE1 }, // Flush Data Cache Entry
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{ "fic", CF_USE1 }, // Flush Instruction Cache
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{ "fice", CF_USE1 }, // Flush Instruction Cache Entry
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{ "hadd", CF_USE1|CF_USE2|CF_CHG3 }, // Halfword Parallel Add
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{ "havg", CF_USE1|CF_USE2|CF_CHG3 }, // Halfword Parallel Average
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{ "hshl", CF_USE1|CF_USE2|CF_CHG3 }, // Halfword Parallel Shift Left
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{ "hshladd", CF_USE1|CF_USE2|CF_USE3|CF_CHG4 }, // Halfword Parallel Shift Left and Add
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{ "hshr", CF_USE1|CF_USE2|CF_CHG3 }, // Halfword Parallel Shift Right
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{ "hshradd", CF_USE1|CF_USE2|CF_USE3|CF_CHG4 }, // Halfword Parallel Shift Right and Add
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{ "hsub", CF_USE1|CF_USE2|CF_CHG3 }, // Halfword Parallel Subtract
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{ "idtlbt", CF_USE1|CF_USE2 }, // Insert Data TLB Translation
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{ "iitlbt", CF_USE1|CF_USE2 }, // Insert Instruction TLB Translation
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{ "lci", CF_USE1|CF_CHG2 }, // Load Coherence Index
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{ "ldb", CF_USE1|CF_CHG2 }, // Load Byte
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{ "ldcd", CF_USE1|CF_CHG2 }, // Load and Clear Doubleword
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{ "ldcw", CF_USE1|CF_CHG2 }, // Load and Clear Word
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{ "ldd", CF_USE1|CF_CHG2 }, // Load Doubleword
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{ "ldda", CF_USE1|CF_CHG2 }, // Load Doubleword Absolute
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{ "ldh", CF_USE1|CF_CHG2 }, // Load Halfword
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{ "ldil", CF_USE1|CF_CHG2 }, // Load Immediate Left
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{ "ldo", CF_USE1|CF_CHG2 }, // Load Offset
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{ "ldsid", CF_USE1|CF_CHG2 }, // Load Space Identifier
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{ "ldw", CF_USE1|CF_CHG2 }, // Load Word
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{ "ldwa", CF_USE1|CF_CHG2 }, // Load Word Absolute
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{ "lpa", CF_USE1|CF_CHG2 }, // Load Physical Address
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{ "mfctl", CF_USE1|CF_CHG2 }, // Move From Control Register
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{ "mfia", CF_CHG1 }, // Move From Instruction Address
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{ "mfsp", CF_USE1|CF_CHG2 }, // Move From Space Register
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{ "mixh", CF_USE1|CF_USE2|CF_CHG3 }, // Mix Halfwords
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{ "mixw", CF_USE1|CF_USE2|CF_CHG3 }, // Mix Words
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{ "movb", CF_USE1|CF_CHG2|CF_USE3 }, // Move and Branch
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{ "movib", CF_USE1|CF_CHG2|CF_USE3 }, // Move Immediate and Branch
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{ "mtctl", CF_USE1|CF_CHG2 }, // Move To Control Register
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{ "mtsarcm", CF_USE1 }, // Move To Shift Amount Register Complement
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{ "mtsm", CF_USE1 }, // Move To System Mask
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{ "mtsp", CF_USE1|CF_CHG2 }, // Move To Space Register
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{ "or", CF_USE1|CF_USE2|CF_CHG3 }, // Inclusive OR
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{ "pdc", CF_USE1 }, // Purge Data Cache
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{ "pdtlb", CF_USE1 }, // Purge Data TLB
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{ "pdtlbe", CF_USE1 }, // Purge Data TLB Entry
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{ "permh", CF_USE1|CF_CHG2 }, // Permute Halfwords
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{ "pitlb", CF_USE1 }, // Purge Instruction TLB
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{ "pitlbe", CF_USE1 }, // Purge Instruction TLB Entry
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{ "popbts", CF_USE1 }, // Pop Branch Target Stack
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{ "probe", CF_USE1|CF_USE2|CF_CHG3 }, // Probe Access
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{ "probei", CF_USE1|CF_USE2|CF_CHG3 }, // Probe Access Immediate
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{ "pushbts", CF_USE1 }, // Push Branch Target Stack
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{ "pushnom", 0 }, // Push Nominated
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{ "rfi", 0 }, // Return From Interruption
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{ "rsm", CF_USE1|CF_CHG2 }, // Reset System Mask
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{ "shladd", CF_USE1|CF_USE2|CF_USE3|CF_CHG4 }, // Shift Left and Add
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{ "shrpd", CF_USE1|CF_USE2|CF_USE3|CF_CHG4 }, // Sihft Right Pair Doubleword
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{ "shrpw", CF_USE1|CF_USE2|CF_USE3|CF_CHG4 }, // Sihft Right Pair Word
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{ "spop0", 0 }, // Special Operation Zero
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{ "spop1", CF_CHG1 }, // Special Operation One
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{ "spop2", CF_USE1 }, // Special Operation Two
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{ "spop3", CF_USE1|CF_USE2 }, // Special Operation Three
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{ "ssm", CF_USE1|CF_CHG2 }, // Set System Mask
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{ "stb", CF_USE1|CF_CHG2 }, // Store Byte
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{ "stby", CF_USE1|CF_CHG2 }, // Store Bytes
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{ "std", CF_USE1|CF_CHG2 }, // Store Doubleword
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{ "stda", CF_USE1|CF_CHG2 }, // Store Doubleword Absolute
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{ "stdby", CF_USE1|CF_CHG2 }, // Store Doubleword Bytes
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{ "sth", CF_USE1|CF_CHG2 }, // Store Halfword
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{ "stw", CF_USE1|CF_CHG2 }, // Store Word
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{ "stwa", CF_USE1|CF_CHG2 }, // Store Word Absolute
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{ "sub", CF_USE1|CF_USE2|CF_CHG3 }, // Subtract
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{ "subi", CF_USE1|CF_USE2|CF_CHG3 }, // Subtract from Immediate
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{ "sync", 0 }, // Synchronize Caches
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{ "syncdma", 0 }, // Synchronize DMA
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{ "uaddcm", CF_USE1|CF_USE2|CF_CHG3 }, // Unit Add Complement
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{ "uxor", CF_USE1|CF_USE2|CF_CHG3 }, // Unit XOR
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{ "xor", CF_USE1|CF_USE2|CF_CHG3 }, // Exclusive OR
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// Floating point instructions
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{ "fabs", CF_USE1|CF_CHG2 }, // Floating-Point Absolute Value
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{ "fadd", CF_USE1|CF_USE2|CF_CHG3 }, // Floating-Point Add
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{ "fcmp", CF_USE1|CF_USE2|CF_CHG3 }, // Floating-Point Compare
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{ "fcnv", CF_USE1|CF_CHG2 }, // Floating-Point Convert
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{ "fcpy", CF_USE1|CF_CHG2 }, // Floating-Point Copy
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{ "fdiv", CF_USE1|CF_USE2|CF_CHG3 }, // Floating-Point Divide
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{ "fid", 0 }, // Floating-Point Identity
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{ "fldd", CF_USE1|CF_CHG2 }, // Floating-Point Load Doubleword
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{ "fldw", CF_USE1|CF_CHG2 }, // Floating-Point Load Word
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{ "fmpy", CF_USE1|CF_USE2|CF_CHG3 }, // Floating-Point Multiply
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{ "fmpyadd", CF_USE1|CF_USE2|CF_CHG3|CF_USE4|CF_CHG5 }, // Floating-Point Multiply/Add
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{ "fmpyfadd", CF_USE1|CF_USE2|CF_USE3|CF_CHG4 }, // Floating-Point Multiply Fused Add
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{ "fmpynfadd", CF_USE1|CF_USE2|CF_USE3|CF_CHG4 }, // Floating-Point Multiply Negate Fused Add
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{ "fmpysub", CF_USE1|CF_USE2|CF_CHG3|CF_USE4|CF_CHG5 }, // Floating-Point Multiply/Subtract
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{ "fneg", CF_USE1|CF_CHG2 }, // Floating-Point Negate
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{ "fnegabs", CF_USE1|CF_CHG2 }, // Floating-Point Negate Absolute Value
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{ "frem", CF_USE1|CF_USE2|CF_CHG3 }, // Floating-Point Remainder
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{ "frnd", CF_USE1|CF_CHG2 }, // Floating-Point Round to Integer
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{ "fsqrt", CF_USE1|CF_CHG2 }, // Floating-Point Square Root
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{ "fstd", CF_USE1|CF_CHG2 }, // Floating-Point Store Doubleword
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{ "fstw", CF_USE1|CF_CHG2 }, // Floating-Point Store Word
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{ "fsub", CF_USE1|CF_USE2|CF_CHG3 }, // Floating-Point Subtract
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{ "ftest", CF_CHG1 }, // Floating-Point Test
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{ "xmpyu", CF_USE1|CF_USE2|CF_CHG3 }, // Fixed-Point Multiply Unsigned
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// Performance Monitor Coprocessor
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{ "pmdis", 0 }, // Performance Monitor Disable
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{ "pmenb", 0 }, // Performance Monitor Enable
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// Macros
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{ "call", CF_USE1|CF_CALL }, // Call Subroutine
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{ "ret", 0 }, // Return From Subroutine
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{ "shld", CF_USE1|CF_USE2|CF_CHG3 }, // Shift Left Doubleword
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{ "shlw", CF_USE1|CF_USE2|CF_CHG3 }, // Shift Left Word
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{ "shrd", CF_USE1|CF_USE2|CF_CHG3 }, // Shift Right Doubleword
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{ "shrw", CF_USE1|CF_USE2|CF_CHG3 }, // Shift Right Word
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{ "ldi", CF_USE1|CF_CHG2 }, // Load Immediate
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{ "copy", CF_USE1|CF_CHG2 }, // Copy Register
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{ "mtsar", CF_USE1 }, // Move To %SAR
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{ "nop", 0 }, // No Operation
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};
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CASSERT(qnumber(Instructions) == HPPA_last);
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