update to ida 7.6, add builds
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305
idasdk76/module/h8/h8.hpp
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305
idasdk76/module/h8/h8.hpp
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/*
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* Interactive disassembler (IDA).
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* Copyright (c) 1990-99 by Ilfak Guilfanov.
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* ALL RIGHTS RESERVED.
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* E-mail: ig@datarescue.com
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*
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*
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*/
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#ifndef _H8_HPP
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#define _H8_HPP
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#include "../idaidp.hpp"
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#include <diskio.hpp>
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#include "ins.hpp"
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#include "../iohandler.hpp"
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#define PROCMOD_NAME h8
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#define PROCMOD_NODE_NAME "$ h8"
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//------------------------------------------------------------------
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// processor types
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typedef uint16 proctype_t;
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static const proctype_t none = 0;
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static const proctype_t P300 = 0x0001; // H8/300, H8/300H
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static const proctype_t P2000 = 0x0002; // H8S/2000
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static const proctype_t P2600 = 0x0004; // H8S/2600
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static const proctype_t PSX = 0x0008; // H8SX
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// assume 'Normal mode' as the default
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static const proctype_t MODE_MASK= 0xF000;
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static const proctype_t MODE_MID = 0x1000; // H8SX
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static const proctype_t MODE_ADV = 0x2000; // H8/300H (!), H8S, H8SX
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static const proctype_t MODE_MAX = 0x3000; // H8SX
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// submodel
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static const proctype_t SUBM_MASK= 0x0F00;
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static const proctype_t SUBM_TINY= 0x0100; // H8/300H Tiny model
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// full insn set and normal mode
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static const proctype_t P30A = P300 | MODE_ADV;
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static const proctype_t P26A = P2600 | MODE_ADV;
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//------------------------------------------------------------------
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#ifdef _MSC_VER
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#define ENUM8BIT : uint8
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#else
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#define ENUM8BIT
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#endif
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enum regnum_t ENUM8BIT
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{
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R0, R1, R2, R3, R4, R5, R6, R7, SP=R7,
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E0, E1, E2, E3, E4, E5, E6, E7,
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R0H, R1H, R2H, R3H, R4H, R5H, R6H, R7H,
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R0L, R1L, R2L, R3L, R4L, R5L, R6L, R7L,
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ER0, ER1, ER2, ER3, ER4, ER5, ER6, ER7,
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// don't change registers order above this line
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MACL, MACH,
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PC,
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CCR, EXR,
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rVcs, rVds, // virtual registers for code and data segments
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VBR, SBR, // base or segment registers
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};
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//---------------------------------
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// Operand types:
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/*
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o_reg 1 Register direct
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Rn
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x.reg
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o_phrase 2 Register indirect
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@ERn
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x.phrase contains register number
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x.phtype contains phrase type (normal, post, pre)
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o_displ 3 Register indirect with displacement
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@(d:2,ERn)/@(d:16,ERn)/@(d:32,ERn)
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x.reg, x.addr, disp_16, disp_32, disp_2
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o_displ 4 Index register indirect with displacement
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@(d:16, RnL.B)/@(d:16,Rn.W)/@(d:16,ERn.L)
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@(d:32, RnL.B)/@(d:32,Rn.W)/@(d:32,ERn.L)
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x.displtype = dt_regidx,
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x.reg,
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x.addr - disp_16, disp_32, idx_byte/word/long
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o_phrase 5 Register indirect with post-inc/pre-dec/pre-inc/post-dec
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@ERn+/@-ERn/@+ERn/@ERn-
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o_mem 6 Absolute address
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@aa:8/@aa:16/@aa:24/@aa:32
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x.memtype = @aa:8 ? mem_sbr : mem_direct
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x.addr
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o_imm 7 Immediate
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#x:2/#xx:3/#xx:4/#xx:5/#xx:8/#xx:16/#xx:32
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#1/#2/#4/#8/#16
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x.value
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o_near 8 Program-counter relative
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@(d:8,PC)/@(d:16,PC)
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o_pcidx 9 Program-counter relative with index register
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@(RnL.B,PC)/@(Rn.W,PC)/@(ERn.L,PC)
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x.reg
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o_mem 10 Memory indirect
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@@aa:8
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x.memtype = mem_ind
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x.addr
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o_mem 11 Extended memory indirect
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@@vec:7
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x.memtype = mem_vec7
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x.addr
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o_reglist Register list
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x.reg, x.nregs
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o_displ first operand of MOVA insn
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@(d16,<EA>.[BW])/@(d32:<EA>.[BW])
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x.displtype = dt_movaop1,
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x.addr,
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x.szfl - disp_16/disp_32/idx_byte/idx_word
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x.idxt - <EA> type
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<EA> type:
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o_reg - x.reg EQ to o_regidx
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o_phrase - x.phrase,x.idxdt
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o_displ - x.reg,x.value,x.idxsz,x.idxdt
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o_regidx - x.reg,x.value,x.idxsz,x.idxdt
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o_mem - x.value,x.idsz,x.idxdt
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*/
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#define o_reglist o_idpspec0
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#define o_pcidx o_idpspec1
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#define phtype specflag1 // phrase type:
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const int ph_normal = 0; // just simple indirection
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const int ph_pre_dec = 0x10; // -@Rn ^ 3 -> @Rn+
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const int ph_post_inc = 0x13; // @Rn+
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const int ph_pre_inc = 0x11; // +@ERn
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const int ph_post_dec = 0x12; // @ERn-
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#define displtype specflag1 // displ type:
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const int dt_normal = 0; // Register indirect with displacement
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const int dt_regidx = 1; // Index register indirect with displacement
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const int dt_movaop1 = 2; // first operand of MOVA insn
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#define szfl specflag2 // various operand size flags
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// index target
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const int idx_byte = 0x01; // .b
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const int idx_word = 0x02; // .w
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const int idx_long = 0x04; // .l
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// size of operand displ
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const int disp_16 = 0x10; // 16bit displacement
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const int disp_24 = 0x20; // 24bit displacement
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const int disp_32 = 0x40; // 32bit displacement
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const int disp_2 = 0x80; // 2bit displacement
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#define memtype specflag1 // mem type:
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const int mem_direct = 0; // x.addr - direct memory ref
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const int mem_sbr = 1; // SBR based @aa:8
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const int mem_vec7 = 2; // @@vec:7
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const int mem_ind = 3; // @@aa:8
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#define nregs specflag1 // o_reglist: number of registers
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// MOVA Op1 store
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#define idxt specflag3 // MOVA: optype_t of index
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#define idxsz specflag4 // MOVA: size of index
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#define idxdt specval // MOVA: index phtype,displtype,memtype
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//------------------------------------------------------------------
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const uint16 aux_none = 0; // no postfix
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const uint16 aux_byte = 1; // .b postfix
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const uint16 aux_word = 2; // .w postfix
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const uint16 aux_long = 3; // .l postfix
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//------------------------------------------------------------------
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#define UAS_HEW 0x0001 // HEW assembler
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//------------------------------------------------------------------
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ea_t calc_mem(const insn_t &insn, ea_t ea); // map virtual to physical ea
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ea_t calc_mem_sbr_based(const insn_t &insn, ea_t ea); // map virtual @aa:8 physical ea
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void idaapi h8_segend(outctx_t &ctx, segment_t *seg);
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int idaapi h8_is_align_insn(ea_t ea);
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bool idaapi create_func_frame(func_t *pfn);
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int idaapi is_sp_based(const insn_t &insn, const op_t &x);
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bool idaapi is_return_insn(const insn_t &insn);
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int is_jump_func(const func_t *pfn, ea_t *jump_target);
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int may_be_func(const insn_t &insn); // can a function start here?
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int is_sane_insn(const insn_t &insn, int nocrefs);
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bool idaapi h8_is_switch(switch_info_t *si, const insn_t &insn);
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//------------------------------------------------------------------
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struct h8_iohandler_t : public iohandler_t
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{
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h8_iohandler_t(netnode &nn) : iohandler_t(nn) {}
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virtual void get_cfg_filename(char *buf, size_t bufsize) override;
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};
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struct h8_t : public procmod_t
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{
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netnode helper;
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h8_iohandler_t ioh = h8_iohandler_t(helper);
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proctype_t ptype = none; // contains all bits which correspond
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// to the supported processors set
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char show_sizer = -1;
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uchar code = 0;
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uchar code3 = 0;
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bool flow = false;
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virtual ssize_t idaapi on_event(ssize_t msgid, va_list va) override;
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inline bool advanced(void) { return (ptype & MODE_MASK) != 0; }
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inline bool is_h8s(void) { return (ptype & (P2000|P2600)) != 0; }
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inline bool is_h8sx(void) { return (ptype & PSX) != 0; }
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inline bool is_tiny(void) { return (ptype & SUBM_TINY) != 0; }
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inline regnum_t r0(void) { return advanced() ? ER0 : R0; }
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inline bool is_hew_asm(void) const
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{
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return (ash.uflag & UAS_HEW) != 0;
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}
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void load_symbols(void);
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const char *find_sym(ea_t address);
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const char *set_idp_options(
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const char *keyword,
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int /*value_type*/,
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const void * /*value*/,
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bool /*idb_loaded*/);
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void set_cpu(int cpuno);
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int get_displ_outf(const op_t &x, flags_t F);
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ea_t trim_ea_branch(ea_t ea) const; // trim address according to proc mode
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void h8_header(outctx_t &ctx);
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void trimaddr(op_t &x);
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void opatHL(op_t &x, op_dtype_t dtyp);
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void opdsp16(insn_t &insn, op_t &x, op_dtype_t dtyp);
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void opdsp32(insn_t &insn, op_t &x, op_dtype_t dtyp);
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bool read_operand(insn_t &insn, op_t &x, ushort flags);
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bool map014(insn_t &insn);
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bool map4(insn_t &insn);
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int ana(insn_t *pinsn);
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int exit_40(insn_t &insn);
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int exit_54_56(insn_t &insn, uint8 rts, uint8 rtsl);
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int exit_59_5D(insn_t &insn, uint16 jump, uint16 branch);
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int exit_7B(insn_t &insn);
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int h8sx_03(insn_t &insn);
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int h8sx_0A(insn_t &insn);
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int h8sx_1A(insn_t &insn);
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int h8sx_6A(insn_t &insn);
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void handle_operand(const insn_t &insn, const op_t &x, bool is_forced, bool isload);
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int h8sx_6B(insn_t &insn);
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int h8sx_78(insn_t &insn);
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int h8sx_79(insn_t &insn);
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int h8sx_7A(insn_t &insn);
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bool h8sx_010D(insn_t &insn);
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bool h8sx_010E(insn_t &insn);
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bool insn_ldc(insn_t &insn, uint8 byte2, regnum_t reg);
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bool h8sx_01_exr(insn_t &insn);
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bool insn_mova(insn_t &insn);
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int insn_mova_reg(insn_t &insn, uint8 opcode, uint8 rs, bool is_reg_equal);
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bool h8sx_01_other(insn_t &insn);
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bool insn_addx_imm(insn_t &insn, op_t &x, uint8 byte2, uint8 byte3, uint16 mask, bool check_byte3);
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bool insn_bra(insn_t &insn, uint8 byte2, uint8 byte3);
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bool insn_bfld_bfst(insn_t &insn, uint8 byte2, uint8 byte3, bool is_bfld);
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bool use_leaf_map(insn_t &insn, const struct map_t *m, uint8 idx);
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bool op_from_byte(insn_t &insn, op_t &x, uint8 byte2);
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bool read_1st_op(insn_t &insn, uint8 byte2, uint8 byte3_hiNi);
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bool op_phrase(const insn_t &insn, op_t &x, uint8 reg, int pht, op_dtype_t dtype=dt_byte);
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bool op_displ_regidx(insn_t &insn, op_t &x, uint8 selector, bool is_32, uint8 reg);
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int emu(const insn_t &insn);
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int h8_get_frame_retsize(const func_t *);
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int h8sx_7C(insn_t &insn);
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int h8sx_7D(insn_t &insn);
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bool h8sx_010_01dd(insn_t &insn, uint16 postfix);
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bool h8sx_ldm(insn_t &insn);
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bool insn_mac(insn_t &insn);
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bool insn_tas(insn_t &insn);
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bool op_phrase_prepost(const insn_t &insn, op_t &x, uint8 reg, uint8 selector);
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bool op_phrase_displ2(const insn_t &insn, op_t &x, uint8 reg, uint8 displ);
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int h8sx_01(insn_t &insn);
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bool h8sx_010_00dd(insn_t &insn);
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int h8sx_7E(insn_t &insn);
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int h8sx_7F(insn_t &insn);
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int unpack_8bit_shift(const map_t *m, insn_t &insn, uint16 itype, uint16 itype2);
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int h8sx_10(insn_t &insn);
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int h8sx_11(insn_t &insn);
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bool h8sx_0108(insn_t &insn);
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bool h8sx_0109_010A(insn_t &insn,op_t ®op, op_t &genop);
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int h8sx_0F(insn_t &insn);
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int h8sx_1F(insn_t &insn);
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void add_code_xref(const insn_t &insn, const op_t &x, ea_t ea);
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void h8_assumes(outctx_t &ctx);
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void trace_sp(const insn_t &insn) const;
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bool get_op_value(uval_t *value, const insn_t &_insn, const op_t &x) const;
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bool spoils(const insn_t &insn, int reg) const;
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void check_base_reg_change_value(const insn_t &insn) const;
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void h8_segstart(outctx_t &ctx, segment_t *Srange) const;
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void h8_gen_stkvar_def(outctx_t &ctx, const member_t *mptr, sval_t v) const;
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void h8_footer(outctx_t &ctx) const;
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void load_from_idb();
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};
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extern int data_id;
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#endif // _H8_HPP
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